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hamish@cloud.net.au wrote: > > Is this the simple solution to some of the bugs in 4.2i ? :-| > > I've found 4.2i to be significantly more stable on Windows 2000 (SP2) > than Windows NT (SP6a). Definitely ! Did you install Win2000 SP3 and 4.2i SP3 ? ;-) cheersArticle: 47226
>I do not think it shipped, since
>there is no flooding of Answers
>yet, and no SP-1 released yet.
Check again - it appears both your
conditions are met...
Ken Ryan
Smiths Aerospace
[wishing I worked for someplace
like Aardvark Industries so
I'd be higher up the shipping
queue... :-/ ]
Article: 47227emanuel stiebler <emu@ecubics.com> wrote: : rickman wrote: :> :> Speaking of MS, anyone know what little tricks they are using to get :> companies to switch from 98, ME, NT and 2000 to XP? : Bike chains ? : ;-) :> I just can't belive :> they are going to sit by and let everyone keep using the old OS with :> licences that can't be well enforced. :> : They are probalbly sitting there, while we walk to linux ;-) : As soon, as xilinx ports all the stuff as native applications ... If you consider the win32 api as another toolkit like motif, qt, gtk or others, a winelib application is a native application too... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 47228
This is my last note on this subject. 1. I like synchronous designs, they are your only reasonable choice in 99% of all cases. But there are a few cases where a savvy designer can get away with a safe ripple-clock design. Not often, but occasionally. 2. The million dollar mask set in 130 nm fully digital technology will become even more expensive in the upcoming 100 nm technology. That is the direction, if you want to be on the cutting edge. Luckily, FPGAs can amortize these costs over huge production runs. 3. This has been a lively discussion, started by an innocent suggestion. Peter Alfke ================================== Blackie Beard wrote: > This is my last note on this thread. Chip express doesn't > say it takes 30 masks. Sounds like he's getting the > bendover special if he's paying a million for a fully > synchronous, pure digital asic, even if you had a million > asic gates, it shouldn't cost that much. IMHO. > > BB > ============================================= > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3D8AB923.2A77F16D@yahoo.com... > > Peter Alfke wrote: > > > > > > Blackie Beard wrote: > > > > > > > Keep your design synchronous, or it will be > > > > a real beach to get an ASIC made later. <snip> > > > > > > How many people can still afford an ASIC? > > > > > > I don't want to start a flame, am just curious. > > > At 130 nm just the mask set (~30 masks) is close to a million dollars, > > > excluding design and verification efforts (That's a basic fact, we pay > this all > > > the time)... > > > Is this irrelevant? > > > Just asking, I may be living in a biased environment. Please no flames ! > > > > > > Peter Alfke > > > > So just go with a 210 nm process where they are begging you to use their > > fabs. Maybe they are having a special and will give the masks away for > > free!!! B^) > > > > The OP was using an XCS05! I don't think that is done in anything close > > to a 130 nm process, is it? What are we talking, 250 nm or bigger, > > right? > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47229
rickman wrote: > > Let me get this straight. version 4.x supported 98, ME(?), NT, 2000, > but definitely NOT XP. Now that they are adding XP, they are also > dropping, 98, ME and NT??? I've been through the hoops of supporting multiple versions of Windows in my day job. It's not like supporting Linux variants, trust me. As for the tricks being used to force users to abandon the older operating systems for the newer XP? It's simple. Newer PCs increasingly are no longer are able to run NT. If you want a stable work environment, start getting used to the idea of moving to Linux. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." abuse@xo.com uce@ftc.govArticle: 47230
In article <3D8B7274.C47E14C2@xilinx.com>, Peter Alfke <peter@xilinx.com> wrote: > The million dollar mask set in 130 nm fully digital technology will > become even more expensive in the upcoming 100 nm technology. That > is the direction, if you want to be on the cutting edge. Luckily, > FPGAs can amortize these costs over huge production runs. Since mask making is a largely sequential process (E-beams to cut the masks or similar tasks), they are necessarily hugely expensive. As features get smaller, the masks get correspondingly more complex, as the dies themselves tend to remain roughly the same After all, how many people keep the circuits constant and shrink the die? If this was a productive way for most, we'd all be using Via C3 processors.[1] Additionally, the finer processes add more metal layers -> more fabrication steps -> more masks required. So there are three things which drive up the cost: Finer features on the masks, more features on the masks, and more total masks required. Joy. [1] Which is the old Cyrex Pentium/PPro competitor process shrunk to .13 micron and coupled with good sized caches. A "whopping" 50 mm^2 die and 5 watts at full power, including 64K Icache, 64K Dcache, and 64K victim cache. Pretty much as good a power/performance or better than Transmeta, and awfully low cost too (you can get CPU and very functional motherboard, retail, for $130). -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 47231
Hi, I want make a hard disk drive from SDRAMs,which use IDE interface to connect to pc.and have a battery to keep the data when power off. is there any logic core for FPGA-IDE interfaceing?? any one have try that before?? please give me some suggestion, thank a lot!!!Article: 47232
> > If you want a stable work environment, start getting used to the > idea of moving to Linux. > -- > Steve Williams "The woods are lovely, dark and deep. This is exactly what I think to do. The only doubt that I have is that I use the Suse Linux and Xilinx required Red Hat. I don't know the technical question that induced Xilinx to drop NT but they are very strange. By now I have to put 2 OS on my desktop because old uP emulator doesn't work on W2000 and the up to date of the software is not possible and convenient. Regards GiuseppeArticle: 47233
Giuseppeł wrote: >>If you want a stable work environment, start getting used to the >>idea of moving to Linux. >>-- >>Steve Williams "The woods are lovely, dark and deep. > > > This is exactly what I think to do. > The only doubt that I have is that I use the Suse Linux and Xilinx required > Red Hat. Xilinx only "officially" requires Redhat. That means they provide Redhat specific installation instructions. But don't worry. It should work fine on pretty much any current Linux distribution, with a current version of Wine. Really, the Xilinx tools work pretty good under Wine. I used to have a dual boot system, but Xilinx/Wine (as well as Actel/Wine, the other tool chain I use) has been working so well that I dumped Windows about 6 months. -- My real email is akamail.com@dclark (or something like that).Article: 47234
I'm using a Xilinx CoolRunner XPLA3 CPLD, and on one of the inputs I have a push-button switch. When the button is pressed, the pin connects to +3V (logic one). When the button is not pressed, the circuit is open. I want a logic zero to occur in this case, so I'm going to use a pulldown resistor. Does anyone know what resistor value I should use for this? (note -- later I'll probably just use a toggle switch to choose between 3V and gnd, but I don't have one at the moment.)Article: 47235
Duane Clark wrote: > Simon Gornall wrote: > >> Up until now I've been using the Webpack software available free from >> Xilinx. I'm actually pretty happy with it - the sole problem is that I >> have to reboot into Windows to run it ... this is a major reason for >> me choosing to "do something else" :-) >> >> I noticed that ISE 5.1 is available under linux (hurrah!) at last, and >> was wondering: > > > As mentioned above (in "ISE 5.1 Linux?", ISE 5.1 needs Wine to run. > WebPack will actually install and run under a current CVS version of > Wine too. I run it and the similar ISE program manager. They both > actually work pretty good. Hmm. My "mileage varies". I get a crash either when running 'wine WebPACK_42wp30_fpga_installer.exe', or when unpacking that with unzip, and running 'wine Setup.exe'. Notepad seems to work fine, so I suppose it's just not working with the fpga stuff :-( I get a few dialogue boxes on the screem, then it tells me: fixme:seh:check_resource_write Broken app is writing to the resource data, enabling work-around .. and the InstallShield dialgoue box complains about a missing engine. It's possible this is the OS - I'm running Mandrake 8.2 at home, but I'll give it a go on the Redhat 7.3 in the office tomorrow. Tx, SimonArticle: 47236
The resistor value is uncritical, anything between 1 kilohm and 33 kilohm would be my choice. But: Whenever you press and whenever you release the button, the contact will bounce, which means you seem to make multiple switch closures and openings. Be aware of this bounce. A toggle switch can avoid this, if you make sure that the pin maintains its level while the switch is open (traveling). If you have a spare output, use it to drive the signal input through a kilohm resistor. If not, you can use the input pin as I/O, effectively creating a latch, using the switch to brute-force it over. The current spike is very short, a ns or two... Peter Alfke John wrote: > I'm using a Xilinx CoolRunner XPLA3 CPLD, and on one of the inputs I > have a push-button switch. When the button is pressed, the pin > connects to +3V (logic one). When the button is not pressed, the > circuit is open. I want a logic zero to occur in this case, so I'm > going to use a pulldown resistor. Does anyone know what resistor value > I should use for this? > > (note -- later I'll probably just use a toggle switch to choose > between 3V and gnd, but I don't have one at the moment.)Article: 47237
Stephen Williams wrote: > > rickman wrote: > > > > > Let me get this straight. version 4.x supported 98, ME(?), NT, 2000, > > but definitely NOT XP. Now that they are adding XP, they are also > > dropping, 98, ME and NT??? > > I've been through the hoops of supporting multiple versions of > Windows in my day job. It's not like supporting Linux variants, > trust me. > > As for the tricks being used to force users to abandon the older > operating systems for the newer XP? It's simple. Newer PCs increasingly > are no longer are able to run NT. > > If you want a stable work environment, start getting used to the > idea of moving to Linux. That sounds like a great concept, but in the real world, Linux is hardly supported. Xilinx only supports it running with WINE IIRC and they have no free version of tools for Linux. Anyone know if the Linux version has more or fewer bugs? Seems to me it would have most of the Windows bugs and also a few special to Linux. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47238
Hal Murray wrote: >>The reliability-based lifetime of working silicon is much longer >>than 20 years. Silicon does not really age, if overstresses are >>avoided. > > Are the failure rates of silicon significantly dependent on > temperature? (like tantalum caps, for example) > > I'm interested in the case where there are no metal migration > type bugs in the design. (I realize that may not be a valid > assumption.) Are there always things like thin spots in wires > that make the tail of the curve temperature dependent? Hi Hal, I've studied the reliability numbers for a lot of the FPGA devices from multiple manufacturers and compared them with commercial, military, and hi-rel devices over the past 40 years. For modern devices, the reliability per commercial-grade device is quite good by any standard, using the published data. From empirical data in the lab, they do appear to be superior to even the Class S SSI/MSI devices of 15 years ago. When looking at reliability levels and comparing them historically as a function of gate count, current reliability levels are simply superb, in my opinion. As a general rule, failure rates are a function of temperature and there are charts and tables that give various accelleration factors for temperature and voltage stress. While normally higher temperatures lead to increased failure rates, with a 2 times increase for a 10 degree C rise as a general rule of thumb, that's not always the case and depends on the structures involved. Electromigration always is an issue and many of the commercially produced devices would not meet standard military specifications for step coverage, years ago, although that is less of an issue now because of planarized processes. Then again, with increased density, smaller feature sizes, high clock frequencies, and very high current levels, it's again a concern in general. The device designers are supposed to take this into account to guarantee long-term reliability. Again, from the published data and empirical data, it's just hard to kill these devices when put into normal use. DOA devices are not common; they were not uncommon with hi-rel devices 15 years ago. One thing to keep in mind is long-term storage for non-volatile memory structures, where you might see a guaranteed spec level at worst-case conditions of 10 years. For some applications, such as geosynchronous communications satellites, they are designed for a minimum operational life of from aruond 12-15 years, with the limited resource typically being station-keeping fuel. In cases such as this, qualification over a limited temperature range, for example, may be needed. Anyways, just a quick babble ... -- rk, Just an OldEngineer The ability to improve a design occurs primarily at the interfaces. This is also the prime location for screwing it up. -- from Akin's Laws of Spacecraft DesignArticle: 47239
rickman wrote: > Stephen Williams wrote: >>If you want a stable work environment, start getting used to the >>idea of moving to Linux. > > That sounds like a great concept, but in the real world, Linux is hardly > supported. Xilinx only supports it running with WINE IIRC and they have > no free version of tools for Linux. Anyone know if the Linux version > has more or fewer bugs? Seems to me it would have most of the Windows > bugs and also a few special to Linux. > First, I didn't say "Jump right now!" But I think the situation is better then you think. We're starting to see vendors arguing over who supports Linux more:-) And Xilinx' turnaround on the Linux issue has nearly given me whiplash, but it seems real, and I'm willing to bet that in the not too distant future, Linux support will be touted in bold letter, with Windows getting a footnote. Also, don't knock the WINE support. WINE is not bad at all, it is really just WIN32 support for Linux. It is *not* an emulator, so performance need not be bad. Really, the customers (us) just need to continually nag the vendors until they get it. And given the choice, would you rather nag them to support NT4.0, or Linux?-) -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." abuse@xo.com uce@ftc.govArticle: 47240
"Giuseppe?" <gziggio.pleasedontsendmeanything@tin.it> wrote: > The only doubt that I have is that I use the Suse Linux and Xilinx required > Red Hat. I don't see anything about Red Hat-specific about the installation process; you just run the installer under Wine. It should work in SuSE, Debian, etc just fine. Having said that, I tried it under Debian and didn't get too far. The installer got to the part where it would copy the files, then sat at 0% forever. The progress bar kept changing colour but never increased beyond 0%. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 47241
emanuel stiebler <emu@ecubics.com> wrote: > hamish@cloud.net.au wrote: >> Is this the simple solution to some of the bugs in 4.2i ? :-| >> >> I've found 4.2i to be significantly more stable on Windows 2000 (SP2) >> than Windows NT (SP6a). > > Definitely ! Did you install Win2000 SP3 and 4.2i SP3 ? > ;-) I hear that caused the BSOD.. whoops. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 47242
Stephen Williams wrote: > > First, I didn't say "Jump right now!" But I think the situation is > better then you think. We're starting to see vendors arguing over > who supports Linux more:-) Sorry, I didn't mean to make it sound like I would never switch. I agree, just the fact that Xilinx supports Linux at all is a major turn around. And other vendors, HDL synthesis for example, do a much better job of providing support. > And Xilinx' turnaround on the Linux issue has nearly given me whiplash, > but it seems real, and I'm willing to bet that in the not too distant > future, Linux support will be touted in bold letter, with Windows > getting a footnote. Agreed. I just which they supported the Webpack free tools. That will be a major part of our marketing efforts for our boards with FPGAs on them. It is a lot easier to sell HW when the development SW is free. > Also, don't knock the WINE support. WINE is not bad at all, it is > really just WIN32 support for Linux. It is *not* an emulator, so > performance need not be bad. Mostly true, but it is not perfect and Xilinx has commited to fixing "bugs" under one version of Linux only. Hamish's messages say a little about that. > Really, the customers (us) just need to continually nag the vendors > until they get it. And given the choice, would you rather nag them > to support NT4.0, or Linux?-) Nagging is useful. But a company like Xilinx moves slowly in some respects and the size of the customer makes a much bigger difference than the volume with which you nag. There are some very good listeners at Xilinx. Peter and Austin are good at it as is Mark Baker and Kim Goldblatt. But they can't turn the bow of the HMS Xilinx by themselves. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47243
You must be able clock the I/O cells on both clock edges (reading from DDR). Other than that, use a 2x clock, and you're good to go. SH7 On Thu, 19 Sep 2002 19:18:59 -0700, "James Wong" <james88664@mail.com> wrote: >Hi, >I am new to designing in FPGA and CPLD. What are the issues to consider when designing DDR input and output logic in CPLD? >Thanks, >JamesArticle: 47244
> I don't see anything about Red Hat-specific about the installation > process; you just run the installer under Wine. It should work in SuSE, > Debian, etc just fine. > At page 2-2 of the ISE4.2 version is clearly indicated RedHat Linux 7.2. I still waiting the upgrade to 5.1, so I don't know if anything is changed. Regards GiuseppeArticle: 47245
Looks like part of the performance problem in v4.2 is a
reappearance of the so called RPM zippering problem. That
is, if you have flip-flops placed with RLOCs, then use
synthesized LUTs you would expect the placer to place the
LUTs in the slices with the flip-flops. It does not, so in
a design where you've placed the flip-flops in a dense
pattern, you'd espect good performance. Instead,the placer
is putting the LUTs outside of that dense pattern, killing
the density and performance. (this was a problem with early
versions of the M1 floorplanner that finally was fixed in
the 3.1 tools). Has anyone else seen this? and 2) more
importantly, does the problem exist in the 5.1 tools (which
I haven't received yet).
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
Article: 47246Stephen Williams wrote: > > > Really, the customers (us) just need to continually nag the vendors > until they get it. And given the choice, would you rather nag them > to support NT4.0, or Linux?-) > > -- ... and of course nag the entire EDA industry into dropping the ludicrous price differential between Windoze and Unix/Linux versions, they're all built from the same sources and mostly developed under Linux anyway. Xilinx, I hope & pray, won't do this when they go Linux native, Synplify is o.k. I think (at least for Pro, not sure about non-Pro) but ModelSim still has the ~4x mark-up ... or did the last time I checked.Article: 47247
Duane Clark <junkmail@junkmail.com> wrote: : Giuseppeł wrote: :>>If you want a stable work environment, start getting used to the :>>idea of moving to Linux. :>>-- :>>Steve Williams "The woods are lovely, dark and deep. :> :> :> This is exactly what I think to do. :> The only doubt that I have is that I use the Suse Linux and Xilinx required :> Red Hat. : Xilinx only "officially" requires Redhat. That means they provide Redhat : specific installation instructions. But don't worry. It should work fine : on pretty much any current Linux distribution, with a current version of : Wine. : Really, the Xilinx tools work pretty good under Wine. I used to have a : dual boot system, but Xilinx/Wine (as well as Actel/Wine, the other tool : chain I use) has been working so well that I dumped Windows about 6 months. Duane, what is your option to download the bitstream to the FPGA under Linux? I looked hard at running impact.exe under wine, but as impact probably uses a windriver.sys file to access the parallel port, it seems not feasable with wine. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 47248
Hello, My design has a common low cost crystal oscillator. It uses two inverters HC7404 and a few caps & two res. Can the inverter chip be replace by the FPGA. Can I simply put the crystal across two IO pins ( I am using a Spartan IIE ) and configurae them as an inverter ( while keeping the caps and the res(s) ) ? Sincerely DanArticle: 47249
rk <stellare@nospamplease.erols.com> wrote: ... : Anyways, just a quick babble ... Instructibve babble :-) -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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