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Wojciech Piechowski <wojt@gnu.univ.gda.pl> wrote in message news:<Pine.LNX.4.21.0209131147270.4449-100000@gnu.univ.gda.pl>... > hello! > > I've just read an interesting thread about metastability and this made me > think about making a hardware random bit generator. Exploiting > metastability seems to be interesting. Just put to D an alternating > sequence which toggles with clock. Add some smart routing to make it hit > the hold window. And have a long time thinking how to read metastable Q > without passing metastability to the rest of the circuit.... > > Has anyone done something like this? Or heard about it? I'm thinking about > implementing it. Any help and comments appreciated. Hi. Just wondering... How about generating an unknown clock by feeding a not gate back (most synthesis software won´t allow, but you can use 2 pins for it if you have...)? You could read the bits right out of it, or using it in a counter. The frequency is dependant on temperature, but that sould be no problem. In a coolrunner xpla3 this freq is about 76MHz. Bye...Article: 47001
meta wrote: > > The spacing between neighboring resistor is about 10um. > Bubble jet printers use larger heaters. It is a challenge to > fabricate such tiny 10um heaters. I can imagine :) Did you want to use the silicon as the heater ( water on wafer :), or as the driver to the separate heater matrix ? What hot spot termerature must it tolerate ? CMOS has a common power dissapation formula, P = Cpd * Vcc^2 * fi; Cpd is the power dissipation capacitance, a virtual value dervied from measurements. So you can control local heat flux by Vcc and by clock frequency. Getting 'clean edges' to power zones would be the challenge, and in modern devices, this heat is actually some depth below the surface ( many layers down ) - jgArticle: 47002
Larry Doolittle wrote: > > On Fri, 13 Sep 2002 15:16:52 -0400, rickman <spamgoeshere4@yahoo.com> wrote: > > > >That may all be great in theory, but in practice you can't make it > >work. As someone else pointed out, this is the type of circuit that > >will be very sensitive to noise, espeically on the power bus. You are > >much more likely to get a clock noise measurement circuit than a random > >number generator. > > Somebody needs to try this out, and get some real experimental > data. Either result is interesting. ;-) > > - Larry It has been tried in other sorts of circuits. Using metastability is no different than using an ADC to measure the noise of a diode. The trick is to keep manmade "noise" out of the measurement so you are measuring the "natural" noise. This is a VERY non-trivial problem. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47003
Ricardo Wiggers wrote: > > Wojciech Piechowski <wojt@gnu.univ.gda.pl> wrote in message news:<Pine.LNX.4.21.0209131147270.4449-100000@gnu.univ.gda.pl>... > > hello! > > > > I've just read an interesting thread about metastability and this made me > > think about making a hardware random bit generator. Exploiting > > metastability seems to be interesting. Just put to D an alternating > > sequence which toggles with clock. Add some smart routing to make it hit > > the hold window. And have a long time thinking how to read metastable Q > > without passing metastability to the rest of the circuit.... > > > > Has anyone done something like this? Or heard about it? I'm thinking about > > implementing it. Any help and comments appreciated. > > Hi. > > Just wondering... How about generating an unknown clock by feeding a > not gate back (most synthesis software won´t allow, but you can use 2 > pins for it if you have...)? You could read the bits right out of it, > or using it in a counter. The frequency is dependant on temperature, > but that sould be no problem. In a coolrunner xpla3 this freq is about > 76MHz. > > Bye... Same problem as the others, getting rid of the external noise that will make an oscillator like this tend to couple with any other oscillators in the circuit. But even if you could make this unit perfectly isolated and stable, it would produce a pattern defined by the ratio of this clock frequency to the sampling clock frequency, not exactly random, but rather pseudo random. The difference is that I can't predict a random sequence. But if I know enough about the system and its state, I can predict the output of a pseudo random generator, further it is repeatable. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47004
meta wrote: > > yes, size is a big problem. The spacing between neighoring resistors should > be > less than 10um, which means possibly huge heat flux. At this point I don't know that you can do what you want. You said you needed only 10 x 10 heaters and you need them within a 100 um square area. I don't know the CLB spacing on an FPGA which would be required to implement this. But this area is only a tiny portion of the whole chip. Anyone know the size of the CLB spacing on a Virtex, SpartanII or VirtexII die? I think we can work with the smallest one in each family. Meta, you didn't answer my question about the contact of the die with the water? How do you plan to keep the water from ruining the die? I am not familiar with the thermal conductivity of water, is this much heat enough to make the water boil? If so, you may have a problem cooling the chip. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47005
Just spend the money to buy the JTAG parallel cable. You will have to manually wire your chip plugs to the inputs on the cable. It works great with that iMPACT software Xilinx ships. "Michael Ardai" <n1ist@panix.com> wrote in message news:allnd2$ksp$1@panix3.panix.com... > I have a design that uses Xilinx 18v00 PROMs (18V01 and 18V04) to boot > some FPGAs. I would like to be able to field-update them thru their > JTAG port but would rather not embed Xilinx's eisp software in my system. > Does anyone have any info on the programming algorithm for these or > similar PROMs? I already can handle sending and receiving TAP commands > and data. > > Thanks. > /mike > n1ist@arrl.net >Article: 47006
Check starbridgesystems.com for something similar. "Christopher Saunter" <christopher.saunter@durham.ac.uk> wrote in message news:akl6b6$p16$1@sirius.dur.ac.uk... > Greetings All, > > I just saw the following post on comp.dsp: > http://groups.google.com/groups?q=ni+niweek+labview+fpga&hl=en&lr=&ie=UTF-8& selm=3D6D58E5.1BE95798%40NAESPAM.yahoo.com&rnum=2 > > It looks like National Instruments LabVIEW code being targeted to Xilinx > devices. LabVIEW offers a high level graphical programming language, and > perhaps the way it is organised and used makes it more likely to benefit > from automated targeting to FPGAs than 'c' style languages? > > I doubt it'll change the way I use FPGAs (gimmie LUTs... ;-) but I can see > it going down well with many LabVIEW users who need to produce fast data > processing hardware etc. > > --- > > cds > >Article: 47007
spyng wrote: > > hi all, > just a quick question, for a completely random read ( to different row > /bank /column ) to DDR SDRAM RAM the sustainable data rate is ~ 70 ns, > BL=4. ( base on Micron MT46V8M16-8, tRC = 70 ns, clk=100 mhz). > > right ? I have not used DDR RAM before, but I expect it is very similar to SDRAM which I have used. In the general case, I think you are right. But if you can guarantee that each access is to a different bank, you can overlap accesses, also assuming that you can start one access before the previous one has completed. As a little trick, if you don't do much writing, you can keep duplicate copies in each of the four (?) banks and then rotate through them as you do the reads. This is somewhat like using multiple chips to speed up parallel reads, but you don't need the multiple chips :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47008
I'm working on getting the Virtex/EDIF code generator for Icarus Verilog in line with the improved synthesis of combinational logic, and I'm worrying myself (probably needlessly) over the implementation of 4:1 and 8:1 mux devices. What I've done so far is emit for 4:1 mux devices two LUT3 and a MUXF5. This superficially seems pretty optimal, although I can also change it to generate 2 LUT4 and an XORCY to generate the same function. For 8:1 MUX devices, I imagine generating 4 LUT3, 2 MUXF5 and a MUXF6. This too seems pretty optimal on the surface. For 16:1 and wider, I see no alternative to recursively nesting the right combination of 8:1, 4:1 and 2:1 subnets I've already described. Gosh, muxes are pretty nasty, I can imagine having nightmares over the routing problems these create :-/ So does all this sound plausible? -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." abuse@xo.com uce@ftc.govArticle: 47009
www.opencores.org has a nice verilog core for an SDRAM controller which intelligently trys to reuse pre-existing open banks to speed up random access. If your 'random' access is within predefined modest limits you can usually engineer a scheme where you maintain some lookahead preemptive opening of new banks. Typically this would only be useful if accesses are within one row ( e.g 512 columns x 4 banks = 2048) PaulArticle: 47010
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<alt7df$ufrk$1@ID-84877.news.dfncis.de>... > "Muthu" <muthu_nano@yahoo.co.in> schrieb im Newsbeitrag > news:28c66cd3.0209122001.79bedf3e@posting.google.com... > > Hi, > > > > what is the difference between BUFT and TBUF ???? > > TBUF is a tristate drive for internal nets, a BUFT a tristate driver in the > IOB for signal going outside the IC. Hi, Thanks for the info. and one of the xilinx answer record suggest that if the multiplexer has more than 7 inputs, it is better to design Mux with TBUFs. But i tried once. The problem was, the routing delay is more.. because each CLBs has only 2 TBUFs. Here i need to implement a 64:1 multiplexer for 200 MHz speed. Is there any way to acheive this speed ? Can anyone give me an general idea of Using TBUFs. Since it causes more delays due to its nature of placements, where it will be used. Multiplexer design usign TBUFs is the one way.. But it is not working to the expected frequency. Thanks in advance. Best regards, MuthuArticle: 47011
"Muthu" <muthu_nano@yahoo.co.in> schrieb im Newsbeitrag news:28c66cd3.0209132359.6c639ce6@posting.google.com... > Hi, > > Thanks for the info. and one of the xilinx answer record suggest that > if the multiplexer has more than 7 inputs, it is better to design Mux > with TBUFs. But i tried once. The problem was, the routing delay is > more.. because each CLBs has only 2 TBUFs. > > Here i need to implement a 64:1 multiplexer for 200 MHz speed. Is > there any way to acheive this speed ? As someone stated before, the TBUFs are relicts from the good old time. They where good as long as they lasted. In modern ICs like Virtex-E and much more Virtex-II/PRO, MUXes are better made of regular LUTs. But AFAIK even in Virtex-II, you will not get 200MHz in a single stage MUX. You will have to pipeline. -- MfG FalkArticle: 47012
I am a new comer to VHDL design, and I need to some sort of clock divison scheme that can divide a clock by noninteger values such as 3.33. Not simple values like 1.5,2.5 etc. Can anyone give me some suggestions or ways of achieving this? Please send reply to my email as well Thanks in advance Regards, BruceArticle: 47013
In article <28c66cd3.0209132359.6c639ce6@posting.google.com>, Muthu <muthu_nano@yahoo.co.in> wrote: >Thanks for the info. and one of the xilinx answer record suggest that >if the multiplexer has more than 7 inputs, it is better to design Mux >with TBUFs. But i tried once. The problem was, the routing delay is >more.. because each CLBs has only 2 TBUFs. > >Here i need to implement a 64:1 multiplexer for 200 MHz speed. Is >there any way to acheive this speed ? Whats the architecture you are using? You could use a tree structure of muxes with pipeline registers. One possibility is a series of OR/ANDs (like what the TBUFs do) but using the logic cells, pipeline the output, and pipeline the merge? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 47014
Since all this logic is strictly synchroneous, the divider ratio is integer. Sorry. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net Bruce (newbie) wrote: > I am a new comer to VHDL design, and I need to some sort of clock > divison scheme that can divide a clock by noninteger values such as > 3.33. Not simple values like 1.5,2.5 etc. Can anyone give me some > suggestions or ways of achieving this?Article: 47015
Falk Brunner wrote: > > "rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag > news:3D823853.1CF2BFC9@yahoo.com... > > > > Just a small correction, the global clock inputs are INPUTS only, so no > IOs. > > > The datasheet says, that the 4 global clock inputs are exluded from the > IO > > > number. I can't find a mention in the data sheet where they say if the clock inputs are counted as I/Os or not. I don't see any reason to NOT count them. They are inputs. There is nothing about I/O that excludes input only pins. On older families there were many pins that could be user I/Os, but only input or output after configuration. In this family it seems that the GCLK pins are the only ones that have this "feature". > > Which data sheet? Try counting them. I did. The clock inputs are > > counted as "IOs". > > Actually, I didnt count them. ;-) > And I wont count them. But a Xilinx guy promised to correct that. If you want to trust others for the correctness of your work, then by all means never verify anything in a data sheet, including the things that you have been warned are not reliable. Like Reagan, I will trust, but verify... So Xilinx is going to change the data sheet for the XC2SE family to show FG456 IO counts of 100E 196 150E 261 200E 285 I'll bet you a pepsi twist that it comes out 100E 200 150E 265 200E 289 As far as I am aware, Xilinx counts input only and output only pins, including the GCLK pins in IO counts for ALL of their parts, FPGAs and CPLDs. I've never seen 'em miss one! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47016
Bruce, look at the Virtex-II Digital Clock Manager. It can multiply and divide ( simultaneously!) a continuously running clock. So you can multiply by three and divide by ten, etc. Multiplier and divisor should each not exceed 32. See the Virtex-II Data Book on-line. Peter Alfke, Xilinx Applications "Bruce (newbie)" wrote: > I am a new comer to VHDL design, and I need to some sort of clock divison scheme that can divide a clock by noninteger values such as 3.33. Not simple values like 1.5,2.5 etc. Can anyone give me some suggestions or ways of achieving this? > > Please send reply to my email as well > > Thanks in advance > Regards, > BruceArticle: 47017
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:3D835C3E.A69A9290@yahoo.com... > I can't find a mention in the data sheet where they say if the clock > inputs are counted as I/Os or not. I don't see any reason to NOT count Its somewhere in the 1 (out of 4), product availability. I cant have a look at them now, dont have them here. > > Actually, I didnt count them. ;-) > > And I wont count them. But a Xilinx guy promised to correct that. > > If you want to trust others for the correctness of your work, then by > all means never verify anything in a data sheet, including the things > that you have been warned are not reliable. Like Reagan, I will trust, > but verify... Rickman, whats driving you so insane about this? Its a minor bug, IMHO. In a design, I have a exel sheet with all pins in it, then I distribute my user pins. And there I can see if the device has enough pins or not. I never relyed on the single number in the datasheet. At this point, nothing is messed up with the design. Or do you just make a quick schematics entry, place the FPGA somehow on the PCB, connect it somehow to al ICs and start manufacturing? We dont. -- MfG FalkArticle: 47018
"Rene Tschaggelar" <tschaggelar@dplanet.ch> schrieb im Newsbeitrag news:3D8356A8.4040500@dplanet.ch... > Since all this logic is strictly synchroneous, the divider ratio is > integer. Sorry. Says who? A non-integer clock division can be made using a simple DDS. Yes, this has its limitations, the most important is intrinsic jitter of 1 master clock cyle. But its all a question if this acaptabel for the application or not. -- MfG FalkArticle: 47019
n1ist@panix.com (Michael Ardai) wrote in message news:<allnd2$ksp$1@panix3.panix.com>... > I have a design that uses Xilinx 18v00 PROMs (18V01 and 18V04) to boot > some FPGAs. I would like to be able to field-update them thru their > JTAG port but would rather not embed Xilinx's eisp software in my system. > Does anyone have any info on the programming algorithm for these or > similar PROMs? I already can handle sending and receiving TAP commands > and data. Xilinx doesn't publish information how to program these devices. I suppose it is so they don't have to support it. However, all you have to do is read the SVF file generated by JTAG programmer. It is text and fairly easy to understand. Alan Nishioka alann@accom.comArticle: 47020
Falk Brunner wrote: > > "rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag > news:3D835C3E.A69A9290@yahoo.com... > > > I can't find a mention in the data sheet where they say if the clock > > inputs are counted as I/Os or not. I don't see any reason to NOT count > > Its somewhere in the 1 (out of 4), product availability. I cant have a look > at them now, dont have them here. Looked, searched, not there. > > > Actually, I didnt count them. ;-) > > > And I wont count them. But a Xilinx guy promised to correct that. > > > > If you want to trust others for the correctness of your work, then by > > all means never verify anything in a data sheet, including the things > > that you have been warned are not reliable. Like Reagan, I will trust, > > but verify... > > Rickman, whats driving you so insane about this? Its a minor bug, IMHO. In a > design, I have a exel sheet with all pins in it, then I distribute my user > pins. And there I can see if the device has enough pins or not. I never > relyed on the single number in the datasheet. At this point, nothing is > messed up with the design. Or do you just make a quick schematics entry, > place the FPGA somehow on the PCB, connect it somehow to al ICs and start > manufacturing? We dont. Sorry if I seem so "insane" about this. I do a lot of planning up front where I don't even get to the point of assigning pins until I know a design will fit in the part. Often I don't have the option of moving to a larger part once I have commited to a given package size and/or price. So finding at the design stage that the data sheet was off by 6 pins can be a BIG problem. I have also found discrepencies where a part is listed as being available in a given package only to find that that combination was started, but pulled before making it to full production. So I try to verify, verify, verify everything about these chips that I can. FPGAs and CPLDs seem to have a lot more "discrepancies" than all the other parts on the board together. When was the last time a memory, logic, CPU vendor told you that a new part had pin count or assignment errors???? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47021
In the XCR3xxxXL family architecture it appears that the FF of a macrocell can be used separately from the logic as long as you can feed the D input from the IO pin. I need to implement a shift register with an output register. I would like to be able to use the logic on the input shift register for other combinatorial functions. It looks like the enable on the FFs can come from a single product term without using the "or array". If so, I could decode a simple counter to enable each of the "shift register" FFs. Anyone know for sure if this will allow me to use the combinatorial logic in the macro cell for a separate function? Should I fire up the software and see if it works for myself? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47022
On Sat, 14 Sep 2002 02:40:51 -0700, "Bruce (newbie)" <bruce@bytes.co.za> wrote: >I am a new comer to VHDL design, and I need to some sort of clock divison scheme that can divide a clock by noninteger values such as 3.33. Not simple values like 1.5,2.5 etc. Can anyone give me some suggestions or ways of achieving this? Are the dividers fixed ratio or agile? A program that generates fixed ratio dividers in both VHDL and Verilog can be found at this site: http://fractional_divider.tripod.com/index.html A variable divider is best made with a phase accumulator as Falk suggested. You should be aware that any divider described in synthesisable VHDL will be a state machine that can only change its output on edges of the input clock. So your output clock must have jitter if you are dividing the frequency by a noninteger value. This jitter can be as high as one period of the input clock. (Well, I guess it could be higher if the divider was badly designed.) E.g. dividing 1MHz by your example of 3.33 (to give 300.3kHz) will result in about 990ns p-p of jitter. Depending on your jitter budget, this may be too much. There are some fixes using *analog* electronics (a PLL would work or you could also try a DDS driving a DAC, followed by a low- or bandpass filter and a comparator). But it isn't possible to make intelligent suggestions until your requirements are known. Regards, Allan.Article: 47023
> > Its somewhere in the 1 (out of 4), product availability. I cant have a look > > at them now, dont have them here. > > Looked, searched, not there. Looked, searched, not there. ;-)) Its only notet in the Spartan-II datasheet (first page, ds001_1) So my weak memory suggested me it must be the same with Spartan-IIE. Expect the unexpected. > Sorry if I seem so "insane" about this. I do a lot of planning up front > where I don't even get to the point of assigning pins until I know a > design will fit in the part. Often I don't have the option of moving to > a larger part once I have commited to a given package size and/or > price. So finding at the design stage that the data sheet was off by 6 ?????? Looks like you have a someway much different way of design than me. At first, I (try to) design with flexibility in mind. So I choose a FPGA which is availabe in different sizes for a given package. Gives room for up/downgrading after design is fully implemented. Makes you (and your design buddys/leader) have sweet dreams and not to worry too much about FPGA reaching 101% of its limits. Just recently a colleage had a design in a XCS30. No more way to change the part. Logic resources usage somewhere to 85%. This was a hell for P&R, only with heavy LOCing we could make it. Also I dont design to 100% pin usage. IF you really need this, I do not rely on a plain number, grabbing the excel pin list is vital there. > pins can be a BIG problem. I have also found discrepencies where a part > is listed as being available in a given package only to find that that > combination was started, but pulled before making it to full > production. So I try to verify, verify, verify everything about these > chips that I can. FPGAs and CPLDs seem to have a lot more Sure, verification is important. But it should not develop into paranoia, should'nt it?? ;-)) > "discrepancies" than all the other parts on the board together. When > was the last time a memory, logic, CPU vendor told you that a new part > had pin count or assignment errors???? Never happend to me, yet. Maybe Iam not long enough in the business (just 2 years up to now). -- MfG FalkArticle: 47024
Allan Herriman wrote: > This jitter can be as high as one period of the input clock. (Well, I > guess it could be higher if the divider was badly designed.) > > E.g. dividing 1MHz by your example of 3.33 (to give 300.3kHz) will > result in about 990ns p-p of jitter. > > Depending on your jitter budget, this may be too much. There are some > fixes using *analog* electronics (a PLL would work or you could also > try a DDS driving a DAC, followed by a low- or bandpass filter and a > comparator). The jitter thing also applies to Peter's suggestion of using the DCM in DFS mode. The jitter calculator on the web shows quite large pk-pk figures. For example 50MHz * (2/3) to get a PCI clock would give 890ps, about 3%.
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