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Peter (and the group), I am laughing! I am right down the hall, and Peter sees it as not a good idea, and I am intrigued by it and am dreaming up experiments in my post to Rick! Peter does lend this some reality: there are easier ways to get numbers that are pretty good and (pseudo) random. Austin Peter Alfke wrote: > Let me discourage you from trying to use metastability to generate random > numbers. Metastability is an extremely fast phenomenon, and I do not see how > you can achieve true randomness ( equal probability of any 1-0 sequence, and > equal number of 0s and 1s. > What is you purpose? > Linear Feedback Shift Registers (LFSRs) can substitute for random number > generators in many, but not all, cases > > Peter Alfke, Xilinx > =================== > Wojciech Piechowski wrote: > > > hello! > > > > I've just read an interesting thread about metastability and this made me > > think about making a hardware random bit generator. Exploiting > > metastability seems to be interesting. Just put to D an alternating > > sequence which toggles with clock. Add some smart routing to make it hit > > the hold window. And have a long time thinking how to read metastable Q > > without passing metastability to the rest of the circuit.... > > > > Has anyone done something like this? Or heard about it? I'm thinking about > > implementing it. Any help and comments appreciated. > > > > -- > > -- Wojciech Piechowski - wpiechowski@acm.org - Gadu-Gadu 494156 --Article: 46976
Let me discourage you from trying to use metastability to generate random numbers. Metastability is an extremely fast phenomenon, and I do not see how you can achieve true randomness ( equal probability of any 1-0 sequence, and equal number of 0s and 1s. What is you purpose? Linear Feedback Shift Registers (LFSRs) can substitute for random number generators in many, but not all, cases Peter Alfke, Xilinx =================== Wojciech Piechowski wrote: > hello! > > I've just read an interesting thread about metastability and this made me > think about making a hardware random bit generator. Exploiting > metastability seems to be interesting. Just put to D an alternating > sequence which toggles with clock. Add some smart routing to make it hit > the hold window. And have a long time thinking how to read metastable Q > without passing metastability to the rest of the circuit.... > > Has anyone done something like this? Or heard about it? I'm thinking about > implementing it. Any help and comments appreciated. > > -- > -- Wojciech Piechowski - wpiechowski@acm.org - Gadu-Gadu 494156 --Article: 46977
> -----Original Message----- > From: rickman [mailto:spamgoeshere4@yahoo.com] > You can easily control a > "virtual" resistor in a digital FPGA. [...] > So you can use a simple digital counter with a threshold compare to > enable a FF divide by two as the heater. Can you be confident that the FF will dissipate more than the circuits/nets that drive its clock input??? I suspect that the original poster would like to have negligible dissipation anywhere on his chip except at the matrix points he's trying to control. Sounds tough on a general purpose FPGA. Interesting idea, though. -- Jonathan Bromley HDL Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project = Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 = 1AW, UK Tel: +44 (0)1425 471223 mail: = jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: = http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. = reserves all rights of privilege in respect thereof. It is intended for the use = of the addressee only. If you are not the intended recipient please delete = it from your system, any use, disclosure, or copying of this document = is unauthorised. The contents of this message may contain personal views = which are not the views of Doulos Ltd., unless specifically stated.Article: 46978
On Fri, 13 Sep 2002 11:19:52 -0400, rickman wrote:
>Wojciech Piechowski wrote:
>>
>> I've just read an interesting thread about metastability and this made me
>> think about making a hardware random bit generator.
>
>But, to have a *useful* random number generator, the values must have
>certain properties. One of them is that the distibution must be even.
An even distribution generates the most entropy per clock cycle.
A hardware random number generator is very interesting even if
it only generates a small percentage of that entropy per clock cycle.
>If you are generating a stream of 1s and 0s, then you must have half 1s
>and half 0s. It would be very, very hard to control the metastability
>to get this even distribution. Partly this is because the delay is a
>function of temperature and voltage which you will not be able to
>control sufficiently.
Even getting the distribution to stay in the .1 to .9 range would
probably require some kind of feedback. I don't have any practice
with the DLLs of VirtexE and Virtex-II to know if they have enough
flexibility to be used as the control element. According to the
metastability numbers, the edges need to fall within about 40 ps
of each other (Peter's recent Virtex-II number; other families
presumably have larger times). The delay quantum of Virtex is
60ps, right? So it could get within 30 ps of a desired time offset.
>I have seen a random generator based on diode noise have problems with
>distribution.
I guess it depends on what the goal is.
- Larry
Article: 46979"Muthu" <muthu_nano@yahoo.co.in> schrieb im Newsbeitrag news:28c66cd3.0209122001.79bedf3e@posting.google.com... > Hi, > > what is the difference between BUFT and TBUF ???? TBUF is a tristate drive for internal nets, a BUFT a tristate driver in the IOB for signal going outside the IC. -- MfG FalkArticle: 46980
>Let me discourage you from trying to use metastability to generate random >numbers. Metastability is an extremely fast phenomenon, and I do not see how >you can achieve true randomness ( equal probability of any 1-0 sequence, and >equal number of 0s and 1s. There are tricks for turning biased sequences into random bits. Try 10 => 0 and 01 => 1. 00 and 11 get ignored. I think the real problem with trying to get randomness from metastability is that it's compilcated and hard to analyze. A lot of work has been done in that field. I'm far from a wizard. You get randomness from things like thermal noise and radioactive decay. Ask google about "noise diode". What is the true source of noise on a metastability setup? Thermal noise. Right? The classic problem with thermal noise systems is power supply isolation. Will your metastability setup really measure thermal noise or will it just measure power supply coupling from the rest of your circuit? Or clock jitter? >What is you purpose? >Linear Feedback Shift Registers (LFSRs) can substitute for random number >generators in many, but not all, cases Pseudo random. Not really random. No good for crypto. Yes, very good for many things. Other classic ways to get a few random bits are to look at the bottom bit(s?) of a fast counter when something like a keystroke or packet arrives. But even that can be amazingly non random. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 46981
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:3D81943A.96738A6C@yahoo.com... > I have not done a complete count of one of these parts lately, but I am > pretty sure that not only do they count the clock inputs as "IOs", they Just a small correction, the global clock inputs are INPUTS only, so no IOs. The datasheet says, that the 4 global clock inputs are exluded from the IO number. -- MfG FalkArticle: 46982
Yes, the Xilinx Spartan-IIE I/O count includes the 4 GCLK pins that can be used as general-purpose inputs. Dan wrote: > Hello, > > The XC2S50-PQ208 has 140 IOs as stated in the Xilinx data sheet. > > I just approved a requested design change to the replace the XC2S50-PQ208 > ( Spatan II ) with with E version because the data sheet states it has 146 > IOs. I only count 142. I have counted two times. Is Xilinx counting the 4 > GCLKs as IOs. If they have changed the rules on their IO counts in this way > I will be very annoyed. I need all of the documented 146 IOs. Can someone > please tell me were are the 4 missing IOs on the Spartan IIE -PQ208 package > ( device size 50K gates and up ) ? > > Dan -- Marc Baker Xilinx ApplicationsArticle: 46983
In article <uo45k7j3j76b56@corp.supernews.com>, Hal Murray <hmurray@suespammers.org> wrote: >>Linear Feedback Shift Registers (LFSRs) can substitute for random number >>generators in many, but not all, cases > >Pseudo random. Not really random. No good for crypto. >Yes, very good for many things. As pseudo-random goes, LFSRs are actually pretty crappy. Hashing a counter with a crypto hash would be soo much better. Or encrypting a counter and using the lower 1/2 bits (since a block cypher should look like a random PERMUTATION). -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 46984
Your counting is correct. Xilinx will be updating this data sheet with the correct numbers as soon as possible. rickman wrote: > Dan wrote: > > > > Hello, > > > > The XC2S50-PQ208 has 140 IOs as stated in the Xilinx data sheet. > > > > I just approved a requested design change to the replace the XC2S50-PQ208 > > ( Spatan II ) with with E version because the data sheet states it has 146 > > IOs. I only count 142. I have counted two times. Is Xilinx counting the 4 > > GCLKs as IOs. If they have changed the rules on their IO counts in this way > > I will be very annoyed. I need all of the documented 146 IOs. Can someone > > please tell me were are the 4 missing IOs on the Spartan IIE -PQ208 package > > ( device size 50K gates and up ) ? > > > > Dan > > I have not done a complete count of one of these parts lately, but I am > pretty sure that not only do they count the clock inputs as "IOs", they > count all the dual use pins that are used during configuration and/or > other functions depending on how programmed (CCLK, DOUT, D0/DIN, > INIT...). > > Just for the fun of it I counted the IOs for the XC2S150E-FG456 and > XC2S200E-FG456. Interestingly enough I got the right number for the > XC2S200E-FG456 assuming that the GCLKs are counted as IOs, 289. But for > the XC2S150E-FG456, I got 2 pins more than the data sheet number, 263. > Of course I double checked my counts. I did them by banks to make sure > I did it right. So I don't know for sure, but I belive the data book is > off in this case. Hmmmm... checking the 100E I count two less than the > data book. > > But the point it, they count GCLKs, INIT... all of the pins that can be > used as IOs in any way, shape or form. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX -- Marc Baker Xilinx Applications (408) 879-5375Article: 46985
Jonathan Bromley wrote: > > > -----Original Message----- > > From: rickman [mailto:spamgoeshere4@yahoo.com] > > > You can easily control a > > "virtual" resistor in a digital FPGA. > [...] > > So you can use a simple digital counter with a threshold compare to > > enable a FF divide by two as the heater. > > Can you be confident that the FF will dissipate more than the > circuits/nets that drive its clock input??? > > I suspect that the original poster would like to have > negligible dissipation anywhere on his chip except at the > matrix points he's trying to control. Sounds tough on a > general purpose FPGA. > > Interesting idea, though. That all depends on how you define "negligible". :) I belive you can achive a 100:1 ratio depending on other factors such as the total heat generated and the values of N and M. There are a lot of facts not in evidence. That is why I suggested the OP email me. Heck, I don't even know if the OP wants to run this thing with the lid on or off??? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46986
Austin Lesea wrote: > > Rick, > > I thought of using the DCM's variable phase shift to "keep" the metastability > region in the right spot, but that does two things, one it removes a degree of > randomness, and two, it puts the count of metastable events into a mode where > its rate or occurences, are predictable (ie non-random rate?). I don't see the metastability being the actual thing generating the random data. A following stage that removes the metastability would have a random like appearance since it would have a probability of going in either direction. The trick is to get that probability to 50:50. Not at all easy... I also expect that you can't really keep the delay close enough to "perfect" to help in this situation. You would be trying to keep the pencil balanced on its edge by twitching your finger as a poor analogy. > Like many things that appear random, metastability does't seem so random upon > closer inspection. It is just a bad thing that happens at a given probability > for any specific condition. > > The teaser is that if you had it in the region you want, and you use the phases > of the DCM to sample inside the region of metastability, it might be interesting > to see what kind of distribution you get. For example, sample at 90 degrees and > 180 degrees. If you get both equal, call that a 1, if they are not both equal, > call that a zero. Don't look at this "coin toss" unless the event was > metastable (i.e. the data had not settled). > > I suspect that the distribution of this is not good, as longer metastable events > are much more unlikely than shorter metastable events (how long the ball > balances on the hill before it rolls off....). > > Even though the distribution is not evenly distributed (ie it may be gaussian), > it still might be useful. > > Perhaps sampling at closer phases would even out the probability of a 1 or 0 to > closer to 50%....... > > Austin You are much closer to your metastable circuits than I am. I think we are talking about different things we are measuring. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46987
Peter Alfke wrote: > Let me discourage you from trying to use metastability to generate random > numbers. Metastability is an extremely fast phenomenon, and I do not see how > you can achieve true randomness ( equal probability of any 1-0 sequence, and > equal number of 0s and 1s. > What is you purpose? > Linear Feedback Shift Registers (LFSRs) can substitute for random number > generators in many, but not all, cases > > Peter Alfke, Xilinx > =================== > Wojciech Piechowski wrote: > Isn't there some confusion here, on this thread, between `randomness' and `distribution'. Just because a variable isn't uniformly distributed doesn't mean it isn't random. In fact the value of the metastability decay time is generally held to be random with an exponential distribution. So ... lets assume that we can use metastability to get random values X with some distribution F. Now its a long time since I did any stats but IIRC there's a thing called the Central Limit Theorem that says for any distribution if you form a new set of values by taking averages: V(N) = (X1 + ..... + XN)/N the distribution of V(N) converges to Gaussian as N gets large. Now the Gaussian function is symmetric about its mean so, letting M = the mean of this new distribution, we can generate a new stream of 1's & 0's by taking a 1 if V(N) > M, 0 otherwise. This should be uniform i.e. 0 & 1 are equi-probable. Discuss :-) ? I have a feeling that the CLT applies to random variables whose range is the whole real line so that this might have to be modified to use the initial `metastab' bit stream to create random floating point values.Article: 46988
Typically N<=10 and M<=10. The power in a single resistor is around 20mW. "Rajeev" <rrr@ieee.org> wrote in message news:c0f37b00.0209130738.69c14376@posting.google.com... > Can you tell us typical values of N,M and power in a single resistor ? > > -rajeev- > ---------------- > "Lu Hu" <meta2000@ustc.edu> wrote in message news:<3d80d0cc$0$3925$b45e6eb0@senator-bedfellow.mit.edu>... > > Hello, > > > > I have never used FPGA before. Could anybody tell me if it is possible to > > make a 2-D resistor array (N*M) using FPGA? The power input of each resistor > > needs to be controlled individually. It is preferrable that the FPGA board > > has built-in array of cavities. Thank you! > > > > -metaArticle: 46989
It is a very good suggestion though there are still some details to think about. I am worrying about the power at each heating point. Is 20mW too big for the virtual resistor? "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3D820B00.77F8034D@yahoo.com... > Reading this thread I see that the respondents have all been thinking > too "linearly", if you will excuse the pun. You can easily control a > "virtual" resistor in a digital FPGA. > > Consider a switched capacitor filter. Switches are used to control the > rate that a capacitor is used to move current from one node to another. > For currents at frequencies well below the Nyquist rate of the > switching, this appears to be a continuous resistor. Certainly a > heating effect would have to heat enough mass to mask the "switching > noise". > > So you can use a simple digital counter with a threshold compare to > enable a FF divide by two as the heater. The heating FF should run at a > very high rate to produce the maximum heating effect. The > counter/compare circuit should run at a slower rate so that it does not > produce significant heat itself. Or you can use a large number of > heating FFs controlled by each counter to produce more heat than the > counter. > > The length of the counter will be determined by the control resolution > you need to have over the circuit. > > As with most simple solutions, the devil is in the details. If you need > further help with this, drop me an email at the address below. > > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46990
Yes, you are right. I just need "site-heating". "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:x#u3VB0WCHA.3472@lucy.doulos.com... > -----Original Message----- > From: rickman [mailto:spamgoeshere4@yahoo.com] > You can easily control a > "virtual" resistor in a digital FPGA. [...] > So you can use a simple digital counter with a threshold compare to > enable a FF divide by two as the heater. Can you be confident that the FF will dissipate more than the circuits/nets that drive its clock input??? I suspect that the original poster would like to have negligible dissipation anywhere on his chip except at the matrix points he's trying to control. Sounds tough on a general purpose FPGA. Interesting idea, though. -- Jonathan Bromley HDL Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. reserves all rights of privilege in respect thereof. It is intended for the use of the addressee only. If you are not the intended recipient please delete it from your system, any use, disclosure, or copying of this document is unauthorised. The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 46991
With any technology you will have some heating elsewhere. The question is how much is acceptable? Not so tough. If you only need 100 heating points with 20 mW per point I expect this will be easy with a standard FPGA. Is there a size limit on the individual heaters? In another post you said you were heating water. Does that mean you need to remove the lid from the package and put water on the die? I belive this is not a good thing for semiconductors. Have you considered this issue? meta wrote: > > Yes, you are right. I just need "site-heating". > > "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message > news:x#u3VB0WCHA.3472@lucy.doulos.com... > > -----Original Message----- > > From: rickman [mailto:spamgoeshere4@yahoo.com] > > > You can easily control a > > "virtual" resistor in a digital FPGA. > [...] > > So you can use a simple digital counter with a threshold compare to > > enable a FF divide by two as the heater. > > Can you be confident that the FF will dissipate more than the > circuits/nets that drive its clock input??? > > I suspect that the original poster would like to have > negligible dissipation anywhere on his chip except at the > matrix points he's trying to control. Sounds tough on a > general purpose FPGA. > > Interesting idea, though. > > -- > Jonathan Bromley > HDL Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > This e-mail and any attachments are confidential and Doulos Ltd. reserves > all rights of privilege in respect thereof. It is intended for the use of > the addressee only. If you are not the intended recipient please delete it > from your system, any use, disclosure, or copying of this document is > unauthorised. The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46992
Falk Brunner wrote: > > "rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag > news:3D81943A.96738A6C@yahoo.com... > > > I have not done a complete count of one of these parts lately, but I am > > pretty sure that not only do they count the clock inputs as "IOs", they > > Just a small correction, the global clock inputs are INPUTS only, so no IOs. > The datasheet says, that the 4 global clock inputs are exluded from the IO > number. Which data sheet? Try counting them. I did. The clock inputs are counted as "IOs". -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46993
Rick Filipkiewicz wrote: > > Peter Alfke wrote: > > > Let me discourage you from trying to use metastability to generate random > > numbers. Metastability is an extremely fast phenomenon, and I do not see how > > you can achieve true randomness ( equal probability of any 1-0 sequence, and > > equal number of 0s and 1s. > > What is you purpose? > > Linear Feedback Shift Registers (LFSRs) can substitute for random number > > generators in many, but not all, cases > > > > Peter Alfke, Xilinx > > =================== > > Wojciech Piechowski wrote: > > > > Isn't there some confusion here, on this thread, between `randomness' and > `distribution'. Just because a variable isn't uniformly distributed doesn't mean > it isn't random. In fact the value of the metastability decay time is generally > held to be random with an exponential distribution. > > So ... lets assume that we can use metastability to get random values X with > some distribution F. Now its a long time since I did any stats but IIRC there's > a thing called the Central Limit Theorem that says for any distribution if you > form a new set of values by taking averages: > > V(N) = (X1 + ..... + XN)/N > > the distribution of V(N) converges to Gaussian as N gets large. Now the Gaussian > function is symmetric about its mean so, letting M = the mean of this new > distribution, we can generate a new stream of 1's & 0's by taking a 1 if V(N) > > M, 0 otherwise. This should be uniform i.e. 0 & 1 are equi-probable. > > Discuss :-) ? > > I have a feeling that the CLT applies to random variables whose range is the > whole real line so that this might have to be modified to use the initial > `metastab' bit stream to create random floating point values. That may all be great in theory, but in practice you can't make it work. As someone else pointed out, this is the type of circuit that will be very sensitive to noise, espeically on the power bus. You are much more likely to get a clock noise measurement circuit than a random number generator. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46994
meta wrote: > > Typically N<=10 and M<=10. The power in a single resistor is around > 20mW. What physical size were you looking for ? Can all be on -> 2W load ? Bubble jet printers use minature heaters, and control - plenty of those about :) Also, LCD display techniques drive a matrix of cross points, where the objective is to have a good On : OFF ratio. With these, as MUX ratios go up, the available contrast, or ratio of On : Off gets worse ( ie a smaller control span ) Then there are DOT-LED drive schemes - we have done 48 LEDS from a 22V10, ( 10 OP ) as an example of this. A 44 pin CPLD could drive up to 480 DOT-LEDs, but will likely hit drive ceilings before that. -jgArticle: 46995
On Fri, 13 Sep 2002 15:16:52 -0400, rickman <spamgoeshere4@yahoo.com> wrote:
>
>That may all be great in theory, but in practice you can't make it
>work. As someone else pointed out, this is the type of circuit that
>will be very sensitive to noise, espeically on the power bus. You are
>much more likely to get a clock noise measurement circuit than a random
>number generator.
Somebody needs to try this out, and get some real experimental
data. Either result is interesting. ;-)
- Larry
Article: 46996"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:3D823853.1CF2BFC9@yahoo.com... > > Just a small correction, the global clock inputs are INPUTS only, so no IOs. > > The datasheet says, that the 4 global clock inputs are exluded from the IO > > number. > > Which data sheet? Try counting them. I did. The clock inputs are > counted as "IOs". Actually, I didnt count them. ;-) And I wont count them. But a Xilinx guy promised to correct that. -- MfG FalkArticle: 46997
yes, size is a big problem. The spacing between neighoring resistors should be less than 10um, which means possibly huge heat flux. "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3D8237CC.4FD185CD@yahoo.com... > With any technology you will have some heating elsewhere. The question > is how much is acceptable? Not so tough. If you only need 100 heating > points with 20 mW per point I expect this will be easy with a standard > FPGA. Is there a size limit on the individual heaters? > > In another post you said you were heating water. Does that mean you > need to remove the lid from the package and put water on the die? I > belive this is not a good thing for semiconductors. Have you considered > this issue? > > > > meta wrote: > > > > Yes, you are right. I just need "site-heating". > > > > "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message > > news:x#u3VB0WCHA.3472@lucy.doulos.com... > > > -----Original Message----- > > > From: rickman [mailto:spamgoeshere4@yahoo.com] > > > > > You can easily control a > > > "virtual" resistor in a digital FPGA. > > [...] > > > So you can use a simple digital counter with a threshold compare to > > > enable a FF divide by two as the heater. > > > > Can you be confident that the FF will dissipate more than the > > circuits/nets that drive its clock input??? > > > > I suspect that the original poster would like to have > > negligible dissipation anywhere on his chip except at the > > matrix points he's trying to control. Sounds tough on a > > general purpose FPGA. > > > > Interesting idea, though. > > > > -- > > Jonathan Bromley > > HDL Consultant > > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > > > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK > > Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com > > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > > > This e-mail and any attachments are confidential and Doulos Ltd. reserves > > all rights of privilege in respect thereof. It is intended for the use of > > the addressee only. If you are not the intended recipient please delete it > > from your system, any use, disclosure, or copying of this document is > > unauthorised. The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46998
The spacing between neighboring resistor is about 10um. Bubble jet printers use larger heaters. It is a challenge to fabricate such tiny 10um heaters. "Jim Granville" <jim.granville@designtools.co.nz> wrote in message news:3D823A7F.CF@designtools.co.nz... > meta wrote: > > > > Typically N<=10 and M<=10. The power in a single resistor is around > > 20mW. > > What physical size were you looking for ? > > Can all be on -> 2W load ? > > Bubble jet printers use minature heaters, and control - plenty of > those about :) > > Also, LCD display techniques drive a matrix of cross points, where > the objective is to have a good On : OFF ratio. > With these, as MUX ratios go up, the available contrast, or > ratio of On : Off gets worse ( ie a smaller control span ) > > Then there are DOT-LED drive schemes - we have done 48 LEDS from a > 22V10, > ( 10 OP ) as an example of this. > > A 44 pin CPLD could drive up to 480 DOT-LEDs, but will likely hit > drive ceilings before that. > > -jgArticle: 46999
Hi Kevin, > Do you know if the QII 2.1's built-in synthesis tool can generate > an EDIF netlist? I personally hate using synthesis tools > that generate proprietary or non-text netlists. After P&R you can get Quartus to spew out a VQM (a subset of Verilog) netlist. It's somewhere under Processing->Compiler Settings->"Synthesis and Fitting" tab, check the "Save a node-level netlist..." option, or, alternatively, in 2.1 you can specify your favourite simulator in the Project->"EDA Tools" menu, and then from the "Processing" menu generate a netlist in the VHDL or Verilog dialect of choice. > Speaking of LeonardoSpectrum, Ben, if you worked at Mentor > Graphics, do you know why LeonardoSpectrum's GUI used to be sooooooo > buggy until LeonardoSpectrum 2002a? (I still remember Altera OEM version > LeonardoSpectrum 2001a.028's GUI used to crash so easily.) I had moved to Altera by the time the Mentor OEM deal got into practice, so no first-hand stories here. My guess is that it's an "Engineering resources" problem. I have been looking at the details of the synthesis engine and have noted a lot of changes and improvements there. With the 2001.1 series I tried to only make the settings I needed, do a run and exit the tool. If I wanted to try different settings I would restart the tool and try those settings. It's a way of life... Thing is that the synthesis engine runs only once and frees its resources, while the GUI has to survive multiple runs, settings changes etc. If the testing comprised of opening a sample design, setting its options, compiling it and exiting the tool I can sort-of imagine the whole thing getting wobbly after a few runs. As such, the GUI indeed has been a stability disaster and I think that the port from "mainline" Leonardo to the OEM version so far for a long time has suffered from (1) not enough GUI-focused engineering and (2) not enough internal testing. BTW: as to (1), you'll be in for a treat sometime next year. I've seen some really neato alpha-stage code at work a few months ago. The reason why you'll see it only next year is because Mentor seems to be taking complaints about (2) seriously now. Best regards, Ben
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