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Is it possible to build a Ring Oscillator in an FPGA chip? Any kind of tricks may do, but is it possible? Kelvin.Article: 47501
"Cool Morning ..." wrote: > > Is it possible to build a Ring Oscillator in an FPGA chip? Any kind of > tricks may do, but is it possible? > > Kelvin. I most certainly is. One of my former coworkers did just that inside an Altera 10KA part to help characterize the part when we found that the timing analysis tool was failing to accurately do the job. I don't remember the exact rational, but he was calculating the free running speed of the oscillator using the timing tool and then measuring how fast it actually ran under temperature and voltage. All you have to do is construct a ring feedback path with three 2-input NAND gates and then pull the other inputs to a one. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47502
Yes it is. You may have to go outside the chip though as most software doesn't like combinatorial loops. Be ready to send your device to the guy who wants dead parts though as it is not a FPGA friendly design. Steve "Cool Morning ..." <Far@East.Design> wrote in message news:3d93b2da@news.starhub.net.sg... > Is it possible to build a Ring Oscillator in an FPGA chip? Any kind of > tricks may do, but is it possible? > > Kelvin. > > > > >Article: 47503
rickman wrote: > > "Cool Morning ..." wrote: > > > > Is it possible to build a Ring Oscillator in an FPGA chip? Any kind of > > tricks may do, but is it possible? > > > > Kelvin. > > I most certainly is. One of my former coworkers did just that inside an > Altera 10KA part to help characterize the part when we found that the > timing analysis tool was failing to accurately do the job. I don't > remember the exact rational, but he was calculating the free running > speed of the oscillator using the timing tool and then measuring how > fast it actually ran under temperature and voltage. Yes, SW tools are great, but you can't beat bringing the silicon inside the design loop :) > > All you have to do is construct a ring feedback path with three 2-input > NAND gates and then pull the other inputs to a one. We have done the same thing, to measure Delays, Delay matching, and node delays inside CPLD ( more accurate than any data sheet :) You can resolve to ps delays this way. Fishhooks : - Some tools may not like the async+loop, so could need 'coaxing' - If making it long, make sure to have a INIT(Start/enable), that drives every second NAND gate. This forces it to start from a known DC state, otherwise you can find there is more than one stable 'traveling wave' in your ring. -jgArticle: 47504
Yep, you can do that. Oscillation frequency depends on how many luts you
put in the ring. Great for characterizing the delay times in the part.
Good also for letting the magic smoke out of the part (and the board it is
sitting on) if you put too many of them in there.
"Cool Morning ..." wrote:
> Is it possible to build a Ring Oscillator in an FPGA chip? Any kind of
> tricks may do, but is it possible?
>
> Kelvin.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47505Altera was never prohibited from calling their devices "FPGA". Others did it, Actel and Quicklogic come to mind. The acronym never was protected by any copyright What stopped Altera from using this appropriate name is not such a mystery: During the time of the lawsuit between Altera and Xilinx, Altera wanted to emphasize that their LUT-based devices were not really just a copy of Xilinx FPGAs. Any little bit of nomenclature juggling was used to help the cause. Now that the lawsuit is over, Altera can use common sense and call their devices FPGAs. If it walks like a duck, and sounds like a duck, and smells like a duck... Peter Alfke ================================ Eric Smith wrote: > "Xanatos" <fpsbb98@yahoo.com> writes: > > IIRC, the Altera-Xilinx deal that allowed cross-patents means Altera can use > > the term FPGA instead of CPLD. > > Why would Altera not have been allowed to use the term FPGA previously? > Does Xilinx have a trademark on it?Article: 47506
Every Xilinx FPGA you buy has already had a ring oscillator running in it, since that is part of the test routine. Works like a champ, but can be very fast if you make the loop too small. You can also use it to measure chip temperature, and even temperature gradients across the chip. (Remember, frequency can easily be measured with one part per million accuracy). You can also use it as a controllable heater and make a thermostat out of it. Peter Alfke "Cool Morning ..." wrote: > Is it possible to build a Ring Oscillator in an FPGA chip? Any kind of > tricks may do, but is it possible? > > Kelvin.Article: 47507
Peter, You mentioned the chip has already a ring oscillator on it, but how can I find it? How can I make use of it? Is it something like the DLL which I can instantiate in my vhdl code? Let's say my chip is Spartan2 200K...My app is for a clock of 100Hz...maybe I can divide a mega-herts ring oscillator... ---------------------------------------------------- "Peter Alfke" <palfke@earthlink.net> wrote in message news:3D93CE70.26C00B44@earthlink.net... > Every Xilinx FPGA you buy has already had a ring oscillator running in > it, since that is part of the test routine. Works like a champ, but can > be very fast if you make the loop too small. > You can also use it to measure chip temperature, and even temperature > gradients across the chip. > (Remember, frequency can easily be measured with one part per million > accuracy). > You can also use it as a controllable heater and make a thermostat out of > it. > > Peter Alfke > > > "Cool Morning ..." wrote: > > > Is it possible to build a Ring Oscillator in an FPGA chip? Any kind of > > tricks may do, but is it possible? > > > > Kelvin. >Article: 47508
Ray, I did a small experiment but it doesn't seem to Implement in ISE4. I used five inverters and ring them up... ---------------------------------------------------- "Ray Andraka" <ray@andraka.com> wrote in message news:3D93C71A.4944C757@andraka.com... > Yep, you can do that. Oscillation frequency depends on how many luts you > put in the ring. Great for characterizing the delay times in the part. > Good also for letting the magic smoke out of the part (and the board it is > sitting on) if you put too many of them in there. > > "Cool Morning ..." wrote: > > > Is it possible to build a Ring Oscillator in an FPGA chip? Any kind of > > tricks may do, but is it possible? > > > > Kelvin. > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 47509
> All you have to do is construct a ring feedback path with three 2-input > NAND gates and then pull the other inputs to a one. Synthesier must complain that a signal is driven by several sources.Article: 47510
On Fri, 27 Sep 2002 14:26:39 +1200, Jim Granville <jim.granville@designtools.co.nz> wrote: >> > Is it possible to build a Ring Oscillator in an FPGA chip? Any kind of >> > tricks may do, but is it possible? [snip] >- If making it long, make sure to have a INIT(Start/enable), that > drives every second NAND gate. > This forces it to start from a known DC state, otherwise you > can find there is more than one stable 'traveling wave' in your ring. Does this happen in silicon in practice? I once managed to prove to myself that this couldn't happen in the steady state. Any finite amount of dispersion would make all but the "fundamental" disappear. Of course, proving something to myself and proving something in a manner that survives peer review are different things :) Regards, Allan.Article: 47511
Allan Herriman wrote: > > On Fri, 27 Sep 2002 14:26:39 +1200, Jim Granville > <jim.granville@designtools.co.nz> wrote: > > >> > Is it possible to build a Ring Oscillator in an FPGA chip? Any kind of > >> > tricks may do, but is it possible? > [snip] > >- If making it long, make sure to have a INIT(Start/enable), that > > drives every second NAND gate. > > This forces it to start from a known DC state, otherwise you > > can find there is more than one stable 'traveling wave' in your ring. > > Does this happen in silicon in practice? Yes. We have seen this in CPLD, but I would expect it to be a universal CMOS effect. > > I once managed to prove to myself that this couldn't happen in the > steady state. Any finite amount of dispersion would make all but the > "fundamental" disappear. I think the digital nature of the system, is non linear enough that this ideal does not apply - ie you do not get a smooth reduction to 0ns wide pulses, instead some 'snap' occurs. - jgArticle: 47512
Sometimes I get an error box "Full compilation was cancelled due to an error" while compiling a design written in vhdl with Quartus 2 v2.1 (appers on lower version aswell), but there is no error in the Message window. It appears during the logic synthesizer is running. I have checked this vhdl code with Leonardo Spectrum too. No errors were found. But aslong I use LPM-functions with black boxes Quartus is running the logic synthesizer aswell. I'm compiling designs for 20K1500E and ARM-based Excalibur EPXA10. For compilation I use an P4 with 1GB RAM so hardware shouldn'd be the Problem, am I rigth? Does anyone have an idea? thanks Michael TornowArticle: 47513
Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote in message news:<qhk7l8jlgr.fsf@ruckus.brouhaha.com>... > lyqin@cti.com.cn (Leon Qin) writes: > > I can't find it on Xilinx Web site . > > You're looking for the wrong thing. Alliance isn't free. Webpack is free. AFAIK they will update their WebPack in the near future... Greetz, Thomas KurthArticle: 47514
> -----Original Message----- > From: Rick Filipkiewicz [mailto:rick@algor.co.uk] > Subject: Re: Timing accuracy with Modelsim > What about Verilog ? > Much easier to learn The usual take on this is that Verilog has a longer, shallower learning curve; VHDL is hard to get to grips with, but once you've mastered the basics it all makes pretty good sense, whereas you can write useful code in Verilog really easily, but it takes years to discover all its <cough> idiosyncrasies. > no bad memories of Pascal Ahem, which of the two languages (Verilog/VHDL) gives rise to code full of begin/end delimiters? My horror-memory of Pascal is of the innumerable 'end' delimiters that you tended to get after any complicated piece of code. Verilog suffers the same trouble. VHDL's block-oriented control structures make it much less messy. > IIRC the Verilog/VHDL overall useage ratio is > 45/55 with Verilog being much more commonly used in the > US and VHDL more common in Europe. I think that's about right for *design*. As you move towards the back-end of the design flow, Verilog increasingly dominates. -- Jonathan Bromley HDL Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project = Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 = 1AW, UK Tel: +44 (0)1425 471223 mail: = jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: = http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. = reserves all rights of privilege in respect thereof. It is intended for the use = of the addressee only. If you are not the intended recipient please delete = it from your system, any use, disclosure, or copying of this document = is unauthorised. The contents of this message may contain personal views = which are not the views of Doulos Ltd., unless specifically stated.Article: 47515
"Rajeev" <rrr@ieee.org> wrote in message news:c0f37b00.0209261119.6b5bc055@posting.google.com... > Wow! Learned a lot today. > <snip> > Only problem is that using MULT16x16(S)_PLUS.vhd from the AppNote, I > can't get the functional simulation to behave: simulation works if I > change the inputs > every 2nd clock or slower, but if the input holds for just 1 clock, > the outputs > aren't updated :-( I read the answers about VHDL pulse-swallowing in > VHDL simulation, and tried slowing down my simulation clock, but to no > avail. And I don't have this problem with LogiCore multipliers, it > seems to be something with > the MULT16x16(S)_PLUS.vhd... > Have you checked the time resolution you are specifying for the VHDL simulation? I have been caught out by simulating Unisim or Simprim DLL models when I set the time resolution to 1 ns, but it needed to be ps. The model output was just dead at 1 ns resolution, but it was fine if you selected ps resolution. Regards Alan -- Alan Fitch [HDL Consultant] DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. reserves all rights of privilege in respect thereof. It is intended for the use of the addressee only. If you are not the intended recipient please delete it from your system, any use, disclosure, or copying of this document is unauthorised. The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 47516
Cool Morning ... ha scritto nel messaggio <3d93b2da@news.starhub.net.sg>... >Is it possible to build a Ring Oscillator in an FPGA chip? Any kind of >tricks may do, but is it possible? > >Kelvin. Yes, I did it many times. But some software tool prevent rings. In this case, the trick is to insert in the ring a gate with an input connected to an external pin. Generally, a single inverter oscillates at too high frequency, so you have to connect more cells in chain and to instruct the software tool don't optimize it. For example, I tested ring oscillators in Altera EP1k30-2: single inverter: untestable 2 LCELL: 385 MHz 3 LCELL: 250 MHz 8 LCELL: 100 MHz 9 LCELL: 70 MHz Naturally, the frequency varies with voltage, temperature, from device to device, how the ring cells are placed and routed, etc. I agree with Ray, ring oscillators are power consuming and many oscillators on the same chip can damage it, also without you note high temperature externally. I experienced it :-( LuigiArticle: 47517
Hello, I'm trying to program CPLD device, which can't be found through non-standard cable. I would like to stimulate it myself to make sure it's alife. There is example on the Xilinx site http://toolbox.xilinx.com/docsan/xilinx4/data/docs/pac/trbshoot5.html, describing how to send IDCODE request. I'm confused, [1] the always-'1' TDI means BYPASS instruction?! [2] How does currently loaded instruction affect states sransitition and outputs? ThanksArticle: 47518
Most synthesis tools will not allow the loop. I find the easiest way to force
it is to instantiate the primitives.
Karl wrote:
> Ray,
>
> I did a small experiment but it doesn't seem to Implement in ISE4. I used
> five inverters and ring them up...
>
> ----------------------------------------------------
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3D93C71A.4944C757@andraka.com...
> > Yep, you can do that. Oscillation frequency depends on how many luts you
> > put in the ring. Great for characterizing the delay times in the part.
> > Good also for letting the magic smoke out of the part (and the board it is
> > sitting on) if you put too many of them in there.
> >
> > "Cool Morning ..." wrote:
> >
> > > Is it possible to build a Ring Oscillator in an FPGA chip? Any kind of
> > > tricks may do, but is it possible?
> > >
> > > Kelvin.
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47519Hello, Thanx for the reply. I require around 48K bits of memory. An XCV50E/XC2V40 should do the job. Thats fine. Now regarding your question about using memory in the existing FPGA. I have my core logic plus the memory in the existing FPGA. In the final product, the core logic will be converted to ASIC. But I am not sure about the memory. Because as I understand it is difficult to implement memory in ASIC of my required size (not digital ASIC) in terms of process as well as cost, compared to external chip. First of all, is this true? If so, I have to have another FPGA to implement memory, as you told. Regards, Nagaraj CS Ray Andraka <ray@andraka.com> wrote in message news:<3D930322.9D4E30A5@andraka.com>... > You could always use a second FPGA to do that. If you need just 1 memory, > then an XC2S15 should do the trick. I suspect a second small FPGA with > just enough size to fit the number of BRAMs you need is going to be less > costly than a special purpose dual port (read low volume and therefore > expensive) memory. Question is, why can't that be integrated into the > FPGA? If the issue is that you need a large bank of dual port memory, > then you would be better off using a traditional single ported memory plus > some logic in the FPGA to make it appear as a dual port memory. > > Nagaraj wrote: > > > Dear group members, > > I am using Dual Port BlockRAM (of CoreGen IP)in my design (Xilinx > > Virtex device). Now my system requirement is such that the DPRAM > > should reside outside the FPGA. > > I am searching for a Dual Port SRAM IC which is similar to the Dual > > Port Block RAM (of CoreGen IP). Except for the functionality > > (enable,reset etc.), other things like memory size, physical > > size,cost,timing doesn't matter for me. > > Could somebody please help in knowing the availability of an IC > > atleast close to my requirement? > > > > Regards, > > Nagaraj CS > > --Article: 47520
Furthermore I wanted to know how can the devices at beginning of a dasy-chain be in BYPASS mode meanwhile the following device loads its test-vector into BSR register? I know that all devices must be at the same mode at the same time, so if one of devices is bypassed then all devices must be bypassed (nobody catches the data).Article: 47521
(reposted due to news server uncertainties)
Hello folks,
I generated 2 filters using coregen - a singlerate and an interpolated
filter with the following common params:
coefficients: "1,3" (3 bits, signed, non-symmetric, fixed, optimisation
switched on)
input: 1 bit unsigned
parallel implementation with registered output
Zero Packing Factor = 4 for the interpolated filter.
Both filters take 9 slices on a xc2v40-fg256-5 using ISE 4.2.03i.
My question relates to why these filters should be the same size (in slices)
when the interpolated filter does "more".
Here are the mapping stats for both:
Singlerate:
Number of Slices: 9 out of 256 3%
Number of Slices containing
unrelated logic: 0 out of 9 0%
Number of Slice Flip Flops: 11 out of 512 2%
Total Number 4 input LUTs: 4 out of 512 1%
Number used as LUTs: 3
Number used as Shift registers: 1
Number of bonded IOBs: 11 out of 88 12%
Interpolated:
Number of Slices: 9 out of 256 3%
Number of Slices containing
unrelated logic: 0 out of 9 0%
Number of Slice Flip Flops: 11 out of 512 2%
Total Number 4 input LUTs: 5 out of 512 1%
Number used as LUTs: 3
Number used as Shift registers: 2
Number of bonded IOBs: 11 out of 88 12%
Looking at the post place and route floorplans of both, what jumps out is
that the singlerate case has 7 flip-flops being used on their own in slices
without the LUT (as an FG or an SRL16) whereas the interpolated case has
only 6 flip-flops on their own in slices.
It seems that, for the interpolated case, adding the 3 sample delay between
the filter taps (done with 3 SRL16s for the 3-bit signal) simply means that
coregen makes more efficient use of the logic - i.e. instantiates 1 less
flip-flop on its own.
It also seems that SRL16s are always mapped together with a flip-flop by the
tools (is this the case?) - presumeably with the flip-flop taking the last
delay of an N bit delay with the SRL16 doing N-1 delays (N <= 16) - is this
right.
Surely, then coregen could do a better job (i.e. less slices) of the
singlerate case since the interpolated filter simply requires more logic?
Or, could the slice cost of the singlerate case be reduced through some
clever manual floorplanning?
I realise that this post is a little hand-wavy and that you might not be
able to give me some categoric answers but I would appreciate your
thoughts/experience in these areas - even if you do put it all down to tool
"black magic" ;-) .
Thanks for your time,
Ken
Article: 47522Hi Chris, Ahh, the memories - my first computer was a cpc464. z80 is one of the few assembly languages I know AND like ;-) I have been thinking about building a z80 pc for some time, but as ever, time is the issue... Probably one of the most important points for choosing an fpga is what voltage the system will run at. I see that the ez80 is 3.3v, and you may be wanting to interface to 5V logic, so this is an important consideration for the FPGA if you want to keep things simple. Secondly, if this is a hobby project, you will probably want to stear clear of BGA packages. Thirdly, what is the job of the FPGA in the system? I should imagine you could integrate all of the following and more easily into a reasonably small FPGA. All this equates to needing quite a lot of IO. Basically stick the FPGA between the processor and the world. CRTC UART Memory control (ties with the CRTC) Interupt Logic Sound subsystem (I wonder about the possibility of having a hardware sprite accelerator in the FPGA, using device blockram for the sprites?) The ez80 has a built in UART, but you may want more flexibility, the same goes for interupts. I should say I'm not familiar with Altera. If I was to sugest I Xilinx FPGA, I'd say go for the Virtex (or Spartan II) family, as you have 5 volt tolerenec, which might make life easier. There are two non BGA packaging options, I'd reccomend the larger (pq/hq240) as this gives 166 user IO pins (looking at the virtex datasheet) - if you want to integrate all the above into one device you'll probably need it! A wide variety of logic capacities are availible with this packaging option, so you do not have to decide on the exact device to soon. Also, the DLLs will probably be verry usefull for running the FPGA at (e.g.) 2x the clock generated by the ez80. I don't see there being a need for more than 1 FPGA, but... --- Further, I'd be neat to have a CPLD or some such acting as an interface between the system and copious user digital IO. I wish I could have done that in the past, rather than soldering 74 logic all over veroboard and trying to find a source for the 50 way header... --- I hope the above is of some use to bringing Arnold back to life! ta cds --- ChristopheGuelff (christopheguelff@aol.com) wrote: : If www.cpcng.org doesn't work, please try http://cpcng.kriga.net or : http://www.cpcng.com : Concerning the FPGA job : We don't know how FPGA(s) we must put on the board : : this depends on the type of FPGA chosen and how many I/O pins and gates the : FPGA requires. Ideally we need someone able to design and debug the FPGA and : able to give some idea of how many FPGA's will likely be required. My feeling : is that we need quite a few FPGA I/O lines, a large number relative to the : amount of logic gates required - to avoid going for an expensive FPGA or one a : very high density e.g. BGA package, we should perhaps choose 2 FPGA's. : We need someone able to program the FPGA and choose as soon as possible how : FPGA we need. : What the FPGA must contains is described on our prototype's webpage : http://www.arnold6.com or http://www.hanssummers.com/computers/cpcng : Concerning the project : Our aim is to build a free sucessor of the : Amstrad464/6128 computer range by using ez80 and with somes enhanced video and : sound capabilities, a new OS etc. : Regards, : Chris : www.cpcng.orgArticle: 47523
Ray, Or put a nand gate in the loop. Austin Ray Andraka wrote: > Most synthesis tools will not allow the loop. I find the easiest way to force > it is to instantiate the primitives. > > Karl wrote: > > > Ray, > > > > I did a small experiment but it doesn't seem to Implement in ISE4. I used > > five inverters and ring them up... > > > > ---------------------------------------------------- > > > > "Ray Andraka" <ray@andraka.com> wrote in message > > news:3D93C71A.4944C757@andraka.com... > > > Yep, you can do that. Oscillation frequency depends on how many luts you > > > put in the ring. Great for characterizing the delay times in the part. > > > Good also for letting the magic smoke out of the part (and the board it is > > > sitting on) if you put too many of them in there. > > > > > > "Cool Morning ..." wrote: > > > > > > > Is it possible to build a Ring Oscillator in an FPGA chip? Any kind of > > > > tricks may do, but is it possible? > > > > > > > > Kelvin. > > > > > > -- > > > --Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com > > > > > > "They that give up essential liberty to obtain a little > > > temporary safety deserve neither liberty nor safety." > > > -Benjamin Franklin, 1759 > > > > > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 47524
Karl wrote: > Peter, > > You mentioned the chip has already a ring oscillator on it, but how can I > find it? How can I make > use of it? Karl, you misunderstood. There is no dedicated ring oscillator. We just configure one, as others have already described. Does your 100 Hz frequency have to be all internally, or can you dedicate some pins and external RC? Peter Alfke, Xilinx
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