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Ben Twijnstra wrote: > > Hiya, > > Just to make sure that everyone knows my bias: I have worked for both Mentor > Graphics and Altera (and work for neither at the moment). While at Altera I > have pushed hard for the Linux port and a whole bunch of other improvements > in Quartus (IBIS support etc) so I'm following development closely. > > I have been checking out the improved HDL support in Quartus 2.1 and I must > say I am impressed with the stability of the parser. I have run several > designs that Leonardo is having problems with (from generating wrong logic > to downright crashes) through Quartus to see whether I could get one of > those "Internal Error" things to pop up, and so far it has eaten everything > I thew at it. > > As to logic optimization, that's another story. I am not saying that the > optimizer is particularily bad, but generally speaking I would say that > Leonardo and Synplify are definitely doing a better job. > > I'm too busy doing other things to run proper benchmarks, but on average I > would guesstimate that the Quartus optimizer generates logic that is 10-15% > larger and between 5 and 10% slower than what the Big Two cough up, but > part of that really depends on your design. Data path operations seem to > clearly be done more efficiently by Leonardo, while control stuff seems to > be pretty much on par. Interesting summary. So how does it handle/expedite manual floorplanning ? ie do you think (extra) manual floorplanning would improve the optimise to the point of parity with the others ? - jgArticle: 46951
Wishing for the non-applicable? The ands/ors are implemented in the silicon at the TBUF and PIP locations. I saw an illustration in a datasheet at one point that showed how it's done at the gate level. There are no conversions of "virtual TBUFs" into general logic - it's entirely implemented with the TBUF emulating silicon. "No LUTs were harmed in the making of this TBUF." The only difference between the "virtual" TBUF and a real one is that when no TBUFs drive the wire, the result is a logic high and when there are multiple drivers *any* logic low will force the output low. I've simulated the behavior - in RTL code rather than post P&R, I think - with weak-high/strong-low drivers and a pullup. Think of it in similar terms and you have the real results. Niv wrote: > I have a Virtex design with an internal tristate bus. > I know it isn't REALLY a tristate bus, but emulated with OR's feeding to > ANDs, etc. > > However, is thereany way at all I can view the real logic built by the PAR > tool (ISE 4.2i). The editor only shows TBUFs, but this isn't real silicon. > > Or am I wishing for the impossible? > > TIA, Niv.Article: 46952
Niv wrote: > > I have a Virtex design with an internal tristate bus. > I know it isn't REALLY a tristate bus, but emulated with OR's feeding to > ANDs, etc. > > However, is thereany way at all I can view the real logic built by the PAR > tool (ISE 4.2i). The editor only shows TBUFs, but this isn't real silicon. > > Or am I wishing for the impossible? > > TIA, Niv. Xilinx reduced the number of TBUFs in the Virtex parts relative to the number of CLBs, but they did not eliminate them. Per the Virtex data sheet there are 2 TBUF for every 4 LUT and FF (1 CLB). BUFTs Each Virtex CLB contains two 3-state drivers (BUFTs) that can drive on-chip busses. See Dedicated Routing, page 7. Each Virtex BUFT has an independent 3-state control pin and an independent input pin. However, they are a slow resource becoming less and less effective and more and more expensive as chips get larger. The Virtex2 family has two for every 8 FF and LUT (1 CLB) and they are implemented with logic and not true three state drivers. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46953
Hi, An FPGA is a Field Programmable Gate-Array, a programmable ASIC. All digital, I am not aware of any devices that allow what I think it is your talking about. Good Luck, Mike D. "Lu Hu" <meta2000@ustc.edu> wrote in message news:3d80d0cc$0$3925$b45e6eb0@senator-bedfellow.mit.edu... > Hello, > > I have never used FPGA before. Could anybody tell me if it is possible to > make a 2-D resistor array (N*M) using FPGA? The power input of each resistor > needs to be controlled individually. It is preferrable that the FPGA board > has built-in array of cavities. Thank you! > > -meta > >Article: 46954
Actually there are programmable analog devices. I did hear of such things and I know they exist. "Mike D" <mdelphia@snet.net> wrote in message news:jy9g9.960$or5.371977262@newssvr10.news.prodigy.com... > Hi, > An FPGA is a Field Programmable Gate-Array, a programmable ASIC. All > digital, I am not aware of any devices that allow what I think it is your > talking about. > > Good Luck, > > Mike D. > > "Lu Hu" <meta2000@ustc.edu> wrote in message > news:3d80d0cc$0$3925$b45e6eb0@senator-bedfellow.mit.edu... > > Hello, > > > > I have never used FPGA before. Could anybody tell me if it is possible to > > make a 2-D resistor array (N*M) using FPGA? The power input of each > resistor > > needs to be controlled individually. It is preferrable that the FPGA board > > has built-in array of cavities. Thank you! > > > > -meta > > > > > >Article: 46955
While Altera claims some improvement in their floorplanner for
Quartus II 2.1, I personally didn't see much change compared to QII 2.0.
I was not able to run "Timing Closure Floorplanner" which is supposed to
be a new feature of QII 2.1 because the QII 2.1 Web Edition's license
doesn't allow users to use LogicLock. (The screen said I need to have
LogicLock license to run "Timing Closure Floorplanner.")
The regular QII 2.1 floorplanner still has the same problem as the QII
2.0 floorplanner had that it is really hard to see what resources of the
chip (LUTs and FFs) are actually being used compared to Xilinx's
floorplanner.
Plus, Altera's P&R (Altera calls it a fitter.) still has a bad habit of
adding "~1" to LUTs (i.e., ix7423 becomes ix7423~1), allowing the P&R to
ignore the location specified by the floorplanner. (ix7423's location
information specified by the floorplanner will be ignored because it
won't apply to ix7423~1.)
As long as those two problems aren't fixed, I don't feel like wasting
too much time with Altera. (I will remain a Xilinx user.)
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Jim Granville wrote:
>
>
> Interesting summary.
>
> So how does it handle/expedite manual floorplanning ?
>
> ie do you think (extra) manual floorplanning would improve the
> optimise to the point of parity with the others ?
>
> - jg
Article: 46956
Ben Twijnstra wrote:
>
> Hiya,
>
>
> I have been checking out the improved HDL support in Quartus 2.1 and I must
> say I am impressed with the stability of the parser. I have run several
> designs that Leonardo is having problems with (from generating wrong logic
> to downright crashes) through Quartus to see whether I could get one of
> those "Internal Error" things to pop up, and so far it has eaten everything
> I thew at it.
>
Do you know if the QII 2.1's built-in synthesis tool can
generate an EDIF netlist?
I personally hate using synthesis tools that generate proprietary or
non-text netlists.
Speaking of LeonardoSpectrum, Ben, if you worked at Mentor
Graphics, do you know why LeonardoSpectrum's GUI used to be sooooooo
buggy until LeonardoSpectrum 2002a? (I still remember Altera OEM version
LeonardoSpectrum 2001a.028's GUI used to crash so easily.)
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 46957Hello, The XC2S50-PQ208 has 140 IOs as stated in the Xilinx data sheet. I just approved a requested design change to the replace the XC2S50-PQ208 ( Spatan II ) with with E version because the data sheet states it has 146 IOs. I only count 142. I have counted two times. Is Xilinx counting the 4 GCLKs as IOs. If they have changed the rules on their IO counts in this way I will be very annoyed. I need all of the documented 146 IOs. Can someone please tell me were are the 4 missing IOs on the Spartan IIE -PQ208 package ( device size 50K gates and up ) ? DanArticle: 46958
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3D81172C.8E69AA16@yahoo.com>... > Niv wrote: > > > > I have a Virtex design with an internal tristate bus. > > I know it isn't REALLY a tristate bus, but emulated with OR's feeding to > > ANDs, etc. > > > > However, is thereany way at all I can view the real logic built by the PAR > > tool (ISE 4.2i). The editor only shows TBUFs, but this isn't real silicon. > > > > Or am I wishing for the impossible? > > > > TIA, Niv. > > Xilinx reduced the number of TBUFs in the Virtex parts relative to the > number of CLBs, but they did not eliminate them. > > Per the Virtex data sheet there are 2 TBUF for every 4 LUT and FF (1 > CLB). > > BUFTs > Each Virtex CLB contains two 3-state drivers (BUFTs) that > can drive on-chip busses. See Dedicated Routing, page 7. > Each Virtex BUFT has an independent 3-state control pin > and an independent input pin. > > > However, they are a slow resource becoming less and less effective and > more and more expensive as chips get larger. The Virtex2 family has two > for every 8 FF and LUT (1 CLB) and they are implemented with logic and > not true three state drivers. > > Hi, what is the difference between BUFT and TBUF ???? Best regards, Muthu > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46959
To make your simulation job easier with a external VHDl/Verilog simulator like Modelsim, there is a handy command in Quartus II, if you have created the vectors using the Quartus II waveform editor, and you want to convert the vwf into a testbench VHDL/Verilog file; Do the following in order: 1. Processing->Start Analysis and Elaboration, if the design has not been compiled before 2. Open the waveform file (vwf) in the waveform editor 3. Tools->Export Current File As.. (you can convert the vectors into VHDL or Verilog testbenches. You can check it out with the fir.vwf file that is part of the Quartus II tutorial. 4. This will create fir.vht in the project directory. -ds "Prashant" <prashantj@usa.net> wrote in message news:ea62e09.0209110814.2178ee93@posting.google.com... > Hi, > > I'm trying to develop a design and prototype on the A15E board from > Altera. This is the design flow I plan to follow. > > 1. Write RTL. > 2. Synthesize RTL in Quartus 2. > 3. Simulate the design using Quartus 2 simulator. > 4. After the simulation looks correct, program the device on the > board. > > I have seen a lot of people recommend Modelsim for simulations and > Leonardo/Synplicity for synthesis. I understand the reasons for using > these tools. > > But, instead if I followed the route of synthesis, place & route and > simulation in Quartus 2, would my design work in the FPGA on the board > ? I believe it should. Is there anything I should be careful about ? > > Do let me know. > > Thanks, > PrashantArticle: 46960
The internel structure of Virtex,you describe as a 3-State Logik is modelled as a system of Transducrors, which do not need Pullups or pulldowns. If you go outside , a Pullup(Pulldown) after the Pad-Cell should be instanciated. As a matter of fact this Pullup(Pulldown), realized on silicon is really a Source( Sink) of current, which is only available when the FPGA is loaded. "Anjan" <anjanr@yahoo.com> wrote in message news:5a5faf7b.0208292039.17074bbc@posting.google.com... > I am implementing a tristate bus in virtex. Should the bus be pulled > up or can they be left as it is?Article: 46961
>While I'm a big "information needs to be free" kind of guy, it seems >kind of strange to me that the primary contributers are individuals, >and the main beneficiaries (financially) are business entities. >Aren't these kinds of projects usually handled under a "use limited to >not for profit" arrangement? Kind of like shareware WS-FTP, if you're >using it at school go ahead, but if you're making money using it, you >shell out your $30. Otherwise all that we've accomplished is reducing >corporate NRE at engineers' expense. That's one reasonable way to do things. But I think you are missing the big picture on the open source movement. I'll second Hamish's suggestion to read Eric Raymond's book - Cathedral and Bazaar. He's got a good section in there on Cisco writing a print spooler package. They wrote it because they needed it. Then they gave it away so they wouldn't have to maintain it. Other users would do that, and enhance it too. So roughly, they get back free maintaince. (I might have scrambled the details, but I think that's the right idea.) In the software world, it's common for companies using open source software to have people doing serious work on a package and sending their fixes or improvements back to the community. The community will then maintain things you are interested in. It also earns good karma in case you want help tracking down a problem. I'm not sure Opencores is over the hump yet. For small things it's as easy/cheap to reinvent the solution as it is to integrate some external package into your project. For large complicated cores/packages it really helps to have lots of users helping to find (and fix) all the bugs. Let me ask a similar question. Why do people contribute to this newsgroup? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 46962
Dan wrote: > > Hello, > > The XC2S50-PQ208 has 140 IOs as stated in the Xilinx data sheet. > > I just approved a requested design change to the replace the XC2S50-PQ208 > ( Spatan II ) with with E version because the data sheet states it has 146 > IOs. I only count 142. I have counted two times. Is Xilinx counting the 4 > GCLKs as IOs. If they have changed the rules on their IO counts in this way > I will be very annoyed. I need all of the documented 146 IOs. Can someone > please tell me were are the 4 missing IOs on the Spartan IIE -PQ208 package > ( device size 50K gates and up ) ? > > Dan I have not done a complete count of one of these parts lately, but I am pretty sure that not only do they count the clock inputs as "IOs", they count all the dual use pins that are used during configuration and/or other functions depending on how programmed (CCLK, DOUT, D0/DIN, INIT...). Just for the fun of it I counted the IOs for the XC2S150E-FG456 and XC2S200E-FG456. Interestingly enough I got the right number for the XC2S200E-FG456 assuming that the GCLKs are counted as IOs, 289. But for the XC2S150E-FG456, I got 2 pins more than the data sheet number, 263. Of course I double checked my counts. I did them by banks to make sure I did it right. So I don't know for sure, but I belive the data book is off in this case. Hmmmm... checking the 100E I count two less than the data book. But the point it, they count GCLKs, INIT... all of the pins that can be used as IOs in any way, shape or form. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46963
> -----Original Message----- > From: Lu Hu [mailto:meta2000@ustc.edu] > I have never used FPGA before. Could anybody tell me if it is > possible to > make a 2-D resistor array (N*M) using FPGA? The power input > of each resistor > needs to be controlled individually. It is preferrable that > the FPGA board > has built-in array of cavities. Thank you! I'm guessing here, but.. are you trying to test some kind of thermal imaging system? You cannot "make a 2-D resistor array" using an FPGA, not even an analog FPGA (the basic elements on analog FPGAs are much more complicated than resistors). However, it _is_ possible to CONTROL a 2-D resistor array using an FPGA. You can control the power input using pulse-width modulation, if the modulation period is much shorter than the thermal time constant of your heating elements. But if N,M are large then there could be some tricky problems concerned with the large number of pins you need to control. If you wish to use row/column addressing of the matrix, you will need a diode in series with each resistor. This will make it much more difficult to determine the power delivered to each resistor. Give us some more details of what you need, and perhaps you will receive some interesting suggestions. It may also be a good idea to take your problem to sci.electronics.design which has some contributors with a lot of instrumentation experience (and some contributors with a nice line in flame :-) ). -- Jonathan Bromley HDL Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project = Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 = 1AW, UK Tel: +44 (0)1425 471223 mail: = jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: = http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. = reserves all rights of privilege in respect thereof. It is intended for the use = of the addressee only. If you are not the intended recipient please delete = it from your system, any use, disclosure, or copying of this document = is unauthorised. The contents of this message may contain personal views = which are not the views of Doulos Ltd., unless specifically stated.Article: 46964
hello! I've just read an interesting thread about metastability and this made me think about making a hardware random bit generator. Exploiting metastability seems to be interesting. Just put to D an alternating sequence which toggles with clock. Add some smart routing to make it hit the hold window. And have a long time thinking how to read metastable Q without passing metastability to the rest of the circuit.... Has anyone done something like this? Or heard about it? I'm thinking about implementing it. Any help and comments appreciated. -- -- Wojciech Piechowski - wpiechowski@acm.org - Gadu-Gadu 494156 --Article: 46965
The ispPAC20 & 30 do also have DAC's. Also analogue programmable devices. Furthermore i havn't used these devices but i am doing research at it right now. So if anyone could send me good information or user experiences are very welcome tnx dennis sneijers, the netherlands Lorenzo Lutti wrote: > > "Neil Franklin" <neil@franklin.ch.remove> ha scritto nel messaggio > news:6u7kht5vv0.fsf@chonsp.franklin.ch... > > > So I doubt you will find an FPGA with > > hardwired DAC circuits. > > There are the FPAAs, or "analog FPGA". For example: > > www.anadigm.com > > By the way, has anyone used this kind of devices? I'm not even able to > download their trial software (the connection is always reset before the > end, and after few retries their web server apparently bans my IP). > > -- > LorenzoArticle: 46966
"Stan" <vze3qgji@verizon.net> wrote: > But tell me, why would anyone implement scan in an FPGA? Scan is usually > used at wafer probe, and presumably Xilinx tests them using their own test > configuration at wafer probe. Scan insertion is also necessary for runtime bist. In critical systems you like to know, when your chip fails. Another point is, that a boardlevel test may require boundary scan regardless if you use an fpga or an asic. bye ThomasArticle: 46967
Thanks, Jonathan. Your guess is very close. :) Actually I want a 2-D array of tiny heating points to heat water (sounds interesting, isn't it? ). We can fabricate the resistor array but wiring could be a big problem when N*M is very large. As what you said, we wish to use row/column addressing of the matrix instead of wiring directly to each resistor. I wish there is something that could be used as a 2-D switch with built-in resistor array (it is crucial since we need N*M connecting wires if the control part and the resistor array are separate.) -meta "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:xVYkt6vWCHA.3472@lucy.doulos.com... > -----Original Message----- > From: Lu Hu [mailto:meta2000@ustc.edu] > I have never used FPGA before. Could anybody tell me if it is > possible to > make a 2-D resistor array (N*M) using FPGA? The power input > of each resistor > needs to be controlled individually. It is preferrable that > the FPGA board > has built-in array of cavities. Thank you! I'm guessing here, but.. are you trying to test some kind of thermal imaging system? You cannot "make a 2-D resistor array" using an FPGA, not even an analog FPGA (the basic elements on analog FPGAs are much more complicated than resistors). However, it _is_ possible to CONTROL a 2-D resistor array using an FPGA. You can control the power input using pulse-width modulation, if the modulation period is much shorter than the thermal time constant of your heating elements. But if N,M are large then there could be some tricky problems concerned with the large number of pins you need to control. If you wish to use row/column addressing of the matrix, you will need a diode in series with each resistor. This will make it much more difficult to determine the power delivered to each resistor. Give us some more details of what you need, and perhaps you will receive some interesting suggestions. It may also be a good idea to take your problem to sci.electronics.design which has some contributors with a lot of instrumentation experience (and some contributors with a nice line in flame :-) ). -- Jonathan Bromley HDL Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. reserves all rights of privilege in respect thereof. It is intended for the use of the addressee only. If you are not the intended recipient please delete it from your system, any use, disclosure, or copying of this document is unauthorised. The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 46968
Could you tell me where I can find some info. about these devices? Thank you. "Roger King" <roger@king.com> wrote in message news:cYag9.5574$8b1.4998@news01.bloor.is.net.cable.rogers.com... > Actually there are programmable analog devices. I did hear of such things > and I know they exist. > > > > "Mike D" <mdelphia@snet.net> wrote in message > news:jy9g9.960$or5.371977262@newssvr10.news.prodigy.com... > > Hi, > > An FPGA is a Field Programmable Gate-Array, a programmable ASIC. All > > digital, I am not aware of any devices that allow what I think it is your > > talking about. > > > > Good Luck, > > > > Mike D. > > > > "Lu Hu" <meta2000@ustc.edu> wrote in message > > news:3d80d0cc$0$3925$b45e6eb0@senator-bedfellow.mit.edu... > > > Hello, > > > > > > I have never used FPGA before. Could anybody tell me if it is possible > to > > > make a 2-D resistor array (N*M) using FPGA? The power input of each > > resistor > > > needs to be controlled individually. It is preferrable that the FPGA > board > > > has built-in array of cavities. Thank you! > > > > > > -meta > > > > > > > > > > > >Article: 46969
> -----Original Message----- > From: meta [mailto:meta2000@ustc.edu] > Your guess is very close. :) Actually I want a 2-D array of tiny > heating points to heat water (sounds interesting, isn't it? ). > We can fabricate the resistor array but wiring could be a big > problem when N*M is very large. As what you said, we wish > to use row/column addressing of the matrix instead of > wiring directly to each resistor. I wish there is something that > could be used as a 2-D switch with built-in resistor array > (it is crucial since we need N*M connecting wires if the > control part and the resistor array are separate.) I have a really, really cool idea for how to do this if you could build an array of DIODES instead of resistors. If you make an array of resistors, you need a diode in series with each one in order to achieve XY addressing. So, why not get rid of the resistors altogether and use the diodes as the heating elements? Trouble is, diodes are very non-linear and so it would be hard to control the power input to each. But I know how to fix that. Continue the conversation by private email if you're interested - it's not appropriate for comp.arch.fpga. Cheers -- Jonathan Bromley HDL Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project = Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 = 1AW, UK Tel: +44 (0)1425 471223 mail: = jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: = http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. = reserves all rights of privilege in respect thereof. It is intended for the use = of the addressee only. If you are not the intended recipient please delete = it from your system, any use, disclosure, or copying of this document = is unauthorised. The contents of this message may contain personal views = which are not the views of Doulos Ltd., unless specifically stated.Article: 46970
Dear Mark,
Try setting the depth of the chipscope sample storage memory
to 1024 or more. In my VirtexII design this forces the ILA BRAMS to be
less than 36 bits wide. So, 1024 is 18 bits wide, 2048 is 9 bits wide
etc.
HTH, Syms.
mark <mark@pac.net> wrote in message news:<3D7EDEFE.AC422DC8@pac.net>...
> Hello,
>
> I'm working on a Xilinx XC2V6000 design which will make use of nearly
> all (144) of the embedded multipliers and am trying to use Chipscope at
> the same time. I believe that Chipscope uses the block ram in a x36
> configuration, because I am getting PAR "unroutable" errors now that the
> number of multipliers is growing, due to design module integration.
> When the number of multipliers + the number of Chipscope block rams is
> about 144, or less, there are no PAR errors. Also, I've read (in Google
> and the Xilinx datasheets) that if a block ram and the adjacent
> multiplier are used, then the width of the block ram is limited to x18
> or less, so that the multiplier can be used, due to routing between the
> multiplier and block ram.
>
> The basic flow is: VHDL -> synthesis -> Chipscope Inserter -> Xilinx
> tools. I've looked at the fpga using FPGA editor and it does seem that
> the block ram is used in a x36 configuration.
>
> Could anyone tell me if this sort of issue is true when using the
> embedded multipliers and Chipscope? If so, is there a work-around, for
> validation/debugging? Can Chipscope use the block ram in a different
> configuration?
>
> Thank you for your time,
> Mark
Article: 46971Wojciech Piechowski wrote: > > hello! > > I've just read an interesting thread about metastability and this made me > think about making a hardware random bit generator. Exploiting > metastability seems to be interesting. Just put to D an alternating > sequence which toggles with clock. Add some smart routing to make it hit > the hold window. And have a long time thinking how to read metastable Q > without passing metastability to the rest of the circuit.... > > Has anyone done something like this? Or heard about it? I'm thinking about > implementing it. Any help and comments appreciated. Resolving the metastable state in another FF stage or two would not be a problem. That is what is going on in a cross clock domain synchonizer. The first FF can not be made stable and always has a chance of becoming metastable. But the following stages have a much, much reduced chance of being metastable. But, to have a *useful* random number generator, the values must have certain properties. One of them is that the distibution must be even. If you are generating a stream of 1s and 0s, then you must have half 1s and half 0s. It would be very, very hard to control the metastability to get this even distribution. Partly this is because the delay is a function of temperature and voltage which you will not be able to control sufficiently. I don't see how this circuit could ever be useful. Distirbution of values is a very difficult issue to control in general. I have seen a random generator based on diode noise have problems with distribution. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46972
Can you tell us typical values of N,M and power in a single resistor ? -rajeev- ---------------- "Lu Hu" <meta2000@ustc.edu> wrote in message news:<3d80d0cc$0$3925$b45e6eb0@senator-bedfellow.mit.edu>... > Hello, > > I have never used FPGA before. Could anybody tell me if it is possible to > make a 2-D resistor array (N*M) using FPGA? The power input of each resistor > needs to be controlled individually. It is preferrable that the FPGA board > has built-in array of cavities. Thank you! > > -metaArticle: 46973
Rick, I thought of using the DCM's variable phase shift to "keep" the metastability region in the right spot, but that does two things, one it removes a degree of randomness, and two, it puts the count of metastable events into a mode where its rate or occurences, are predictable (ie non-random rate?). Like many things that appear random, metastability does't seem so random upon closer inspection. It is just a bad thing that happens at a given probability for any specific condition. The teaser is that if you had it in the region you want, and you use the phases of the DCM to sample inside the region of metastability, it might be interesting to see what kind of distribution you get. For example, sample at 90 degrees and 180 degrees. If you get both equal, call that a 1, if they are not both equal, call that a zero. Don't look at this "coin toss" unless the event was metastable (i.e. the data had not settled). I suspect that the distribution of this is not good, as longer metastable events are much more unlikely than shorter metastable events (how long the ball balances on the hill before it rolls off....). Even though the distribution is not evenly distributed (ie it may be gaussian), it still might be useful. Perhaps sampling at closer phases would even out the probability of a 1 or 0 to closer to 50%....... Austin rickman wrote: > Wojciech Piechowski wrote: > > > > hello! > > > > I've just read an interesting thread about metastability and this made me > > think about making a hardware random bit generator. Exploiting > > metastability seems to be interesting. Just put to D an alternating > > sequence which toggles with clock. Add some smart routing to make it hit > > the hold window. And have a long time thinking how to read metastable Q > > without passing metastability to the rest of the circuit.... > > > > Has anyone done something like this? Or heard about it? I'm thinking about > > implementing it. Any help and comments appreciated. > > Resolving the metastable state in another FF stage or two would not be a > problem. That is what is going on in a cross clock domain synchonizer. > The first FF can not be made stable and always has a chance of becoming > metastable. But the following stages have a much, much reduced chance > of being metastable. > > But, to have a *useful* random number generator, the values must have > certain properties. One of them is that the distibution must be even. > If you are generating a stream of 1s and 0s, then you must have half 1s > and half 0s. It would be very, very hard to control the metastability > to get this even distribution. Partly this is because the delay is a > function of temperature and voltage which you will not be able to > control sufficiently. I don't see how this circuit could ever be > useful. > > Distirbution of values is a very difficult issue to control in general. > I have seen a random generator based on diode noise have problems with > distribution. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46974
Lu Hu wrote: > > Hello, > > I have never used FPGA before. Could anybody tell me if it is possible to > make a 2-D resistor array (N*M) using FPGA? The power input of each resistor > needs to be controlled individually. It is preferrable that the FPGA board > has built-in array of cavities. Thank you! > > -meta Reading this thread I see that the respondents have all been thinking too "linearly", if you will excuse the pun. You can easily control a "virtual" resistor in a digital FPGA. Consider a switched capacitor filter. Switches are used to control the rate that a capacitor is used to move current from one node to another. For currents at frequencies well below the Nyquist rate of the switching, this appears to be a continuous resistor. Certainly a heating effect would have to heat enough mass to mask the "switching noise". So you can use a simple digital counter with a threshold compare to enable a FF divide by two as the heater. The heating FF should run at a very high rate to produce the maximum heating effect. The counter/compare circuit should run at a slower rate so that it does not produce significant heat itself. Or you can use a large number of heating FFs controlled by each counter to produce more heat than the counter. The length of the counter will be determined by the control resolution you need to have over the circuit. As with most simple solutions, the devil is in the details. If you need further help with this, drop me an email at the address below. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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