Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote in message news:<3bea5746.123877786@netnews.agilent.com>... > On 7 Nov 2001 22:06:31 -0800, assaf_sarfati@yahoo.com (Assaf Sarfati) > wrote: > > >allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote in message news:<3be88ba4.6211972@netnews.agilent.com>... > >> On 6 Nov 2001 06:42:09 -0800, assaf_sarfati@yahoo.com (Assaf Sarfati) > >> wrote: > You say you looked at the generated gate level VHDL file (I assume > that's what you mean by "time_sim.vhd") and saw delays in the VHDL. > There are no delays in the time_sim.vhd itself, but everything is connected by X_BUF components. I've GREPed the Active-HDL libraries, and there is an X_BUF component in the simprim_VITAL.vhd file; it inserts a VITAL delay. I haven't tried to analyze everything in detail, since it's very unreadable code, and I am not expert in VITAL (or I wouldn't have started this thread). > I'm using Alliance 3.x, and there are no delays in the code generated > by ngd2vhdl, and the documentation doesn't describe any options for > adding delays. > > Are you sure you are looking at the file generated by ngd2vhdl and not > some other tool (such as your VHDL synthesiser)? Yes; at least it's generated by a tool called by the Flow Engine, and saved in the directory used to save P&R results and logs. > > What is the "Virtex library source?" Do you mean the simprim or > unisim source? If so, I don't recommend changing it. Your changes > may be lost when you install a service pack. > > Regards, > Allan. I am not too sure about which file, since I've done this change some time ago, as part of trying to run the back-annotation VHDL, and lost it since... I am aware that the change may be lost, since I've lost it already. Regards AssafArticle: 36526
Assaf Sarfati <assaf_sarfati@yahoo.com> wrote: > hamish@cloud.net.au wrote in message news:<3be93443$0$385$afc38c87@news.optusnet.com.au>... >> Assaf Sarfati <assaf_sarfati@yahoo.com> wrote: >> > As far as I could see, Synplicity simply ignored syn_noclockbuf in the >> > HDL code, since it know better than me what was and what wasn't a clock... >> >> It does work, but you usually have to put it inside your entity section; >> inside the architecture doesn't work. > How can I put the attribute in the entity? after all, it is an internal > signal within the architecture... Oh, I must have misunderstood. Just use syn_noclockbuf, should work fine. I've used it successfully. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 36527
Steven Derrien <sderrien@irisa.fr> wrote: > 1) I guess that one has to simulate the VHDL model of the annotated > placed & routed design; and trace all primitives activity for a while to > get a good idea of the circuit behavior, however, for large design, this > is likely to be VERY time consuming, if not impossible due to the tool > stability or PC memory limits. Can someone give his opinion about this ? That's about right. I did run an Xpower analysis a couple of months back. I used post-map VHDL (not post-route), as I didn't see a lot of extra advantage in having a routed design. I assume you do need all the internal nodes in the VCD file, so you do need post-map or post-route code. I ran about 100us of simulation, and got a 500Mb VCD file. Then I fed it into Xpower, which took over two hours to read in the waveforms and do the analysis. My design uses about 35% of a 2V6000. From memory it was using 200-400Mb of so during the analysis, which is reasonable given that par uses up to 700-800 on this design (off the top of my head). > 2) Xilinx support says one has to use Modelsim to guarantee proper work > of the tool Don't know; I used ModelSim. As long as your simulator's VCD support is decent it shouldn't matter. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 36528
In comp.arch.fpga Jonathan Bromley <Jonathan.Bromley@doulos.com> wrote: > In article <3beabd8f$0$230$cc9e4d1f@news.dial.pipex.com>, Tony Benham > <tonyb@nospam.kerrisway.freeserve.co.uk> writes >>I deal in digital video which uses 10 bit vectors. I often want to assign a >>hex no to a 10 bit slv, but I've not found a neat way of doing it. VHDL 93 >>supports this for slv's that are multiples of 4 bits, but seems to not deal >>with other nos of bits. Is there any way of dealing wth this ? ie I want to >>do "slv(9 DOWNTO 0) <= Hex 3AC ;" in effect ? > Yes, it's irritating. Well, you could write slv(9 downto 0) <= "11" & x"AC"; but that isn't very nice really. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 36529
Kenneth <small__lee@hotmail.com> wrote: > In the Synplify Pro, there is a field for me to specify the required > operating frequency. However no matter what value(e.g. 40MHz) I set, > the implementation will treat all the clock(1x, 2x and 4x) have the > same timing constraint of 40MHz(this is shown in the Place and Route > Report after the implementation). As a result, I got a poor > implementation result. Synplify is a bit unfriendly in this regard, IMHO. I haven't had any luck in setting the frequencies of the generated clocks in the Synplify constraints file/editor. > Even I add the the following constraints in the UCF file, > NET "CLOCK/dcm0_clk1x" TNM_NET = "CLOCK/dcm0_clk1x"; > TIMESPEC "TS_CLOCK_dcm0_clk1x" = PERIOD "CLOCK/dcm0_clk1x" 25 ns HIGH 50 > %; > NET "CLOCK/dcm0_clk2x" TNM_NET = "CLOCK/dcm0_clk2x"; > TIMESPEC "TS_CLOCK_dcm0_clk2x" = PERIOD "CLOCK/dcm0_clk2x" 12.5 ns HIGH > 50 %; > NET "CLOCK/dcm0_clkfx" TNM_NET = "CLOCK/dcm0_clkfx"; > TIMESPEC "TS_CLOCK_dcm0_clkfx" = PERIOD "CLOCK/dcm0_clkfx" 12.5 ns HIGH > 50 %; > (the hierarchy is Top_level -> CLOCK ->DCM) Probably the NCF from Synplify is overriding your UCF. > So, what should be the correct method to set the timing in my case? I suggest not using the NCF. You can turn it off in Synplify, in the implementation options. If you put a PERIOD constraint (in the UCF) on the input to the DCM, the tools (NGDBUILD specifically) will generate the constraints for the outputs; one for clk0, one for clk2x, one for clkfx. Xilinx 4.1i in particular (maybe 3.x as well) has good support for related clocks in constraints too. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 36530
Hi ZX-TEAM can be reached via me ;-) Or have a look at: http://www.zx81.de Kai, one of our members has developed ZX2000, a new "ZX81" with a lot of new features and LCD-display. A photo of the prototype can be found on my web-site, I think it's in the meetings area. Just read the complete site and you will find tons if information. A pcb for the ZX2000 is not available at the moment, because we do have lots of other projects like ZX96 links for taht on the startpage of www.zx81.de Of course you do not have to learn the german languge. Good by(t)e Peter -- http://www.zx81.deArticle: 36531
Dear All, I have to implement a Reed Solomon Encoder and a convolutional Interleaver. Could anybody send me some examples for a (208,188)or DVB standard RS coder (only the encoder) and the Interleaver. Note: The link http://www.fokus.gmd.de/research/cc/mobra/products/fec/content.html is unavailable now. Does anybody know where it is know? ThanksArticle: 36532
What do you exactly mean by saying "reconfigurable routers( IP ) using FPGA's"? By using FPGA's in your router design, you already have "reconfigurability" in your router as you can download different designs to the FPGA's as new protocols/requirments are added to IP routing. Jim do you mean "Ramnath" <ramnathgoenka@yahoo.com> wrote in message news:62cc2cff.0111102011.25090c9f@posting.google.com... > hi, > > I am in need of some ideas about reconfigrable routers( IP ) > using FPGA's. > > Can some one point the door. Although i have got some papers from > google i could not digest it. > > RamnathArticle: 36533
Hi all,
I got this counter from:
http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlexmp.html
Does this get synthesized as a ripple counter, or synchronous
counter? Is it tool/technology dependant?
If i wanted to make something using T flip-flops, do you make
a separate entity/architecture just for a T flop and use that,
or are there easier ways?
LIBRARY ieee;
USE ieee.Std_logic_1164.ALL;
USE ieee.Std_logic_unsigned.ALL;
ENTITY cntrnbit IS
GENERIC(n : Positive := 8);
PORT(clock, reset, enable : IN Std_logic;
count : OUT Std_logic_vector((n-1) DOWNTO 0));
END cntrnbit;
ARCHITECTURE v1 OF cntrnbit IS
SIGNAL count_int : Std_logic_vector((n-1) DOWNTO 0);
BEGIN
PROCESS
BEGIN
WAIT UNTIL rising_edge(clock);
IF reset = '1' THEN
count_int <= (OTHERS => '0');
ELSIF enable = '1' THEN
count_int <= count_int + 1;
ELSE
NULL;
END IF;
END PROCESS;
count <= count_int;
END v1;
Article: 36534I debounced an encoder in software by sampling it every 1 ms. If it stayed the same 3 times in a row I considered it stable. I then looked at the stable state transitions to determine the rotation. But I consider digital sampling a kludgy substitute for proper signal conditioning: I reckon the proper way is to RC low-pass filter the encoder signals then schmitt-trigger them into binary TTL levels. That way you avoid complex debouncing mechanisms, and you can use the phases as if they were the perfect square waves shown in simplified textbook explanations. K.Article: 36535
Peter Liebert-Adelt <p.liebert@t-online.de> wrote in message news:3BEE63E3.BBA6CEFB@t-online.de... > Hi > > ZX-TEAM can be reached via me ;-) > Or have a look at: http://www.zx81.de > > Kai, one of our members has developed ZX2000, a new "ZX81" with > a lot of new features and LCD-display. A photo of the prototype can be > found on my web-site, I think it's in the meetings area. There are bigger pics on Bodo's ZX97 page. Just read the > complete site > and you will find tons if information. > A pcb for the ZX2000 is not available at the moment, because we do have > lots of other projects like ZX96 links for taht on the startpage of > www.zx81.de The ZX96 in the Eurorack requires a Sinclair ULA at the heart. Which as we know is no longer made. http://www.howell1964.freeserve.co.uk/ZX81/ZX81_CPLD/ZX81_CPLD.htm shows how Bodo used a single CPLD to replace the ZX81 ULA. If someone does make a clone board of the ZX81, I'd suggest: 100 x 160 (or 220) mm Eurocard and DIN41612 expansion connector same pinout as ZX96 (goodbye RAM pack wobbles!) Modern FPGA or CPLD (Xilinx?) 32K RAM chip (goodbye RAM pack altogether!) Hi-Res graphics Integrated into the language as per http://www.howell1964.freeserve.co.uk/ZX81/G007_Technical.htm There's various other ZX81 stuff at: http://www.howell1964.freeserve.co.uk/ZX81/ZX81.htmArticle: 36536
in article 3BEE63E3.BBA6CEFB@t-online.de, Peter Liebert-Adelt at p.liebert@t-online.de wrote on 11/11/01 11:41 AM: > Of course you do not have to learn the german languge. I tried that once but I didn't get very far. Didn't stop me translating the Speccy ROM into German though. :) -AndrewArticle: 36537
I will like to know what is typically the optimal number I should select for the maximum fanout of nets (wires)? I am working on a Verilog-based PCI IP core, and FRAME#, IRDY#, and C/BE#[3:0] signals tends to get fanouted to a large number. I hear that high fanout worsens the routing performance, but I will like to know by how much. The synthesis tool I used was XST (ISE WebPack 4.1), and the default maximum fanout is 100. The target device is Spartan-II (XC2S150-5PQ208C). Kevin Brace (don't respond to me directly, respond within the newsgroup)Article: 36538
Kevin Brace wrote: > I will like to know what is typically the optimal number I should > select for the maximum fanout of nets (wires)? There is no "optimal" number. Any additional load will inevitably slow a signal down ( more in older architectures, much less in Virtex, and hardly at all in Virtex-II, thanks to generous buffering ). If that extra delay is within your timing budget: just ignore it. If it exceeds your budget, you must do something, like duplicate logic. There is no magic number. It all depends on your design... Peter AlfkeArticle: 36539
If you know apriori the direction of rotation, eg. for a motor positional
feedback, then you can catch the edge of one of the encoder signals to
set/reset a flip-flop then ignore any further transitions on that encoder
signal until the quadrature signal changes state. It give you a robust
signal conditioning without the degradading the time of arrival
information. Of course, this doesn't work if you don't know when the
encoder rotation direction changes.
kryten_droid wrote:
> I debounced an encoder in software by sampling it every 1 ms.
>
> If it stayed the same 3 times in a row I considered it stable.
>
> I then looked at the stable state transitions to determine the rotation.
>
> But I consider digital sampling a kludgy substitute for proper signal
> conditioning:
>
> I reckon the proper way is to RC low-pass filter the encoder signals
> then schmitt-trigger them into binary TTL levels.
>
> That way you avoid complex debouncing mechanisms,
> and you can use the phases as if they were the
> perfect square waves shown in simplified textbook explanations.
>
> K.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36540> ------- > function hex10 > ( hex12 : std_logic_vector(11 downto 0)) > return std_logic_vector is > begin > return hex12(9 downto 0); > end hex10; > ------- > > and use: > > slv(9 downto 0) <= hex10(X"3AC"); Hi all experts out there, I remember having a problem with the case statement when using this approach. For example, the case statement below will not compile because hex10(X"3AC") is not locally static. I think even if we make hex10 a pure function taking in constants only, we only make it globally static only, still not acceptable to the case statement. Does anybody have a solution to this? Thanks in advance. case addr is when hex10(X"3AC") => REG_3AC <= edi; when others => null; end case; Regards, kahheanArticle: 36541
Given a count value that may "chatter" between two values, the debounce issue can be effectively eliminated in software by adding a software hysteresis; no signal conditioning required as long as the encoding scheme is stable. If the software lags for an increase but responds to a decrease right away, the system is stable: When the raw count reports 0-1-2-3-2-3-2-3-4-3-2-3-2-1-0 4 _ 3 _ _ _/ \_ _ 2 _/ \_/ \_/ \_/ \_ 1 _/ \_ 0 _/ \_ the software can see through the chatter by responding with 0-0-1-2-2-2-2-2-3-3-2-2-2-1-0 3 ___ 2 _________/ \_____ 1 _/ \_ 0 ___/ \_ As with any hysteresis there's a little "backlash" but the count is rock solid. No level of software signal conditioning got rid of chatter in one system I worked on until the software hysteresis was applied. Beautiful results. kryten_droid wrote: > > I debounced an encoder in software by sampling it every 1 ms. > > If it stayed the same 3 times in a row I considered it stable. > > I then looked at the stable state transitions to determine the rotation. > > But I consider digital sampling a kludgy substitute for proper signal > conditioning: > > I reckon the proper way is to RC low-pass filter the encoder signals > then schmitt-trigger them into binary TTL levels. > > That way you avoid complex debouncing mechanisms, > and you can use the phases as if they were the > perfect square waves shown in simplified textbook explanations. > > K.Article: 36542
John Handwork wrote: > > Given a count value that may "chatter" between two values, the debounce > issue can be effectively eliminated in software by adding a software > hysteresis; no signal conditioning required as long as the encoding > scheme is stable. If the software lags for an increase but responds to > a decrease right away, the system is stable: > > When the raw count reports > > 0-1-2-3-2-3-2-3-4-3-2-3-2-1-0 > 4 _ > 3 _ _ _/ \_ _ > 2 _/ \_/ \_/ \_/ \_ > 1 _/ \_ > 0 _/ \_ > > the software can see through the chatter by responding with > > 0-0-1-2-2-2-2-2-3-3-2-2-2-1-0 > 3 ___ > 2 _________/ \_____ > 1 _/ \_ > 0 ___/ \_ > > As with any hysteresis there's a little "backlash" but the count is rock > solid. No level of software signal conditioning got rid of chatter in > one system I worked on until the software hysteresis was applied. > Beautiful results. Interesting idea, and it can be applied right at the Quad State engine, if desired. -jgArticle: 36543
Good Morning,
actually I'm finding with your help to speed up these counters and
enhance them, expecially the following counter divider 3 that on
XCV1000 bg 560 -4 seems to work only at a maximum of 160 MHz while I
need at least 165MHz but I prefer something more 'cause the project
include many others circuit. Here it is, it is revised from an idea of
Ray, it is changed in a way to have the zero of the counter
corrisponding to the falling edge of the clocks.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter_divider_3 is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
count_3 : out STD_LOGIC_VECTOR (2 downto 0);
clk_div_3 : out STD_LOGIC
);
end counter_divider_3;
architecture counter_divider_3_arch of counter_divider_3 is
signal int_count_3 : STD_LOGIC_VECTOR (1 downto 0) ;
signal reset_clk_a_b : STD_LOGIC_VECTOR (3 downto 0) ;
signal count_0_delayed : STD_LOGIC;
begin
process (clk)
begin
if reset='1' then
int_count_3 <= "01";
elsif rising_edge(clk) then
-- & funziona come aggregatore di bit non un and logico !!
int_count_3 <= int_count_3(0) & not(int_count_3(0) or
int_count_3(1));
end if;
end process;
process(clk)
begin
if falling_edge(clk) then
count_0_delayed <= int_count_3(0);
end if;
end process;
clk_div_3 <= int_count_3(0) nor count_0_delayed;
with int_count_3 select
count_3 <= "010" when "00" ,
"001" when "10" ,
"000" when "01" ,
"XXX" when others;
end counter_divider_3_arch;
and these are the others counters, have you some idea to enhance them
again ??
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter_divider_4 is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
count_4 : out STD_LOGIC_VECTOR (2 downto 0);
clk_div_4 : out STD_LOGIC
);
end counter_divider_4;
architecture counter_divider_4_arch of counter_divider_4 is
signal int_count_4 : STD_LOGIC_VECTOR (1 downto 0) ;
begin
process (clk)
begin
if reset='1' then
int_count_4 <= "00";
else
if falling_edge(clk) then
int_count_4 <= int_count_4 + 1 ;
end if;
end if;
end process;
count_4(1 downto 0) <= int_count_4 ;
count_4(2) <= '0' ;
clk_div_4 <= int_count_4(1);
end counter_divider_4_arch;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter_divider_6 is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
count_6 : out STD_LOGIC_VECTOR (2 downto 0);
clk_div_6 : out STD_LOGIC
);
end counter_divider_6;
architecture counter_divider_6_arch of counter_divider_6 is
begin
process (clk, reset)
variable count_6_interno : STD_LOGIC_VECTOR (2 downto 0);
begin
if reset='1' then
count_6_interno := "000";
else
if falling_edge(clk) then
if count_6_interno < 5 then
count_6_interno := count_6_interno + 1;
if count_6_interno = 3 then
clk_div_6 <= '1' ;
else null;
end if ;
else
count_6_interno := "000";
clk_div_6 <= '0' ;
end if;
end if;
end if;
count_6 <= count_6_interno;
end process;
end counter_divider_6_arch;
Thanks for your help !!
Article: 36544We always design a monitor bus to wich variouse important signals can be switched to outsideArticle: 36545
Falk, > > During a timing simulation with Foundation Timing Simulator I get the > > following messages: > > > > "undetermined input pin state" > > This should be clear. Some of your input signals are not defined in the > simulation. E.G. if the data input of a FF isnt defined and a clock impulse > arrives, what should we see at the output?? > Go and assign a valid value. This isn't that clear, because every (external) input signal has a defined stimulus! MichaelArticle: 36546
Dear all, My circuit need various frequency clock. Is it common to built Clock Multiplier ? I think it is easier to built clock divider rather than clock multiplier. For examples, My circuit need clock source 60 MHZ and 80 MHz, Therefore If I have one 120 MHz clock source, I just need to built 1/3 clock divider and 1/2 clock divider. But another way is by using 20 MHz clock source then I built 3x clock multiplier and 4x clock multiplier. I really appreciate for your advices/suggestion. Thanks BuzzArticle: 36547
In article <3BEF751B.5B2B@designtools.co.nz>, Jim Granville <jim.granvil
le@designtools.co.nz> writes
>John Handwork wrote:
>>
>> Given a count value that may "chatter" between two values, the debounce
>> issue can be effectively eliminated in software by adding a software
>> hysteresis; no signal conditioning required as long as the encoding
>> scheme is stable. If the software lags for an increase but responds to
>> a decrease right away, the system is stable:
>
[snip details]
>> As with any hysteresis there's a little "backlash" but the count is rock
>> solid. No level of software signal conditioning got rid of chatter in
>> one system I worked on until the software hysteresis was applied.
>> Beautiful results.
>
>Interesting idea, and it can be applied right at the Quad State engine,
>if desired.
Yes, but does it ever mess up your servo loops! I guess it's ideal
for processing the output from a possibly poor-quality panel
mounted encoder, but hysteresis on a sensor is a disaster in any
position control system. Let the sensor deliver raw values to the
best of its ability, and do application-specific processing
like hysteresis somewhere else.
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
**********************************
** Developing design know-how **
**********************************
This e-mail and any attachments are confidential and Doulos Ltd. reserves
all rights of privilege in respect thereof. It is intended for the use of
the addressee only. If you are not the intended recipient please delete it
from your system, any use, disclosure, or copying of this document is
unauthorised. The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 36548"Philippe Robert" <PhilippeR@sundance.com> writes: > Hi there, > > I found an application note on the Xilinx website (xapp158) about decoupling > capacitors. It is explained that high frequency and mid-frequency capacitors > are required. > > For the high frequency capacitor, I will use 100nF. It says in that app to > fit 1 100nF cap per Vcc. (I have counted as Vcc pins Vccio, Vccaux and > Vccint pins). I end up with 64 cpas for a XC2V1000-FG456 !! > Can someone tell me of my calculation is right ? > > For mid-frequency caps, I will use 10uF tant, but the app note does not say > how many of them to fit. > Does anyone know ? > For some good discussion on *designing* your power distribution system, which becomes essential when the rules of thumb wear out, see this page, especially the top two papers... sorry it's a long link! http://groups.yahoo.com/group/si-list/files/Signal%20Integrity%20Documents/Published%20SI%20Papers%20from%20Sun/ Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 36549
In article <3BEE8C3D.CF9EBE7D@iprimus.com.au>, Russell Shaw
<rjshaw@iprimus.com.au> writes
>Hi all,
>
>I got this counter from:
> http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlexmp.html
>
>Does this get synthesized as a ripple counter, or synchronous
>counter? Is it tool/technology dependant?
>
>If i wanted to make something using T flip-flops, do you make
>a separate entity/architecture just for a T flop and use that,
>or are there easier ways?
>
>
>LIBRARY ieee;
> USE ieee.Std_logic_1164.ALL;
> USE ieee.Std_logic_unsigned.ALL;
> ENTITY cntrnbit IS
> GENERIC(n : Positive := 8);
> PORT(clock, reset, enable : IN Std_logic;
> count : OUT Std_logic_vector((n-1) DOWNTO 0));
> END cntrnbit;
>
> ARCHITECTURE v1 OF cntrnbit IS
> SIGNAL count_int : Std_logic_vector((n-1) DOWNTO 0);
> BEGIN
>
> PROCESS
> BEGIN
> WAIT UNTIL rising_edge(clock);
> IF reset = '1' THEN
> count_int <= (OTHERS => '0');
> ELSIF enable = '1' THEN
> count_int <= count_int + 1;
> ELSE
> NULL;
> END IF;
> END PROCESS;
> count <= count_int;
> END v1;
It is a synchronous ripple counter with a synchronous reset and a
synchronous enable.
It should synthesise fine, though most people in this group would use
numeric_std for arithmetic rather than std_logic_unsigned. Also you
shouldn't really need the null; branch in the if, as you know that you
are synthesising flip-flops and they have memory.
Therefore, I would write
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cntrnbit is
generic(n : positive := 8);
port (Clock : in std_logic;
Reset : in std_logic;
Enable : in std_logic;
count : out std_logic_vector( n-1 downto 0) );
end cntrnbit;
architecture v1 of cntrnbit is
signal count_int : unsigned(n-1 downto 0);
begin
process
begin
wait until rising_edge(clock);
if reset = '1' then
count_int <= (others => '0');
elsif enable = '1' then
count_int <= count_int + 1;
end if;
end process;
count <= std_logic_vector(count_int);
end;
On your second question, is it tool/technology independent, the answer
is maybe! It should be OK with most tools, except Altera Max+PLUS II
doesn't support numeric_std, so your original code would be better than
mine (!).
Secondly, not all FPGAs support synchronous resets built in to the logic
blocks, so you may find you use extra resources to implement gating to
support the synchronous resets.
kind regards
Alan
--
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: alan.fitch@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
**********************************
** Developing design know-how **
**********************************
This e-mail and any attachments are confidential and Doulos Ltd. reserves
all rights of privilege in respect thereof. It is intended for the use of
the addressee only. If you are not the intended recipient please delete it
from your system, any use, disclosure, or copying of this document is
unauthorised. The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z