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Hi, Russell Shaw wrote: > Hi all, > > Are there any good books that have (vhdl) fifo designs and > discussion on asynchronous clock domains etc? > this is not a book but might help as well: http://img.cmpnet.com/deepchip/downloads/cliffsnug01.pdf -- EdwinArticle: 36351
Remove the "if rising_edge(clk) then " so that count_out is a combinatorial output of count_in instead of a registered version of the encoding result. Jim "Banana" <cappellainfuocata@yahoo.it> wrote in message news:d23ae64d.0111070117.6ab85610@posting.google.com... > With this encoder if i set an input count_in , I've the right output > named count_out only on the next edge of the clock, this is no good > for my project, why this happen and how I can modify this encoder to > have the rigth output directly on the same clock edge ??? > Thanks > > Banana > > > library ieee ; > use ieee.std_logic_1164.all ; > > entity encoder is > port ( > count_in : in std_logic_vector(2 downto 0) ; > reset : in std_logic ; > clk : in std_logic ; > count_out : out std_logic_vector(2 downto 0) > ) ; > end encoder ; > > architecture encoder_arch of encoder is > begin > process(clk, reset , count_in) > begin > if ( reset = '1') then > count_out <= "XXX"; > elsif rising_edge(clk) then > case count_in is > when "001" => count_out <= "000"; > when "010" => count_out <= "001"; > when "100" => count_out <= "010"; > when others => NULL; > end case; > end if; > end process; > end encoder_arch ;Article: 36352
> > this is not a book but might help as well: > Nor is this, but it might help: Xilinx Application Note XAPP175 "High Speed FIFOs In SPartan-II FPHAs"Article: 36353
Hi Folks, I am working on a couple of projects using a Xilinx XSV-100 chip, in an XESS evaluation board. They both involve a simple microcontroller (KCPSM), using a BlockRAM as its program ROM. As the designs progress, I am often modifying the KCPSM program code, but not the FPGA design. So far I have only been able to include the modified code into the configuration bitstream by reruning the 'implementation' stage in ther design software (Xilinx Foundation F3.1i), a rather length and unnecessary process. My question is: Is it possible to manually rerun just one subset of the implementation processes to reprogram the RAMs initial values, or is there a utility to modifiy the RAM contents stored in a .bit bitstream file? Cheers, Christopher Saunter ps, Ken, if you're reading this, thanks for the KCPSM, it's saved me a lot of work!Article: 36354
Assaf Sarfati <assaf_sarfati@yahoo.com> wrote: > As far as I could see, Synplicity simply ignored syn_noclockbuf in the > HDL code, since it know better than me what was and what wasn't a clock... It does work, but you usually have to put it inside your entity section; inside the architecture doesn't work. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 36355
Even if this question is quiet general, I got this problem with FPGA : With VirtexII BGA package, where place the decoupling capacitor ? In Virtex-E family, there was a square free at the center of the chip but now, ball are everywhere. Because you need a via to connect power and ground, and because the space between them is 1.27 mm, where to place capacitor ??? Does anybody has experienced this problem ? Thanks in advanceArticle: 36356
In article <9sbh84$7im$1@mail.cn99.com>, duola <deerlux@hotmail.com>
writes
>I want implement such a counter in verilog.
>input clk,en;
>output [4:0]out;
>"en" is low enable and the negative edge of "clk" is used.When the negative
>edge of "en" arrive,"out" must be reset to 0.When the negative edge of "clk"
>arrived,the counter begin counting.When "en" is high level, "clk" is high
>level too.There is not any high frequency clock to use.How should I do?
What would you do in hardware?
I can easily write Verilog that will simulate in this way, but I
don't know how to create hardware that will do it.
If you change the meaning of "en" so that it is an active-high
reset, it's easy. But if you need to hold the count when "en"
is high, ?????
--
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Article: 36357"Scott L. Burris" <scott@slb.org> wrote in message news:MPG.16526619e00d088e989680@news.earthlink.net... > Hi, > > Does anyone have any good suppliers for FPGAs in very small > quantities, like 1 or 2? I'm particularly interested in > the Xilinx Spartan chips. I just tinker with this stuff > as a hobby, so I'm not looking to buy zillions of parts. > I've previously been able to get older parts, like the XC52XX. > But newer chips seem to be a problem. In the UK, Insight-Memec don't mind supplying small quantities of Xilinx parts on a cheque with order basis. Leon -- Leon Heller, G1HSM leon_heller@hotmail.con http://www.geocities.com/leon_heller Low-cost Altera Flex design kit: http://www.leonheller.comArticle: 36358
Although I have to admit that this reply doesn't really solve your problem, about a week ago, I posted a newsgroup posting with a title of "LeonardoSpectrum-Altera stability". You can use Google Groups to search for that. In that posting, I said that LeonardoSpectrum-Altera (a free version available from Altera) crashes when I passed a parameter defined by defparam through two modules which synthesized fine with XST Verilog (ISE WebPack 4.1) and compiled fine with ModelSim 5.5b XE-Starter (also came with ISE WebPack 4.1). Also, during synthesis with LeonardoSpectrum-Altera, when I pressed stop button to stop the synthesis, about 30 to 50% of the time, LeonardoSpectrum-Altera crashes. In my opinion, LeonardoSpectrum-Altera is the worst EDA tool I have ever used (worst than even Cypress' tools I used to use). Although I don't mean to make fun of anyone, I just cannot believe people spend thousands of dollars to buy such a buggy tool. Regards, Kevin Brace (don't respond to me directly, respond within the newsgroup) "Su We" <sweather1999@yahoo.com> wrote in message news:<Cy4G7.65$284.129176@news1.sttln1.wa.home.com>... > We are designing with mentor's HDL author and want to know if there is and > easy way to convert/copy the HDL files generated by HDL author and > synthesize them in Xilinx's project navigator? > > Basically, we are getting errors with leonardo when synthesizing code that > synthesizes fine in xilinx tools. > > thanks > > SWArticle: 36359
Hello, I was wondering if someone had been playing with the new XPoxer tool. As far as I understood form the documentation, getting precise power estimations requires the design beeing simulated to produce a VCD report file (for toggle rates). I have two question regarding this : 1) I guess that one has to simulate the VHDL model of the annotated placed & routed design; and trace all primitives activity for a while to get a good idea of the circuit behavior, however, for large design, this is likely to be VERY time consuming, if not impossible due to the tool stability or PC memory limits. Can someone give his opinion about this ? 2) Xilinx support says one has to use Modelsim to guarantee proper work of the tool Alas, we only have Synopsys VHDL simulator, which can also produce VCD report file, but which is not 'officilially' supported by the tool. Has anybody experienced Xpower/VSS compatibilty problems ? Thanks, Steven PS: Xilinx rep. are welcome to answer these questions :))Article: 36360
Thanks Ray for your long answer! I couldn't make it anyway. I had always
one level of logic too much. What I was trying to was to give out two
bits of an original value from IOBs and in three following cycles this
value incremented by one for each cycle. Now I rewrote the whole thing:
generateLower2AddressBitTop: process(clock,addressFromPadTop,reset)
VARIABLE burstAddressTop: unsigned(1 downto 0);
begin
if (reset = '1') then
burstAddressTop := b"00";
addressTop(1 downto 0) <= std_logic_vector(burstAddressTop(1 downto
0));
elsif (rising_edge(clock)) then
if (startBurstTop_1 = '1') then
burstAddressTop := burstAddressTop + 1;
else
burstAddressTop(1 downto 0) := unsigned(addressFromPadTop(1 downto
0));
end if;
addressTop(1 downto 0) <= std_logic_vector(burstAddressTop(1 downto
0));
end if;
end process;
LUTburstStartTop : LUT3 port map (
I0 => casNegFromPadTop,
I1 => rasNegFromPadTop,
I2 => csNegFromPadTop,
O => startBurstTop_LUT
);
burstStartRegTop: FDCE port map (
D => startBurstTop_LUT,
Q => startBurstTop_0,
c => clock,
ce => ONE,
clr => reset
);
burstDelay3Top: delay3 port map (
set => startBurstTop_0,
clock => clock,
output => startBurstTop_1
);
The process has no statemachine anymore and sees startBurstTop_1 = '0'
in cycle0, thus giving out the default value. During cycle0,
statrBurstTop_1 will turn '1' and be like that for three cycles. "delay3"
consists
of three FF in serial, the first has always '0' as input, but the "set" input
of the component is attached to all three async. PRESER inputs of the FFs.
In the next three cycles the process sees startBurstTop_1 = '1' and output
the
incremented value. I could place the time critical parts by hand and apply
timing constraints to the signal.
Works as well, but not exactly what I had in mind priviously. Thanks for
your help
anyway!
Wfr,
-jc-
> The logic (the if statement) has to be encoded into the INIT attribute of
> the LUT, and then the process reduces to just the flip-flop. If you
> instantiate the LUT and the Flip-flop the placement constraints can be put
> on them right in the VHDL as RLOCs. Encoding the LUT is awkward, as you
> might have guessed, especially if you are starting out with a text
> construct like the if-then-else.
>
> If you can keep the combinatorial logic to a single layer, then the mapper
> will place that logic with the flip-flop, and you avoid having to place
> the LUTs. If the LUT drives the reset or set of and FDR or FDS, or drives
> the clock enable, or drives another LUT, then you'll end up with a LUT
> that doesn't place with the flip-flop. Unfortunately the placer seems to
> do an exceptionally poor job at placing second level LUTs like that.
>
> If you are using synplicity, you can put your lut logic inside a separate
> component and put the xc_map attribute on it. That permits you to place
> the LUT as well. In that case, you can put the if-then-else logic inside
> the separate component.
>
> I try to avoid having to place the LUTs since it is awkward and gives
> fairly hard to read code. It is often necessary however.
>
> Jens-Christian Lache wrote:
>
> > Dear newsgroup!
> >
> > I have a question concerning a placement constraint.
> > If I have the following process:
> >
> > myProc: process(clock,reset)
> > type statemachineType (one,two);
> > variable statemachine statemachineType;
> > begin
> > if (reset = '1') then
> > statemachine := one;
> > something <= '0';
> > elsif (rising_edge(clock)) then
> > case statemachine is
> > when one =>
> > something <= '0';
> > if (signal1 = '1' and signal2 = '0' and signal3 = '1')
> > then
> > statemachine := two;
> > end if;
> > when two =>
> > something <= '1';
> > when others => null;
> > end case;
> > end if;
> > end process;
> >
> > the if statement will result in a LUT4. I can set placement
> > constraints for the statemachine variable FFs, but how can I fixate
> > the location of the lookup table?
> >
> > I tried to handwire a LUT outside of the process like
> >
> > myLUT: LUT3 port map (
> > I0 => signal1,
> > I1 => signal2,
> > I3 => signal3,
> > O => switchState);
> >
> > and then in the process:
> >
> > if (switchState = '1') then
> > statemachine := two;
> > end if;
> >
> > This allows to place the LUT, but introduces a new logic stage and
> > is therefor useless.
> >
> > Any ideas?
> >
> > Thanks,
> >
> > -jc-
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
> "They that give up essential liberty to obtain a little
> temporary safety deserve neither liberty nor safety."
> -Benjamin Franklin, 1759
Article: 36361RS wrote: > > Even if this question is quiet general, I got this problem with FPGA : > With VirtexII BGA package, where place the decoupling capacitor ? > In Virtex-E family, there was a square free at the center of the chip > but now, ball are everywhere. Because you need a via to connect power > and ground, and because the space between them is 1.27 mm, where to > place capacitor ??? On the back side of the board. Make an GND rectangle on the bottom layer. Make a rectangular VCC ring enclosing it. Surface mount capacitors straddle the gap. --Mike TreselerArticle: 36362
Hi! Well, you have to use a multilayer board (if not already done so) and then you can place the capacitors at the bottom layer (opposite of your bga-device). The vias will connect the necessary balls to the opposite of your pcb, and that's it! Of course, you have to use small vias (like 8mil hole and 24mil size or smaller if you like). There exists an application note from Altera (don't know what about Xilinx, but probably there is something similar): http://www.altera.com/literature/an/an114.pdf Rafael RS schrieb: > Even if this question is quiet general, I got this problem with FPGA : > With VirtexII BGA package, where place the decoupling capacitor ? > In Virtex-E family, there was a square free at the center of the chip > but now, ball are everywhere. Because you need a via to connect power > and ground, and because the space between them is 1.27 mm, where to > place capacitor ??? > Does anybody has experienced this problem ? > Thanks in advanceArticle: 36363
In article <3BE98461.B711D28A@flukenetworks.com>, mike.treseler@flukenetworks.com says... > RS wrote: > > > > Even if this question is quiet general, I got this problem with FPGA : > > With VirtexII BGA package, where place the decoupling capacitor ? > > In Virtex-E family, there was a square free at the center of the chip > > but now, ball are everywhere. Because you need a via to connect power > > and ground, and because the space between them is 1.27 mm, where to > > place capacitor ??? > > On the back side of the board. > Make an GND rectangle on the bottom layer. > Make a rectangular VCC ring enclosing it. > Surface mount capacitors straddle the gap. Ok, a couple more questions about this. - How to connect these rings to the VCC/Gnd planes? I'd assume there would have to be a *lot* of vias to the appropriate planes. - What about multiple I/O technologies? The Virtex-E (FG680) design I did used four I/O voltages. Partial "rings" opposite the banks? hat still leaes two rings for VIO and Vcore. - Do the tools used to place the capacitors like the rings? I thought they wanted islands such that the surface tension of the melted solder automagically positioned the caps. - This strategy would seem to eliminate one I/O plane since the decoupling ring isolates the I/O. Is there another trick here? I'd hate to make the back a ground plane. It makes ECs harder. ;-) It still seems the caps are a good distance from the center pins. The center of the FG680 package made a very good place to pack with caps (and terminators). ---- KeithArticle: 36364
I actually bought a few XC2V3000BF957 chips recently. These are still engineering samples (ES) but seem to work OK, with a few caveats. Try to look at a differnt distributor. Andreas rickman wrote: > I am taking a serious look at using the Virtex II chips in a design that > will be going to prototype in Feb, '02. The size I will need is less > than the XC2V1000, but more than the XC2V40. That leaves the '80, '250 > and '500 sized parts. But I can find no information on when they will be > available or target pricing. The '40 lists (web pricing) at about > $35-$40 and the '1000 shows up at $250-$300. > > I am not sure if the XC2V80 will be big enough and it looks like the > XC2V250 might be too expensive (>$100) for this application. Anyone have > the skinny on when Xilinx will be introducing these parts? Is Xilinx > planning to bring down the cost of the XC2V devices any time soon? > Certainly at the small end they are very pricey compared to Spartan II > or other brands of FPGAs. I can get an XC2S150 with 3500 LCs for the > price of an XC2V40 with only 512! Certainly the cost of the extra > features in the XC2V family is not THAT high?! > > >Article: 36365
A few corrections : Altera FPGA's can be EEPROM or SRAM based depending on the density. I wouldn't learn Verilog nor VHDL to start with but use the graphic editors provided. They allow rather complex stuff and are self-documenting. Rene Kevin Brace wrote: > > Xilinx and Altera FPGAs are based on SRAM, so a Configuration PROM > (EEPROM based) has to be attached to program the FPGA when the power > is turned on. > To design circuits for an FPGA, you should learn languages like > Verilog or VHDL. > I will recommend learning Verilog, but I am sure some people will say > VHDL.Article: 36366
Christopher.Saunter@durham.ac.uk (Christopher Saunter) writes: > I am working on a couple of projects using a Xilinx > XSV-100 chip, in an XESS evaluation board. That would be XCV100 chip in XSV-100 board. :-) > As the designs progress, I am often modifying the KCPSM > program code, but not the FPGA design. So far I have > > Is it possible to manually rerun just one subset of > the implementation processes to reprogram the RAMs initial > values, or is there a utility to modifiy the RAM contents > stored in a .bit bitstream file? Try either Xilinxes JBits tool (Java program controlled .bit file editing) or read up on where the BRAM bits are in the bitstream in Xilinx Application Note XAPP151. JBits can be got per EMail to jbits@xilinx.com XAPP151 is at: http://www.xilinx.com/xapp/xapp151.pdf Info how bitstream is stored in .bit is at: http://neil.franklin.ch/Usenet/comp.arch.fpga/20010828_download_bitstream_to_FPGA -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual RobberyArticle: 36367
"Keith R. Williams" wrote: > > On the back side of the board. > > Make an GND rectangle on the bottom layer. > > Make a rectangular VCC ring enclosing it. > > Surface mount capacitors straddle the gap. > > Ok, a couple more questions about this. > > - How to connect these rings to the VCC/Gnd planes? I'd assume there > would have to be a *lot* of vias to the appropriate planes. One via per ball on the perimeter. > - What about multiple I/O technologies? The Virtex-E (FG680) design I > did used four I/O voltages. Partial "rings" opposite the banks? that > still leaes two rings for VIO and Vcore. Sound reasonable to me. > - Do the tools used to place the capacitors like the rings? I thought > they wanted islands such that the surface tension of the melted solder > automagically positioned the caps. You lay the caps parallel in the gap, not on the ring. > - This strategy would seem to eliminate one I/O plane since the > decoupling ring isolates the I/O. Is there another trick here? I'd > hate to make the back a ground plane. It makes ECs harder. ;-) You need 10 layers to handle the IOs on a big BGA. Yes, the real planes are internal layers. > It still seems the caps are a good distance from the center pins. The > center of the FG680 package made a very good place to pack with caps > (and terminators). I expect that the GND and power planes make the exact cap position much less critical than in the two-layer TTL days. --Mike TreselerArticle: 36368
Rob Finch wrote: > Are there any fpga's containing high capacity dram's on chip ? There seem to > be quite a few people interfacing to external drams. I see three good reasons why FPGA manufacturers do not incorporate DRAMs on their chips: Commercial: DRAMs are incredibly cheap, so the user inevitably would compare an on-chip megabyte with the $ 0.20 being paid per external megabyte. Well, some users are more enlightened than that, but the idea will still be in the back of their heads. Technical: DRAMs require different processing steps ( trench capacitors, etc ), which would increase the cost of the composite die. Logistical: What's the right amount ? Inevitably there would be too little for some, and too much for others. And both parties would complain. And everybody would have to pay for it... We have introduced many non-homogeneous features that are (almost) universally appreciated: Carry, LUT-RAM, BlockRAM, multipliers, digital clock management, digitally-controlled output impedance, etc. Very soon, we will have 3 Gbps serial data I/O and 300 MHz PowerPC. These things are process-compatible with the FPGA "fabric", and thus do not cause major manufacturing problems and unreasonable additional cost. And they also are very valuable to, and appreciated by, many interested users. And Virtex-II will stay around if you don't care for gigabits and PowerPCs... Peter AlfkeArticle: 36369
I'm working on a program to aid me in the tedious allocation of pins for a Virtex-II device. But I need to obtain package information, presumably in machine readable form. I can use partgen to generate a plain ASCII file, but this does not contain any information regarding the bank number for each pin. Is there an ASCII (or documented binary file) file where I can find this information? I guess this information is located in the nph file, but I don't have any documentation for its format. TIA Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 36370
I am waiting for Burched (in Australia) to launch their next FPGA development board http://www.burched.com.au/ It is going to be 100 x 130 mm with connectors on a standard 0.1 inch grid so it can mate with sockets mounted on a standard prototyping board. And mount in Eurocard type cases/racks. 200K gate Xilinx Spartan-II device. I had a little input in this so I'm hoping it will be good.Article: 36371
Petter Gustad wrote: > > I'm working on a program to aid me in the tedious allocation of pins > for a Virtex-II device. But I need to obtain package information, > presumably in machine readable form. bsdl files include the pin names and designations. check out: http://support.xilinx.com/support/sw_bsdl.htm --Mike TreselerArticle: 36372
The user interface sure is buggy. IMO, its typical of software originating from development on unix systems. If your code isn't really huge, maybe i could try a compilation... Kevin Brace wrote: > > Although I have to admit that this reply doesn't really solve your > problem, about a week ago, I posted a newsgroup posting with a title > of "LeonardoSpectrum-Altera stability". > You can use Google Groups to search for that. > In that posting, I said that LeonardoSpectrum-Altera (a free version > available from Altera) crashes when I passed a parameter defined by > defparam through two modules which synthesized fine with XST Verilog > (ISE WebPack 4.1) and compiled fine with ModelSim 5.5b XE-Starter > (also came with ISE WebPack 4.1). > Also, during synthesis with LeonardoSpectrum-Altera, when I pressed > stop button to stop the synthesis, about 30 to 50% of the time, > LeonardoSpectrum-Altera crashes. > In my opinion, LeonardoSpectrum-Altera is the worst EDA tool I have > ever used (worst than even Cypress' tools I used to use). > Although I don't mean to make fun of anyone, I just cannot believe > people spend thousands of dollars to buy such a buggy tool. > > Regards, > > Kevin Brace (don't respond to me directly, respond within the > newsgroup) > > "Su We" <sweather1999@yahoo.com> wrote in message news:<Cy4G7.65$284.129176@news1.sttln1.wa.home.com>... > > We are designing with mentor's HDL author and want to know if there is and > > easy way to convert/copy the HDL files generated by HDL author and > > synthesize them in Xilinx's project navigator? > > > > Basically, we are getting errors with leonardo when synthesizing code that > > synthesizes fine in xilinx tools. > > > > thanks > > > > SW -- ___ ___ / /\ / /\ / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ /__/ / Victoria, Australia, Down-Under /__/\/\/ \ \ / \ \/\/ \__\/ \__\/Article: 36373
Neil Franklin wrote: > Christopher.Saunter@durham.ac.uk (Christopher Saunter) writes: > > > I am working on a couple of projects using a Xilinx > > XSV-100 chip, in an XESS evaluation board. > > That would be XCV100 chip in XSV-100 board. :-) > > > As the designs progress, I am often modifying the KCPSM > > program code, but not the FPGA design. So far I have > > > > Is it possible to manually rerun just one subset of > > the implementation processes to reprogram the RAMs initial > > values, or is there a utility to modifiy the RAM contents > > stored in a .bit bitstream file? > > Try either Xilinxes JBits tool (Java program controlled .bit file > editing) or read up on where the BRAM bits are in the bitstream in > Xilinx Application Note XAPP151. > > JBits can be got per EMail to jbits@xilinx.com > > There is a 3rd alternative. Convert the routed .ncd database to ASCII text using the xdl program, edit the INIT lines, convert back to .ncd again via xdl. I believe this gains you a design rule check stage that JBits doesn't have.Article: 36374
Petter Gustad wrote: > I'm working on a program to aid me in the tedious allocation of pins > for a Virtex-II device. But I need to obtain package information, > presumably in machine readable form. I can use partgen to generate a > plain ASCII file, but this does not contain any information regarding > the bank number for each pin. Is there an ASCII (or documented binary > file) file where I can find this information? > > I guess this information is located in the nph file, but I don't have > any documentation for its format. > > TIA > > Petter > -- > ________________________________________________________________________ > Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.com A trick I use, given that the idea of publishing simple ASCII text pinout/function files has escaped the attention of the chip industry since its inception, is to fake a design that uses every pin of the device (incl. clocks). Then a perl script can extract all the info you need from the post P&R .pad and .par files. The only non-simple thing you need to do is make sure there's at least one non-LVTTL IO standard so that the .par file has the banking info. Its a hassle to set up for the first device but easy for all subsequent ones you might want to use. Together with the advantage that the occasional pinout error in the published tables won't catch you out.
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