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Hi
Some tools (Cadence e.g.) support mixed languages design. They count on the
(unique) names of the modules/entities.
A safer method is to make a shell around the verilog: make an entity with
foreign verilog body. When doing so, you can add that shell in a structure.
This way you don't count on the names. Be aware only std_(u)logic and
std_(u)logic_vectors are supported. For simulation, also integers are
supported. (for synth this in not *always* true => generics in vhdl entities
will cause troubles).
It is possible you need to add some lines to the verilog/initialisation
script to simulate the verilog. e.g. libraries with verilog cells, time
correlation with vhdl
example of foreign body:
================================
arictecture netlist of [name topmodule] is
attribute foreign of netlist:architecture is
"verilog: [name topmodule] [path of netlist relative to starting point
of simulation or abs path/[filename of netlist.v]"
begin
end netlist;
================================
instead of type "verilog: [name of topmodule] [path of netlist relative to
starting point of simulation or abs path]/[filename of netlist.v ]"
you can also type refer to a library instead of giving the path of the
verilog file.
Kind regards
J.
--
----------------------------------------------------------------
Johan Van Dyck
VLSI Design Engineer &
Design Technology Office
Philips Leuven (Belgium)
Johan.Van.Dyck@philips.com
----------------------------------------------------------------
"Andrew Gray" <andrew@tuks.co.za> schreef in bericht
news:999585905.440006@nntp.up.ac.za...
> Hi
>
> I downloaded a floating point arithmetic core from opencores.org. The core
> is written in verilog. I have never used verilog before, how can I
implement
> it into a VHDL design. Do I incorporate it as a component and then use
port
> mapping as in VHDL?
>
> Does anyone have any examples on how to do this?
>
> Thanks
>
> Andrew :-)
>
>
Article: 34701
Nisreen,
Unfortunately, there are differences in the way the databook and trce/timing analyzer report values and the way the simulation models report them. This does not
necessarily mean the simulation netlist is incorrect. In many ways, the simulation netlist is more accurate as it takes a much more physical look at the data paths
than the databook or trce does. For instance, the registers in the IOBs are not physically too much more different than the ones in the CLB array so the setup windows
should be similar and certalinly not as large as 1.3 nS however it is all perspective. The databook reports the setup number lumping the pad and input buffer paths
into the number and zeroing out negative hold times therefore giving a much larger setup window than really exists in the silicon. The simulation model on the other
hand does not lump those delays together as one large setup value and instead distributes it to the proper components (namely then input X_BUF) for your case. I
suspect, if you add the value of the components in the data path to that setup value, you should get your 1.3 ns value.
In an attempt to better match these databook values to simulation a new component was created and was started to be added to the netlist in 3.1i however should be
more prevelent in 4.1i (the release coming out now). This new component is called X_SUH standing for SetUp and Hold. This component is added parallel to the input
paths and should contain the same value reported in the "databook" section of the trce report. It will have a much wider window for setup, similar to the databook,
however will not make us alter the values of the datapath (such as zeroing out buffer delays) which can have a very neagative impact on simulation for some cases.
This should give you the expected setup violations during simulation but still give proper datapath structuring.
What I can tell you is that most likely the netlist is accurate even though the numbers might not match up exactly as you would expect. The simulations models are
sometimes constructed in a way that best represents real-life in a simulator and that may not look exactly as it is reported in the databook. If you do still question
the accuracy of the model, please open a case with our hotline and they can better investigate this for you. I will be on vacation for the next few weeks
(technically, I am on vacation now but thought you deserve an answer) so please have the hotline look into this for you since I will not be around to help you out. I
know this can be cionfusing (it is for me many times as well) but I am seeing what we can do for the future to make this less confusing without sacrificing accuracy of
the simulation models.
Hopefully this response helps you out a bit.
-- Brian
Nisreen Taiyeby wrote:
> I am working with virtexE speed grade 8, xilinx alliance series with service pack 8.
>
> When I generate the sdf file for timing simulation, the setup times for flops placed in the IOB is given as 271 ps which happens to be the setup for CLB flops too.
>
> But the latest datasheets on VietexE device gives the IOB setup of 1.3 ns.
>
> That means that my timing simulation is faulty.
>
> Can anyone out there help me.
>
> Regards,
> Nisreen.
Article: 34702I think one of the ways that you can avoid which sythesys tool you use would be to instantiate the BUFG(for the four clocks which needs the clock tree) in the verilog/VHDL design itself. It certainly makes the design spefic to Xilinx thou. For the rest of the clocks I agree that its best way is to use LOWSKEW lines, also might try the constraint MAXSKEW. Thanx, Vikash "Joey Oravec" <joey@sun.science.wayne.edu> wrote in message news:9mv308$s42$1@cwis-1.wayne.edu... > Rick Filipkiewicz <rick@algor.co.uk> wrote: > :> I need to use more than 4 clocks in my design. The synthesis tool > :> (Foundation series) complains about the resource (clock) while I try for > :> implementing my design since there are 4 dedicated clock inputs ONLY > :> (Virtex-E , V1000). > : > : By default most synth tools automatically detect clock nets and assign > : whatever global buffers are available to them. In your case you have to > : decide which clocks are less important and turn this off. > > I'm back to college so I don't have a SynPro license anymore to test the > syn_noclockbuf however that's not exactly the behavior I understood. > > On most parts, you can think of the dedicated input pads and the global > buffer as different things. In many cases you want to use a dedicated > GCLKIOB pad for a conventional clock or reset signal. In other cases you > will use a normal pad, do some more asic-minded gating, then run the > "rightmost" actual clock network into a BUFG for good distribution. In the > latter case you could use a BUFG but not the dedicated input. > > With Synplicity there are at least two important constratints, xc_padtype > and syn_noclockbuf. A signal will be defined as a clock if it is > autodetected or listed in the SCOPE definitions. On most designs though, > the xc_padtype will be most important so you can specify which ones get > the dedicated input pins. There are relatively few times I can think of > for syn_noclockbuf since you almost always want to use the good resources > if they're available. > > The original poster's error actually sounds to me like too many GCLKIOBs > are being used which I frequently saw when using dc_shell. The solution > there might be to define -no_clock everything then define -clock the > signals that you want as GCLKIOBs. Neither FPGA Express nor Synplicity > gave me that too-many-used problem; the only time I had to constrain was > when I wanted specific signals to use the resource instead. > > It helps to mention what synth tool is being used to make an EDIF, I > didn't see that in the original post. > > -- > O..O Arcade machine collection: > (----) http://www.science.wayne.edu/~joey/arcade/ > ( >__< ) IRC - EFNet #rgvac: demigod2k > ^^ ~~ ^^Article: 34703
"Ben Franchuk" <bfranchuk@jetnet.ab.ca> wrote in message news:3B929FE0.2BC22D3A@jetnet.ab.ca... > Kevin Brace wrote: > > I won't call it a deception. > > Neither will I call WebPack a demo software. > > Like someone else said in the thread, do you expect Model > > Technology/Xilinx to give out their simulator for free without any > > limitations? > > YES! For the basic system. > Other people NO! FPGA companies Yes. They make their money > selling FPGA's not with software. > How would you like to buy a Car and it only runs on a TRIAL > road? A hammer that can only hit 50 times? > Ben. If I "borrow" a car I get a trial, if I buy it NO TRIAL. Same goes for my hammers, all the trial versions have gone back now and I bought one! DaveArticle: 34704
I guess it completely depends on you design, i.e how much of registering you are doing and how much is combinational logic. I guess there is no rule to define the ratio. Suggestion would be to start with a bigger part in the prototype and decide on the final one as you get the design working. "Jen" <jennifer.koehler@exchange.sp.trw.com> wrote in message news:58ad032f.0108291457.3f9b55c1@posting.google.com... > I am curious to know from any Virtex II users what they have typically > found > to be their %LUTs used and %Flip-Flops used. I have a design and I am > trying to pick the correct part. I am pretty sure how many FFs I will > be using..but a little weary on my estimates on combinational logic. > I would feel better knowing ratios others have foundArticle: 34705
Daniel Nilsson wrote: > > Hi. > I wonder how I do generate the bitstream using webpack, when I want to load > a custom memory with it (some sort of serial EEPROM), is there specified > anywhere what is what inside the bitstream, and how it shall be loaded into > the fpga (in this case a spartan device) I'm not really sure if the PROM Formatter actually cares whether you're targetting one a serial FPGA configurator ((E)E)PROM, or a parallel EPROM, or whatever. I just tell it to give me a .MCS file, and let my EPROM program figure out what to do with it. JTAG Programmer also knows how to deal with .MCS files. You can also tell it to spit out a HEX file format, which is nothing more than the proper bit-stream data (no .MCS or whatever type of formatting). One of the things I've done is to use a standard parallel EPROM and a small CPLD (9536) to turn the parallel data from the EPROM into a serial stream the FPGA could use. Xilinx has an app note about this somewhere. (This was a long time ago. Reason I did it this was was because I wanted to use something other than the Xilinx OTP configuration PROMs, so I could reprogram if necessary. This was before Atmel and Xilinx came out with their serial EEPROMs, which I think are still more expensive than the EPROM/9536 solution!) -andyArticle: 34706
Harry Chung wrote: > > Hi, > I try to configurate a FPGA by a XC18V04 and I would like to download the bitstream file to the Prom by a universal programmer. Then, what kind of file should I provide to the programmer, *.mcs, *.exo or *.hex? Whichever one your EPROM programmer supports! RTFM. Hint: every EPROM programmer I've used in the last ten years or so accepts .MCS. > Moreover, if I power on the system, what is the typical time required for a complete configuration of FPGA by prom? Or how long should DONE become HIGH? Again, RTFM. More specifically, RTFXDS! -aArticle: 34707
Ray, If I was designing the ISA board (been there, done that...), I'd put a local clock on it. There are probably other things on the board that you'd like to be synchronous to it... ---a Ray Andraka wrote: > > I had assumed he had some local clock. If none, he can use the sysclk (if it is > there at all), however, he cannot depend on the IOW or other signals being > synchronous with that nominally 14.3 MHz clock...it isn't in most systems. If there > is a question as to whether that clock even exists, or if you need a higher clock > rate locally, put an oscillator on the board. Last I dealt with ISA (a few years ago > now), one could still depend on having a sysclock, even though it was not often > used. With the latest boards with barely feigned ISA support, this may no longer be > true. > > "Andy Peters > > > Perhaps you should use a local clock of some reasonable speed to > > synchronize the ISA signals and run your state machine? > > > > --a > > > > DIVERSEG wrote: > > > > > > I have always tried to stick to sync designs. > > > However lately I have ran into a problem. > > > While designing some isa cards I read somewhere that I did not need to use BALE > > > to latch my address lines. > > > > > > Is this acceptable? > > > > > > Also I am decoding using a state machine in a FPGA with Sysclk as the clock for > > > transitions in my state machine. > > > > > > Last week I changed CPU and the new CPU card does not drive Sysclk. > > > Now my boards do not work. I called the board designer and de says that sysclk > > > now a days is not sync with the I/O signals anyway? > > > > > > Who do i believe? > > > > > > Is async acceptable? > > > > > > Are the address lines stable so BALE is not nescessary? > > > > > > Any comments suggestions? > > > > > > Xilinx foundation users is it possible to take the VHDL created by the state > > > diagram editor and make the state machine async and dependant on the input > > > signal transitions to go from one state to another? > > > > > > Steven Collins > > > Macha International, Inc. > > > 713-723-5040x13 > > > scollins@macha.com > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.comArticle: 34708
olivier JEAN <seilebost@aol.com> wrote in message news:ad4152cf.0109040515.71030a19@posting.google.com... > opende2001@aol.com (Opende2001) wrote in message news:<20010815095730.27208.00000830@mb-fr.aol.com>... > AY-3-8192 by using FPGA. > I have many informations about AY-3-8192 and I search any informations http://oric.ifrance.com/oric/index_english.html http://oric.ifrance.com/oric/index_french.htmlArticle: 34709
> We are working on schematic entry for the Virtex II device > XC2V3000-4BF957, but finding it difficult to enter manually. > It is time consuming to create this symbol as there are over > 900 pins. Unfortunately I don't have this. But for sure you must be lazy :) I personally entered more than 2000 pins (3 or 4 chips ...) and it took me about 4 days :( Have a nice day ! KonradArticle: 34710
Hello,
can someone tell me where i can get a few pieces of
Lattice ispLSI 1016E (in Germany). Is it still sold or is there an
replacement
part ? Speed is not much important, but it should be pin compatible.
Greetings,
Martin
Article: 34711Me too, and you can bet that it would be quite a bit faster than 14.3 MHz :-) Andy Peters wrote: > Ray, > > If I was designing the ISA board (been there, done that...), I'd put a > local clock on it. There are probably other things on the board that > you'd like to be synchronous to it... > > ---a > > Ray Andraka wrote: > > > > I had assumed he had some local clock. If none, he can use the sysclk (if it is > > there at all), however, he cannot depend on the IOW or other signals being > > synchronous with that nominally 14.3 MHz clock...it isn't in most systems. If there > > is a question as to whether that clock even exists, or if you need a higher clock > > rate locally, put an oscillator on the board. Last I dealt with ISA (a few years ago > > now), one could still depend on having a sysclock, even though it was not often > > used. With the latest boards with barely feigned ISA support, this may no longer be > > true. > > > > "Andy Peters > > > > > Perhaps you should use a local clock of some reasonable speed to > > > synchronize the ISA signals and run your state machine? > > > > > > --a > > > > > > DIVERSEG wrote: > > > > > > > > I have always tried to stick to sync designs. > > > > However lately I have ran into a problem. > > > > While designing some isa cards I read somewhere that I did not need to use BALE > > > > to latch my address lines. > > > > > > > > Is this acceptable? > > > > > > > > Also I am decoding using a state machine in a FPGA with Sysclk as the clock for > > > > transitions in my state machine. > > > > > > > > Last week I changed CPU and the new CPU card does not drive Sysclk. > > > > Now my boards do not work. I called the board designer and de says that sysclk > > > > now a days is not sync with the I/O signals anyway? > > > > > > > > Who do i believe? > > > > > > > > Is async acceptable? > > > > > > > > Are the address lines stable so BALE is not nescessary? > > > > > > > > Any comments suggestions? > > > > > > > > Xilinx foundation users is it possible to take the VHDL created by the state > > > > diagram editor and make the state machine async and dependant on the input > > > > signal transitions to go from one state to another? > > > > > > > > Steven Collins > > > > Macha International, Inc. > > > > 713-723-5040x13 > > > > scollins@macha.com > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 34712
Peter Ormsby wrote: > > Russell Shaw <rjshaw@iprimus.com.au> wrote in message > news:3B930207.41DEB05C@iprimus.com.au... > > Hi all, > > > > What advantages/disadvantages do segmented-interconnect fpgas have over > > continuous interconnect cplds? > > > > Is there more flexibility in placing pins with segmentation? > > > > A vs X: > > > > http://www.altera.com/literature/pib/pib18_01.pdf > > > Ray Andraka did a good job describing the differences. One thing I would > like to point out is that the Altera document you're pointing to is six (!) > years old. Like Mr. Andraka points out, newer Altera families have a > heirarchy of interconnect. APEX 20KE devices have LAB interconnects span 10 > logic elements (LUT/FF cells), MegaLAB interconnects span 16 or 24 LABs, and > several other levels of interconnect that are shorter than > all-the-way-across-the-device. To see even a different implementation of > interconnect, take a look at Altera's Mercury devices. In those the I/O > pads are dispersed throughout the die rather than just around the edges, > giving you the ability to use local interconnect on I/O signals, even from > nodes burried in the middle of the device. I would suggest that the Altera > document you point to doesn't mean much with respect to the more current > familes of programmable logic devices. > > BTW, I think that this idea of interconnect hierarchy is applicable to > Xilinx devices too - maybe someone who understands the Virtex II > architecture better that I could address what having more slices per CLB > means with respect to local interconnect within a CLB vs. interconnect > between CLBs. > > -Pete- With xilinx webpack (which i haven't used), how good a job does it do the routing? or do you need to hand route every design?Article: 34713
hi Do have someone have some fpga web or newsgroup or faq site address familiar with the comp.arch.fpga. pls tell me! thanks a lotArticle: 34714
hi Do have someeone have some fpga web or newsgroup or faq site address familiar with the comp.arch.fpga. pls tell me! thanks a lotArticle: 34715
When I implement a Duol Clock Fifo in an EPF10k10 chip. I found the signal
RDEmpty,rdusedw are strange from common SysncFifo(For instance :CY7C4265).
RDEmpty turn to right('0') after a long time !!!!!!
And who have implement it ( Duol Clk SyncFifo by LPM_FIFO_DC) in an EPF10k10 chip?
I only need a small depth ( 9BIT * 8).
Thx a lot!
lyqin@cti.com.cn
Article: 34716Vautomation offers USB 1.1 and 2.0 synthesizable (VHDL/Verilog) cores that easily fit in Xilinx-FPGA (we do our development work with a Virtex 2000e-6). See http://www.vautomation.com/vusb.htm (USB 1.1) and http://www.vautomation.com/vusbhs.htm (USB 2.0) regards, Mark "Moadl" <mkeller@fh-landshut.de> wrote in message news:ee721da.-1@WebX.sUN8CHnE... > Hi all, > > at the moment I'm thinking of using an FPGA from brand X to implement a USB interface. What I heard from brand X is that I should translate USB with 'You shouldn't bother' but that's not an answer I really want. > > So I'm wondering if anyone out there has successfully implemented a USB-interface in a Xilinx-FPGA or is this really something I should do in another way? > > Help would be very much appriciated. > > MoadlArticle: 34717
Russell Shaw wrote: > With xilinx webpack (which i haven't used), how good a job does it > do the routing? or do you need to hand route every design? A design tool flow starts with the sources, such as VHDL, Verilog, Abel, Java, schematics or what ever else. These are translated into a netlist, which has only things that are in the target part: such as lookup tables and flipflops. These are then mapped into "CLBs", which are several lookup tables and flipflops (and a few other bits of logic), the exact contents of a CLB depends on the target part. The CLBs are then placed to physical locations, and then are routed. For routing, the Xilinx tools do fairly well. For mapping and placement, it's often fairly easy to improve the clock speed at which a design runs at by constraining placement and/or mapping. This is needed if the design needs to run fairly fast, and "fast" is relative to the base speed of the part, and is also related to details of the design. In the latest parts, fast is somewhere above about 66 MHz. There are several different ways to constrain placement and mapping, ask about them when you have a design that needs this. -- Phil HaysArticle: 34718
"Chris Mc Clements" <cmcclement@computing.dundee.ac.uk> wrote in message news:<9mvos9$l4v$1@dux.dundee.ac.uk>... I wanted clock multiplication not divisionArticle: 34719
Is the Xilinx Multilinx schematics available, or any similar USB based design which works with Xilinx jtagprog? Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 34720
lyqin@cti.com.cn (Leon Qin) writes:
> When I implement a Duol Clock Fifo in an EPF10k10 chip. I found the
> signal RDEmpty,rdusedw are strange from common SysncFifo(For instance
> :CY7C4265). RDEmpty turn to right('0') after a long time !!!!!!
>
When you say a long time, do you mean a few clock cycles? The empty
and full flags have several (3? have to check the ahdl source)
flip-flops for synchronising across the clock domains, so there is
inherently some delay. Do you actually need to cross clock domains?
Otherwise the single clocked LPM_FIFO might be more like what you
expect. On the other hand, the Cypress part you mentioned is an
asynchronous part, which is different again, and not something that
Altera provides a standard LPM for.
> And who have implement it ( Duol Clk SyncFifo by LPM_FIFO_DC) in an
> EPF10k10 chip? I only need a small depth ( 9BIT * 8).
>
That should get implemented in flipflops I think in that part. If you
can get a 10K10E you will have the benefit of dual-ported EABs (1 read
and 1 write port) which improves performance. For such a small FIFO,
you would end up wasting a lot of an EAB though as they are 256x16
each, so maybe that's not such a good idea.
> Thx a lot!
>
Hope it helped!
Martin
--
TRW Automotive Technical Centre
martin.j.thompson@trw.com
Article: 34721Sriram S wrote: > > Hi friends, > > Without using a DLL/PLL how can i multiply a clock by 1.5. You need to double, to 2x clock, and then gate the 2x pulses, so that for every 4 in, 3 are passed, and one is swallowed. This will average 1.5x clock. Clock double can be done with a XOR gate, and a delay, or a XOR gate + FF, this gives nominally needle pulses. The XOR+FF includes a Tco delay term, so can be prefered for parameter tracking purposes. -jgArticle: 34722
martin.j.thompson@trw.com writes:
> lyqin@cti.com.cn (Leon Qin) writes:
>
> > When I implement a Duol Clock Fifo in an EPF10k10 chip. I found the
> >signal RDEmpty,rdusedw are strange from common SysncFifo(For instance
> >:CY7C4265). RDEmpty turn to right('0') after a long time !!!!!!
> >
>
<snip>
> On the other hand, the Cypress part you mentioned is an
> asynchronous part
<snip>
And now I've read the whole page (not just the part of the line that
says 'fully asynchronous...' - I didn't read the bit that continues
'... read and write operation'), I've seen the block diagram that
shows the clock pins! Sorry about that!
In which case, the LPM_DC_FIFO sounds like the part you need to use,
there are parameters you can tweks to affect the latency of the flag
signals. Let me know if you want more guidance.
Cheers,
Martin
--
TRW Automotive Technical Centre
martin.j.thompson@trw.com
Article: 34724
For scheduling I'd like to implement a special counter:
The counter has an extra input "Marked" of type STD_LOGIC_VECTOR(N-1
downto 0). The counter jumps to the next value with Marked(i)='1'. E.g.:
Actual Counter=2, Marked(2,3,4,6,7)='0' , Marked(1,5)='1', => Next
actual counter := 5
I plan to implement the counter for a fixed count length of 4 bit. At
the moment my approach looks like follows:
In a case statement I differentiate the actual counter value. Within the
case I make a series of if statements:
case Counter of
'0'
if Marked(1) then Counter:=1 else
if Marked(2) then Counter:= 2 else
if Marked(0) then Counter:=..0
else Counter:=0;
'1'
if Marked(2) then Counter:=2; else
if Marked(3) then Counter:=3; else
:
This is very brute force.
Are there any suggestions for a better (at least more general - with
"for" or so) implementation than mine?
Is this a standard counter described somewhere in literature (name?
references?)
Michael
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