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On Sun, 02 Dec 2001 23:15:41 -0500, rickman <spamgoeshere4@yahoo.com> wrote: >That may all be true. But I still maintain that place and route software >is inherently more complex than complilers. The tasks required to >convert C language instructions to machine code for a given, well >defined architecture is conceptually straight forward and well >understood by nearly anyone graduating with a computer science degree. >On the other hand, place and route algorithms are in a class of problems >known as NP complete if my schooling has not failed me (or my memory). >This means essentially that you can NEVER deterministically find the >best solution to the problem for a realistic application given the state >of technology in the foreseeable future. At least this is true until we >are using Quantum computing which can explore all solution sets >simultaneously. Code generation for standard processors is not nearly as simple as you suggest here. Even in the good old days of simple processors such as the PDP 11, there was the fundamentally hard problem of register assignment (which nowadays is only a solved problem in the sense that there are pretty good heuristics, the processors try to help, and there are worse problems). Modern processors have goodies like multiple levels of caches, branch prediction, out-of-order execution, vector units, and SMP. They all complicate code generation; sometimes a lot. It is far from trivial to generate the instruction sequence that requires the minimal number of processor cycles to execute, and that's even true for sane architectures like the ARM and Sparc. The i386 something else again. IMHO it's more a matter of acceptance. A program that is twice as large as is necessary or is half as fast as is possible is readily accepted for most applications. On the other hand, an FPGA configuration that uses twice the CLBs necessary or requires halving the clock frequency is often not acceptable.Article: 37226
Hey Alex, You could try www.silabs.com. They use a magic DSP method in their devices to attenuate jitter. Look for Cesium clocking ICs. This might be an alternative way of achieving your jitter requirements. HTH, Syms. "Alex Sherstuk" <sherstuk@iname.com> wrote in message news:<%uSO7.69056$RI2.38425920@news2>... > Austin, > > Thank you for valuable information. > > So, if I want to reduce the jitter on XILINX output to something like 10 > ps - I have to use some external triggers, clocked by extremely pure > frequency. > > And here the next question appears: > who manufactures low noise triggers? > > Is that true, that regular ALS logic flip-flops are introducing 15 - 20 ps > jitter? > > I guess, of course, there are some better triggers, - at least for expensive > jitter-measurement systems. > What kind of triggers? > > Thanks, > AlexArticle: 37227
I would like to know how to generate jedec files for jtag programming with Max++ baseline V10.0 and a ByteblasterMV ? Do we have to get full Max++ in order to generate jedec ? We are trying to programm an Acex 1K100 through a JTAG chain that also contains Xilinx PLDs and a DSP from TI. Thanks LaurentArticle: 37228
hi, I am using Quartus I, to compile a ( medium size project 18% logic element 10%memory) for an APEX20KE400. I am using verilogXL to compile the net list output of the compilation and i find a setup problem on an internal register, regardless of the clock frequency that i use, to feed the design for the simulation purposes. The quartus did not report any such problem and did met my timing requirements Does anyone have any hint for this problem, cause i cannot find any way out... Thanks in advance.Article: 37229
SGF2ZSBhbnlvbmUgdXNlIHRoZSBUcmlzY2VuZCBFNSBvciBBdG1lbCBGUFNMSUMgaW4gdGhlaXIg ZGVzaWduPw0KV2hpY2ggb25lIGlzIGJldHRlciBjaG9pY2U/DQpUaGFuayB5b3UgZm9yIHlvdXIg YWR2aWNlLg0KDQpTaW5jZXJlbHkgeW91cnMsDQpYaWFvDQo=Article: 37230
Glen, Funny, and neat and true story about the clocks. When I was hired at Xilinx, one of the first experiments I did was to make many ring oscillators. I went on to prove that they would phase lock, if and only if, they shared a well for some of the pmos transistors, or if they had adjacent lines (capacitive coupling) of a certain length. If they were built is CLB's that did not share any wells, or used interconnect that was not actually physically adjacent, then they did not couple. The rings tend to oscillate +/- 10% due to variations in the die, they are not easy to get phase locked. This led to a number of design techniques which are used to minimize coupling, as coupling of any kind adds cross talk induced delay variations (a.k.a JITTER), which is a bad thing to be adding. Austin glen herrmannsfeldt wrote: > Austin Lesea <austin.lesea@xilinx.com> writes: > > >I prefer to look at this as "what is the jitter noise floor" in a CMOS FPGA? > > >Getting in, and getting out of the FPGA is the biggest problem, > > followed by the internal distribution of the clock signals. > > >This is something we have carefully characterized, as we are the > >'FPGA Lab' responsible for the verification of the design. > > >To get in, get onto a BUFG (global clock resource) and then get > >out (by using the DDR clock forwarding FF's) is about 35 to 55 ps > >P-P (nothing else happening). > > >If you have an another BUFG operating, the jitter goes up to 55 ps > >to 65 ps P-P. > > This reminds me of a story about the TTL 74S124 (I think that is the > number) dual oscillator. I was told that it was almost impossible > to use both, as they will phase lock if at all possible. > > As I remember, phase locked oscillations were first discovered > by Huygens putting multiple pendulum clocks on the same wall. > You wouldn't expect the coupling to be large, but apparently enough. > > OK, web search and I find: > > http://www.soundfeelings.com/products/alternative_medicine/music_therapy/entrainment.htm > > So, might one expect problems with multiple, non-synchronous oscillator > inputs to the same FPGA? > > -- glenArticle: 37231
Hi, I'm running a course on FPGA design using Xilinx ISE 4.1i. Unfortunately, I can't get it installed properly , but the course has already begun. So I'd very grateful, if anybody could help me with the following problems. I installed ISE 4.1i as a single node network floating license on a Windows NT 4.0 Server. Clients use Windows 2000 Professional . I've got the following 3 questions: 1) The FLEX license mechanism doesn't seem to work properly. I received the license file by e-mail, installed it to a directory on the server machine and set the environment variable. Starting the FLEX license manager on a client, entering setup parameters, pressing control-start, everything is fine. But pressing Control-Stop, a message appears "Server Stop Failed". Pressing Control-Status, another message appears "Unable to obtain status due to missing lmgr325c.dll"; pressing Advanced-Diagnostics, again a message "Unable to perform diagnostics due to missing lmgr325a.dll" (same messages are shown on the server machine). I searched for these 2 dll-files on both machines, server and client: no success. What can I do to fix that problem? 2) Working on the counter-tutorial described in the installation manual, I couldn't synthesize the design. Following message is shown in the console window: "Starting: 'expresscli top.epfx' Unable read the Constraint Editor GUID Done: failed with exit code: 0001." What' can I do about that? Thanx a lot!!! Sincerely Bernd -- * Bernd Scheuermann, Institute AIFB, University of Karlsruhe, Germany * e-mail: scheuermann@aifb.uni-karlsruhe.de * URL: http://www.aifb.uni-karlsruhe.de/~bes * phone: +49 721 608 3924 --- fax: +49 721 693717Article: 37232
Ken McElvain wrote: > > John_H wrote: > > > I love seeing comments form others that reinforce the gripes I've had over > > time. > > > > My experience with the Altera MaxPlus-II tools is dated with no Quartus to > > back mu up but what I saw then is consistent with what I continue to see > > in Xilinx: > > > > Nobody is doing "critical route" placement. > > Take a look at the TOPS technology in Amplify. It does it's own > complete placement of a region while doing timing optimization on > the logic. It doesn't do the whole chip but regions can be pretty > large. Virtex and Virtex-E only. > > http://www.synplicity.com/about/pressreleases/SYB-101final.html Does this take timing constraints into account? If the front end tools are considering timing, then it needs to work with the same timing constraint database that the backend tool does. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 37233
Petter Gustad wrote: > > mrgs1000@yahoo.com (Mark) writes: > > > I am doing some research on place and route tools. I would like to > > collect as much information as possible about them. My primary focus > > is on Xilinx, but I would like to know if there are particular > > features on other vendors tools that you like or dislike. > > I like performance. > > Most place and route algorithms are building some kind of search tree > with an estimate of timing, congestion, etc. I think these > applications would run quite effectively on clusters of workstations > (or PC's). > > I would like to see place and route tools implementing distributed > algorithms so I could increase the throughput (not necessarily > linearly) by throwing cheap $2000 PC's at the problem... > > Petter Back when Neocad was a third party P&R tool vendor, they supported this on Sun workstations. I assume that it was a useful feature since it was taking hours to P&R a 4000 gate FPGA on a PC. But then they sold out to Xilinx and we have a "merged" tool compatible with the Xilinx marketing goals. Does anyone know if they still support distributed processing on workstations? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 37234
"Kevin Brace" <kevinbraceusenet@hotmail.com> schrieb im Newsbeitrag news:cc7b0b5f.0112032335.34c890b5@posting.google.com... > I will like to know if there is a way to increase clock skew by about > 1.0 ns through a .UCF file (User Constraint File). > I am having problems meeting Tsu (setup time), and adding 1.0ns of > clock skew won't totally solve my problem, but it will help. > I will like to add the clock skew through a .UCF file because the HDL > code has to be portable across different FPGA vendors (mainly Xilinx > and Altera). > The device I am using is Xilinx Spartan-II 150K system gate part > (XC2S150-5), and the software I am using is Xilinx ISE WebPack 4.1. Iam curious about INCREASING clock skew. Usually you use a DLL to REMOVE clock skew, dont you ?. Do you use the IOB FFs ?? Without DELAY active? What frequency are you running? Can you switch to a higher speed grade? -- MfG FalkArticle: 37235
"Bernd Scheuermann" <scheuermann@aifb.uni-karlsruhe.de> schrieb im Newsbeitrag news:9uis0f$89h$1@news.rz.uni-karlsruhe.de... > Hi, > > I'm running a course on FPGA design using Xilinx ISE 4.1i. Unfortunately, I > can't get it installed properly , but the course has already begun. So I'd > very grateful, if anybody could help me with the following problems. > > I installed ISE 4.1i as a single node network floating license on a Windows > NT 4.0 Server. Clients use Windows 2000 Professional . I've got the > following 3 questions: We use(ed) Foundation 1.5...3.3 and now 4.1 as well as ISE 4.1 on WIn95/98/2000 machines. We used no license server, just had the licence file on every PC. > "Starting: 'expresscli top.epfx' > Unable read the Constraint Editor GUID > Done: failed with exit code: 0001." You need the licence to use the constraints editor. -- MfG FalkArticle: 37236
Hi!
I'm looking for a way to use the data which are read back by the JTAG. The
application(a special kind of simulator) i wrote have to know the
values('1','0','Z') of the external signals which are read out by JTAG. As
far as i know the file format of the Xilinx JTAG tool isn't quite useful for
my purposes.
Does someone know another tool which makes more sense? (maybe a free one)
Or, does somebody know something more about the read back file format?
Any ideas how to pass these signal values to my Java application? (latching
of the file?, transform?,..)
(btw, i'm using a "xcv800bg432")
thanx in advance
Jens
Article: 37237Ken McElvain wrote: > John_H wrote: > > > Nobody is doing "critical route" placement. > > Take a look at the TOPS technology in Amplify. The improvements gained by Automated TOPS are touted as minor improvements in timing (5%-15% on your posters?), but granted - improvements. The Interactive TOPS is what was touted by Synplify and Xilinx both at the recent EDA Front to Back conference. The manual intervention to say that "duh, these circuit elements need to be close to each other" is, in my heavily biased opinion, a stopgap that should never need to be done. I suggested that I could hire my 8 year old nephew to run the Interactive TOPS and get much better results than the tools will provide. No extensive special knowledge needed. My arguement was simply that the place and route process should be - hands off - doing the critical routes first, backfilling from there. I thank you folks at Synpicity for trying to make up for other vendors' shortcomings. I'm just sad that the tool pricing for this stop-gap for inadequate tools has kept me in the business of editing my .ucf files rather than spinning the TOPS.Article: 37238
rickman wrote: > Back when Neocad was a third party P&R tool vendor, they supported this > on Sun workstations. I assume that it was a useful feature since it was > taking hours to P&R a 4000 gate FPGA on a PC. > > But then they sold out to Xilinx and we have a "merged" tool compatible > with the Xilinx marketing goals. Does anyone know if they still support > distributed processing on workstations? The only thing I know is available is distributed Multipass Place & Route. You can set up multiple workstation "nodes" but each node gets a complete pass of the P&R. If you're to the point you need to eek out that last half nanosecond and have a small number of fast machines this method of distributed P&R can be very helpful. For one design, though, nada.Article: 37239
Why not call Xilinx and tell them what's happening, and get them to help you fix the problem? --andy Bernd Scheuermann wrote: > > Hi, > > I'm running a course on FPGA design using Xilinx ISE 4.1i. Unfortunately, I > can't get it installed properly , but the course has already begun. So I'd > very grateful, if anybody could help me with the following problems. > > I installed ISE 4.1i as a single node network floating license on a Windows > NT 4.0 Server. Clients use Windows 2000 Professional . I've got the > following 3 questions: > > 1) The FLEX license mechanism doesn't seem to work properly. I received the > license file by e-mail, installed it to a directory on the server machine > and set the environment variable. Starting the FLEX license manager on a > client, entering setup parameters, pressing control-start, everything is > fine. But pressing Control-Stop, a message appears "Server Stop Failed". > Pressing Control-Status, another message appears "Unable to obtain status > due to missing lmgr325c.dll"; pressing Advanced-Diagnostics, again a message > "Unable to perform diagnostics due to missing lmgr325a.dll" (same messages > are shown on the server machine). I searched for these 2 dll-files on both > machines, server and client: no success. What can I do to fix that problem? > > 2) Working on the counter-tutorial described in the installation manual, I > couldn't synthesize the design. Following message is shown in the console > window: > > "Starting: 'expresscli top.epfx' > Unable read the Constraint Editor GUID > Done: failed with exit code: 0001." > > What' can I do about that? > > Thanx a lot!!! > > Sincerely > > Bernd > > -- > * Bernd Scheuermann, Institute AIFB, University of Karlsruhe, Germany > * e-mail: scheuermann@aifb.uni-karlsruhe.de > * URL: http://www.aifb.uni-karlsruhe.de/~bes > * phone: +49 721 608 3924 --- fax: +49 721 693717Article: 37240
Ray, Get this: I installed the 9.0 version of the tools on the machine, and tried to "import" a design from the previous generation. Nope, can't do that. OK, so I created a new "project." Maybe it'll let me import my pin-constraint file, so I don't have to retype (or worse, use a point-and-click GUI) to re-enter the 192 pins I've constrained? Nope, can't do that, either. This Sucks Eggs. -a Ray Andraka wrote: > > Wow, This sounds exactly like my complaints about Lattice 5 years ago (I > haven't used Lattice in a while). So sad to hear that nothing has changed. > > Andy Peters wrote: > > > Well, here's a complaint about Lattice's tools. > > > > For some reason, Lattice thinks that designers care about how many logic > > levels it takes to implement a function. See, I don't care. All I care > > is that the finished design meets my timing constraints (and fits). > > Problem is, Lattice's tools don't know a timing constraint from a hole > > in the wall. What their tools expect you to do is to pick a combination > > of fitter options, press "go" and after the place and route completes > > (if, in fact, it does), you have to manually go through the timing > > reports to see if you win or lose. And when you lose, you have to go > > back in and pick a different bunch of options. The fitter "effort" > > switch doesn't do what you think it does, it just picks a different > > algorithm. The "Explore" feature is broken. > > > > If you want to take advantage of the fast I/O output enables, you have > > to set a constraint in a constraint file that's call "end critical > > path." And the fitter will then warn you that there's "no combinational > > logic..." to minimize if you drive your output enable from a flop. (It > > still "does the right thing," but the warning is stupid.) > > > > I've told the Lattice rep more than once: I want to be able to set a > > period constraint and I/O timing constraints, push the "start" button, > > and go get a cup of coffee or get some lunch, and come back and find my > > chip either routed or failed to meet timing (or it wouldn't fit). > > > > I haven't even mentioned how unroutable their chips are. > > > > ---a > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 37241
"Philip Freidin" <philip@fliptronics.com> wrote in message news:mv7m0u4c8rsdmoi2hpc4hc9mdn115bpfbk@4ax.com... > On Mon, 3 Dec 2001 04:43:19 +0000 (UTC), VR > <crossing@notjordanbutaclockdomain.com> wrote: > >Hey all. > > > >I have a uC that's updating a register in my XC4010E via a standard "three-wire" SPI. > > <snip> The other night I took a look at this post, and was hoping you (or Ray, but I somehow suspected you would) would answer it...since I knew it would take me a while to respond...and I'm rather busy right now... so...thanks for answering, and I second your response, it's just what I would have said ;-)Article: 37242
John, Yes, currently there are such things as "single" D-triggers 74LVC1G79, 74LVC1G80 (from TI, Toshiba, and others). Their usage would minimize cross-talk as a source of jitter. But what about thermal and other radiotechnical noises in trigger circuits? What is internal noise of a modern trigger? Thanks, Alex P.S. Of course, I am intending to use clean enough master clock source - something like 5ps jitter. "John_H" <johnhandwork@mail.com> wrote in message news:3C0C190F.CC5A30A0@mail.com... > I don't know for sure if the results are spectacular but when I was designing > jitter test equipment for telecom, the approach I wanted to persue was to use > single-gate registers. At the time the pico-gate devices (someone's trademark, > I'm sure) or other associated small logic families didn't have registers > shipping, only planned. The biggest reason jitter is introduced is crosstalk > between elements within the same package. If there's only one element, how can > you have crosstalk? The jitter steps down to even smaller effects. > > If you treat the registers as analog elements - clean planes, nice clearance on > the traces to reduce crosstalk - you should get the clean edges you desire. But > they'll never be more clean than the clock source that drives the registers - > that *must* be clean. > > > > Alex Sherstuk wrote: > > > Austin, > > > > Thank you for valuable information. > > > > So, if I want to reduce the jitter on XILINX output to something like 10 > > ps - I have to use some external triggers, clocked by extremely pure > > frequency. > > > > And here the next question appears: > > who manufactures low noise triggers? > > > > Is that true, that regular ALS logic flip-flops are introducing 15 - 20 ps > > jitter? > > > > I guess, of course, there are some better triggers, - at least for expensive > > jitter-measurement systems. > > What kind of triggers? > > > > Thanks, > > Alex >Article: 37243
John_H wrote: > > rickman wrote: > > > Back when Neocad was a third party P&R tool vendor, they supported this > > on Sun workstations. I assume that it was a useful feature since it was > > taking hours to P&R a 4000 gate FPGA on a PC. > > > > But then they sold out to Xilinx and we have a "merged" tool compatible > > with the Xilinx marketing goals. Does anyone know if they still support > > distributed processing on workstations? > > The only thing I know is available is distributed Multipass Place & Route. > You can set up multiple workstation "nodes" but each node gets a complete > pass of the P&R. If you're to the point you need to eek out that last half > nanosecond and have a small number of fast machines this method of > distributed P&R can be very helpful. For one design, though, nada. To be honest, I don't think the Neocad tool was anything different. Their sales point was that you could run "many" passes of P&R over a weekend by tasking up all of your machines. Keep in mind that this was at a time when it took hours to P&R a simple chip because PCs were so slow by comparison (~66 MHz IIRC) and Windows was just being supported so that made the tools run even slower (although this was likely only the GUI as the P&R was most likely still a DOS app). Today you only need hours on a machine to P&R if you are doing >1000 Kgate designs. But certainly anything you can do to get the cycle time down would be useful. I wonder if anyone has done a calculation of the wasted CPU cycles on all the machines sitting on desks in the world. I know that some efforts have been made to utilize these CPU cycles such as SETI and encryption cracking. Anyone know of any compute intensive EDA applications that can be distributed over PCs? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 37244
Hi, Is there a free version of JBit or JRoute that I can get from the website? sincerely ------------- Kuan Zhou ECSE departmentArticle: 37245
I am trying to convert a design written in AHDL for an Altera part to a file that can be used to program an Actel part. Has anyone done this? How is this achieved? Cheers JasArticle: 37246
Hi, Synplify will generate a ncf file and if it is in the same directory as your edif file than xilinx will read it "automaticly" however notice that constain pass by ncf and not ucf can't be remove/edit. the reason you need also the ucf is that some constrain you can't pass as well as some constrain you will only add after firt trial of place and route. a small example for constrain you will have in ucf and not in ncf is the lock of the dll/bufg. have a nice day Illan dottavio@ised.it (Antonio) wrote in message news:<fb35ea96.0112022339.42d0d24@posting.google.com>... > Some question about this pair : > > 1)In Xilinx I use Synplify to synthesize, why there are always the > possibility to create a constrain file also in Xilinx ?? I had to > clear it ?? > > 2) Synplify produce a file .ncf containing P&R constrain , how I can > specify it like input to the P&R ??Article: 37247
Hi, you can bring the RTL view and open the constrain editor than look for the wire with the clock you want to constrain and simple drag and drop to the constrain editor in the clock section. have a nice day Illan dottavio@ised.it (Antonio) wrote in message news:<fb35ea96.0111300052.5f5fa4ad@posting.google.com>... > Good Morning , > today I've to talk about a problem with Synflify, I'm a new user of it > so maybe it is just a stupid problem, here it is : > > In my application I've a master clock at 165MHz and 3 derived clock > 165/3 , 165/4 and 165/6 , depending on a signal rate_sel I choose by > means of a multiplexer which one of the clock to use, the signal at > the out of the multiplexer is named clk_div_n . > > The problem is that I want to put the following constrain : > > clk -> 165 MHz > clk_div_n -> 55 MHz > > but in the constrain editor after compiling I've only clk signal > discovered, for it I've set 165MHz constrain and after compiling again > and mapping I've the following result : > > System clock -> 395 MHz (...what is this) > clk -> 87.2 MHz > clk_div_n_inferred -> 78.1 MHz > > so clk_div_n is inferred but there's no way to set the right constrain > on it. > Can you help me in set the right constrain to Synplify ver 7.02 ?? > > Thanks > AntonioArticle: 37248
I have been using Xilinx Fnd 1.5 for my work up to now. However it would not generate a bit streem in win2k so I switched to 4.1. I need to use md0 and md2 which are the high bits of the parallel interface. According to "The Practical Xilinx Designer Lab Book" I have to use those special symbols in the schematic editor which I did up to now. However in 4.1 those symbols are not there. I have also noticed that the ipad symbols are also missing. I checked the preferenced and the correct library is loaded(xc4000). I opened the library file in notepad and did a search to see if the symbol is there and just not loaded and I found that it is not in the library at all. According to Xilinx http://toolbox.xilinx.com/docsan/xilinx4/data/docs/lib/chap07/lib07022.htm md0 and md2 are included in the symbol library. I tried using md0 and md2 in the constrain editor but it gives me the familiar error message. Any ideas how this issue maybe resolved? Please have in mind that I don't fully familiar with vhdl(still using abel) so a schematic solution to this problem would be very helpfull. Thank you Eftychios EftychiouArticle: 37249
Hi, assuming the read address name is radd and the next read address is radd_next than to the memorey radd connect radd_mem which should be : radd_mem = rd ? radd_next : radd; this should make the mem look like register. Also make the radd and radd_next both to be register this will save you head-hack as for timing later. have a nice day Illan shengyu_shen@hotmail.com (ssy) wrote in message news:<f4a5f64f.0111290541.2df7746c@posting.google.com>... > Hi all > > I use MegaWizard in quartus to generate a ram block with 1 asyn read/1 > syn write register file. > > in megawizard, I do in the following ways: > 1 use LPM_RAM_DP+ > 2 use APEX20k400E > 3 single clock > 4 register only the write relate signal, not register the read signal > 5 no asyn clear for any register > > > but in the post syn simulation, I do not got the correct read result > > why? > > I want the read process some what like a combinational logic, same as > a register file read.
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