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Read below... alw@al-williams.com (Al Williams) wrote in message news:<a9835df1.0202212119.6cf9dcaf@posting.google.com>... > 1) Is there any way to parameterize your Verilog so that once you > bring the edif into MAX PLUS II you can still change the parameters? > It looks like the parameters get fixed after passing it through LS. My > guess is this is how it has to be, but that makes the MPII's inability > to do Verilog (for free, at least) a disadvantage. Not to my knowledge. "Parameter" is a verilog language construct, EDIF is just a netlist file format that don't know or care where the cells came from. > 2) I tried to put MPII and LS on my laptop. I disconnected from the > network and MPII still works, but LS complains I don't have a valid > license. Of course, LS won't even try to work from an HD serial port > license. I haven't tried it connected to the network, but ipconfig can > still see my adapter and apparently so can MPII. Any ideas? LS uses the NIC and cannot use the HD. I had to install a NIC in my home PC (not wired to anything) just to get LS to run. > 3) Anyone have any good references to some of the obscure design > doctor messages I've been getting? In particular, I keep getting a > delay warning on a reset line that makes no sense to me. Post 'em here, and we'll take a crack at 'em. > Just groping around for now. Any advice is welcome. > > Al W. Regards, jayArticle: 40051
Hello, I'm trying to use Impact to download the bit file to Spartan 2E 100 PQ208. I know the JTAG hardware (cable, parallel port, PC) are ok since I am able to do it for Spartan XL. When I try it with Spartan 2E, it tries to download it, but consistently fails with "done pin did not go high" error. When I check the CCLK for SPROM, it is continually toggling. Spartan XL requires the FPGA configured through PROM (or otherwise) with BSCAN before the JTAG download would work. For Spartan 2, the Xilinx note states "Virtex and Spartan-II Boundary Scan Code NOTE: Basic boundary scan operations are always available in these devices. BSCAN_VIRTEX/BSCAN_SPARTAN2 is connected to internal logic only." http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=2805 But is this true? Do I need to configure the FPGA with BSCAN before downloading the bit file to FPGA?Article: 40052
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= 1&getPagePath=6545 There is a setting that sometimes works set xil_hwd_pcab_fix =1 It in answer 6545 Steve "Eric Crabill" <eric.crabill@xilinx.com> wrote in message news:3C713E01.744BB64A@xilinx.com... > > Hi Shiva, > > I have encountered problems using Dell systems with parallel > download cables when used with the Hardware Debugger. I don't > know if this applies to the JTAG Programmer software or not. > Actually, I don't even think it is specific to Dell machines; > there have been a number of threads on comp.arch.fpga on this > topic. > > I teach a class at San Jose State, and the entire lab is filled > with Dell machines. It seems (by luck of the draw) that some > machines will not configure an FPGA correctly. > > The symptoms? The Hardware Debugger will attempt to configure, > and then indicate it was successful. However, the FPGA appears > to be "dead". > > I traced it down to some glitches on the port signals; what > happens is that the FPGA is actually configured, and then > "accidentally" cleared at the end of the programming sequence. > My workaround was to cut traces on the board so that the FPGA > cannot be initialized after the first power-on configuration. > Now it always configures the first time, but the downside to > the workaround is that if you want to configure again, you > must cycle the power to the board. > > Hope that helps, > Eric > > shiva kumar wrote: > > > > why does the JTAG CABLE not work on Dell systems for programming > > vertex FPGA's. >Article: 40053
Because I have never tried using an output FF inside an IOB, and
control a tri-state buffer inside an IOB from a CLB FF (regular FF)
instead of an IOB tri-state control FF, I wasn't sure if what I
described was possible.
When I use XST for synthesis, if I choose an option that uses IOB FF
(XST automatically duplicates the FFs that goes into an IOB), XST
attaches attributes to the netlist (.ngc file), but that attributes
causes both FFs (output FF and tri-state control FF) to get pushed
inside an IOB.
No, I don't usually add INST "FF_instance_name" IOB = TRUE; in my .UCF
file because I prefer letting the synthesis automatically add the
attribute, but I guess my design has this awkward requirement, so I
guess it is inevitable to specify IOB = FALSE in .UCF file.
I believe I can add IOB = FALSE during synthesis for each pins, but I
prefer doing at .UCF file level.
Yes, the theory is to move the tri-state control FF out of an
IOB, and bring it closer to the unregistered input to reduce routing
delay.
That will make my design (a PCI IP core) easier to meet setup time, but
will inevitably make Tval (Tco) worse.
However, I decided to use a feature called Address/Data Stepping which
Xilinx and likely Altera use in their PCI IP cores, so some additional
delay turning on/off a tri-state buffer won't cause timing related
issues (Tval < 11ns for 33MHz PCI, but Ton is Ton < infinite (In
practice, Ton < 30ns), and Toff is Toff < 28ns).
Well, the only side effect of doing this is a situation when GNT# is
asserted for only one cycle, the PCI device doing Address/Data Stepping
will have to relinquish the bus, and wait until GNT# gets asserted for
two or more cycles.
Of course, that will mean lower bus utilization, but I think it is
better than not meeting the setup time.
Changing the board layout/pin out is not always an option since
64-bit PCI requires the PCI interface to control 64-bits of AD's OEs
(and eight C/BE#'s OEs, too.).
Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)
Falk Brunner wrote:
>
>
> How can this improve setup time? Because you can move the FF closer to the
> generating logic? Hmm, maybe you should revisit you pin layout and rearrange
> some pins (yes, this is a little bit hard if the board is already finished
> . .;-)
>
> --
> MfG
> Falk
Article: 40054I forgot to mention, but the thing worked fine after a few trials when I added "INST "FF_instance_name" IOB = FALSE;" to my .UCF file. Now my design has one less problem. Kevin Brace (Don't respond to me directly, respond within the newsgroup.)Article: 40055
Thanks to all ............
I hope the driver for the parallel cable may not be installed
properly,
and that was giving the problem . After that I reinstalled the ISE
4.1i software . Tried to program the device worked successfully in my
PC.
Thank you all
regards
Yathish
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<a5687p$4v23g$1@ID-84877.news.dfncis.de>...
> "Kumar" <yatiks@yahoo.com> schrieb im Newsbeitrag
> news:b479edf8.0202212023.45241fd@posting.google.com...
> > >
> > > Looks like a driver problem.
> >
> > I dont think its a driver problem because when I connected the
> > printer to this port ,Printer worked properly.
>
> The parallel-cable has its own driver (dont ask me why such a simple device
> needs a "special" driver, always those stupid software guys . . . .:-0
> It is installed during the install of Foundation/ISE or Impact-stand alone.
Article: 40056Hi Kim, Though very elementary---please check the "Properties" in " Generate Programming File" in "Process" window.Here in the "Startup Options" please check the "Drive DONE pin high". All the above,assuming you are using 4.1i ISE or Alliance. Regards, SANKET. derive@hotmail.com (Mik Kim) wrote in message news:<a35ed87e.0202251556.784566b3@posting.google.com>... > Hello, > > I'm trying to use Impact to download the bit file to Spartan 2E 100 > PQ208. I know the JTAG hardware (cable, parallel port, PC) are ok > since I am able to do it for Spartan XL. When I try it with Spartan > 2E, it tries to download it, but consistently fails with "done pin did > not go high" error. When I check the CCLK for SPROM, it is continually > toggling. > > Spartan XL requires the FPGA configured through PROM (or otherwise) > with BSCAN before the JTAG download would work. For Spartan 2, the > Xilinx note states > > "Virtex and Spartan-II Boundary Scan Code > NOTE: Basic boundary scan operations are always available in these > devices. > BSCAN_VIRTEX/BSCAN_SPARTAN2 is connected to internal logic only." > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=2805 > > But is this true? Do I need to configure the FPGA with BSCAN before > downloading the bit file to FPGA?Article: 40057
Hi, Andy: Thanks for your information. If I am not wrong, did they ship products to Britain also? I was doubt whether I would get the chip since I am in Singapore. -- Best Regards, ----------------------------------------------------------------- Xu Qijun Engineer OKI Techno Centre (S) Pte Ltd Tel: 770-7049 Fax: 779-1621 Email: qijun@okigrp.com.sg "Andy Main" <andymain@blueyonder.co.uk> wrote in message news:3C76900A.6CC6511E@blueyonder.co.uk... > > > > Well, it looks like you work for a company, so burning a few buggy > > anti-fuse FPGAs won't cost you anything (It will cost the company > > something.). > > Quicklogic lets you burn up to 10 webASICs for free!! (we have been a very > happy customer at my workplace - save 20k on a new die just to test!) > > Andy Main >Article: 40058
kingcoolking@rediffmail.com (king) wrote in message news:<bd3eddeb.0202250435.2f60c6ea@posting.google.com>... > Hi all, > I have a design which uses say X no of XCV1000E FPGAs. I wud like to > go for denser FPGAs ( XC2V6000). The total system gates in XCV1000E is > approximately 1.5 Million while in XC2V6000 is 6 Million. So can I > assume that the logic implemented in four (6/1.5) FPGAs can be > implemented using a single XC2V6000 FPGAs? But the LUTs of the two > looks different. Will this affect the beforesaid ratio? Or is there > any other decisive factors involved? Ur reply will be most welcom > with kind regs > king If you have a working design you probably have a working tool-chain. Try to write a wrapper above your X chips, keeping all internal connections inside it and defining as ports everything that goes out (if you have a working HDL test-bench for the whole design, you can use it as template). Run this design through the tool-chain, selecting the new target device (Virtex2 or whatever you like) and see the reported size. Of course the reported size will not be 100% accurate, but you'll get an very good approximation; it's not a good idea to fill up an FPGA anyway - best not to go above 70% utilization unless the design is absolutely frozen and you want to save every last penny in production BOM.Article: 40059
Hi, comparing todays online refernces with the VIRTEX-II Handbook December 6'th 2000 shows that for I/O-bank 4 & 5 (XC2V1000 FG456) new inputs for the DCI reference resistors had been added. I'm having problems with our board which has been layed out according to the 'old' pinout diagram, so using the triple purpose pins as reference inputs. Does anybody know if I can still use the triple purpose pins or if I'll have to live without DCI in the future? If yes, how can I select to use the 'ALT_VRP/N' instead? Cheer's JonasArticle: 40060
I have come across an FPGA demo kit which contains very complicated circuit-board marked as Download Board plus a daughter board which has only a Spartan-2 chip and JTAG connector. If I don't have the Download Board, I only have a daughter board. If I use two DC power supplies to generate 2.5V and 3.3V, and Parallel Cable 3 for JTAG connection to my computer, then can I program this chip correctly? Thanks for your comments. -- Best Regards, ----------------------------------------------------------------- Xu Qijun Engineer OKI Techno Centre (S) Pte Ltd Tel: 770-7049 Fax: 779-1621 Email: qijun@okigrp.com.sgArticle: 40061
So the reasons seems to be the addressing that for LUTRAM is performed
with some LUT and so is not taked in account, just some question again
and then I think the scene is complete :
1) LUTRAM are the distribuited RAM available for example with the
Xilinx RAM CORE ??
2) In my case I need a ROM 4096x512, the best way to obtain it seems
to be using some CASE instruction that XST infer in a distribuited
ROM, do you agree on this ??
3) What do we do with the BLOCKRAM ??
Ciao
Antonio
Article: 40062"Falk Brunner" <Falk.Brunner@gmx.de> writes: <snip> > Talking about RAMs in FPGAs, the new Altera series sounds very promising. > ENDLESS RAM, in all sizes. And the smallest member comes in a 600++ pin BGA > :-0 > Still no small RAMs though :-) Anyway, you just need a small soldering iron and a steady hand. Alternatively, you can scrape the soldermask off the top of the BGA and wire onto the tracks on it.... -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 40063
guiducci@cern.ch (Luigi) wrote in message news:<235ed672.0202220541.3bb1e381@posting.google.com>... > Hi, > I'm developing a design under QUARTUS (I'll switch to QUARTUS II > soon). I have to assign I/O signals to specific pins in my device (to > organize them in a useful way for the board design). What I wasn't > able to find is if there's a different way to do it than using the > boring interface of the "Assignment organizer". I cannot assign 500 > pins clicking with my mouse! Yes (in quartus2), open the node-finder, select "pins unassigned", Named "*", then click "Start" to list all the pins. Now open "current assignments" floor-plan, and display the external package view. Now just drag and drop the pins from the node-finder window to the pins in the floor-plan window. Maxplus2 could do this, so any version of quartus probably would too.Article: 40064
Hi all, I've just started using web Quartus-2 to compile an edif file from leonardo spectrum (acex 1k30). In the edif file (and in the vhdl code), i have a signal called clk1M25 (an internal node). I wanted to set a timing constraint on it in relation to the clock input it is derived from (thru a counter circuit). However, clk1M25 doesn't appear anywhere using the node-finder search box. How can i find it?Article: 40065
Hi! I'm looking for a way to readback the values (0 or 1) of the external signals of an FPGA(a Virtex). In my thesis i don't need a (Xilinx) GUI because i need a opportunity to process these values in my own tools. So i wanna use JTAG, but all the papers i read only describe downloading the bit-files. And the (Xilinx)papers about reading back something (i want) from the chip are much to general and GUI-oriented... (Using Found. 4.1i, MultiLinx(usb), 800thVirtex) Q1: Is there a "simple" possibility(a file, a special stream description, ?) to read out the values of the external signals, so that i could say e.g. "external signal input1 has now a logical one,..."? Q2: "iMPACT" allows a command line option called "readbackToFile", has anybody some experience with this? Which kind of data are read back? Q3: Could the SVF file format help to solve my problem? Thanx in advance!!! All hints are really welcome!!! Jens Frauenschlaeger ---------------------------------------------------------------------------- -------- University of Leipzig - Germany Dept. of CS ---------------------------------------------------------------------------- --------Article: 40066
> Not to my knowledge. "Parameter" is a verilog language construct, > EDIF is just a netlist file format that don't know or care where the > cells came from. Yeah, that's what it looks like from here too. It looks like you can plug in parameters for AHDL, and I imagine if you bought the Verilog built-in that might work. > > LS uses the NIC and cannot use the HD. I had to install a NIC in my > home PC (not wired to anything) just to get LS to run. Well, it all works fine on the big machine, but the demo I wanted to do on the laptop wouldn't recognize either adapter without an actual network connection! Luckily, the registry fix posted earlier worked great! Still need the NIC but it doesn't have to connect to anything. Thanks! > Post 'em here, and we'll take a crack at 'em. So far I have figured most of them out, I think. It looks like it will complain mightly about anything asynchronous, including things inside metafunctions they supply! It appears that sometimes you just have to blow off its warnings? For example, if you want to divide down your incoming clock, it is going to complain even though that is what you want to do. Or should I wire my "new" clock to a global? I haven't tried that. I've put in a few examples from the Web and they are mostly done with ripple clocks that generate plenty of complaints, but seem to work. Just for the exercise, I've done a timer and an 8-bit PWM circuit and finally got all the clocks synced and get no warnings except for one strange one. Keeps telling me my reset line is tied to logic and that may prevent its use as a global signal. I think it is because I have one of the resets to a verilog module inverted and I guess that's a bad thing? I figured out how to tell it to quit trying to globalize reset and that clears up the message, but that's cheating too, I suppose. Works either way. Sigh... Al W.Article: 40067
...found solution in Xilinx answer database...Article: 40068
For your large ROM, you must use several BlockRAMs, 12 in Virtex, 3 in Virtex-II, as I described before. You just establish the content of the RAM by configuration, and then you never write to it again. Thus you have a ROM! Peter Alfke ================ Antonio wrote: > So the reasons seems to be the addressing that for LUTRAM is performed > with some LUT and so is not taked in account, just some question again > and then I think the scene is complete : > 1) LUTRAM are the distribuited RAM available for example with the > Xilinx RAM CORE ?? > > 2) In my case I need a ROM 4096x512, the best way to obtain it seems > to be using some CASE instruction that XST infer in a distribuited > ROM, do you agree on this ?? > > 3) What do we do with the BLOCKRAM ?? > > Ciao > > AntonioArticle: 40069
Sorry Peter , I'm a little bit confused, Maybe I don't understand very well english, and so I think you sayd somethng instead you say something else. 1) Block RAM are slower than LUT to implement a ROM 2) you tell me that for my large ROM I've to use a BLOCKRAM and never write to it, so to be clear, why you suggest me to use BLOCKRAM and not LUT if my design is hungry of speed ?? AntonioArticle: 40070
Sorry, jut reading your question again: For a 2 megabit ROM, you would need almost all the resources in a big FPGA. I would go for an external EEPROM. Peter Alfke ======================= Peter Alfke wrote: > For your large ROM, you must use several BlockRAMs, 12 in Virtex, 3 in > Virtex-II, as I described before. You just establish the content of the > RAM by configuration, and then you never write to it again. Thus you have > a ROM! > > Peter Alfke > ================ > Antonio wrote: > > > So the reasons seems to be the addressing that for LUTRAM is performed > > with some LUT and so is not taked in account, just some question again > > and then I think the scene is complete : > > 1) LUTRAM are the distribuited RAM available for example with the > > Xilinx RAM CORE ?? > > > > 2) In my case I need a ROM 4096x512, the best way to obtain it seems > > to be using some CASE instruction that XST infer in a distribuited > > ROM, do you agree on this ?? > > > > 3) What do we do with the BLOCKRAM ?? > > > > Ciao > > > > AntonioArticle: 40071
Does anyone have a delidded spartan II? I'm curious as to the die size. Thanks. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 40072
Hi, anybody here is using it ? Care to comment ? ThanksArticle: 40073
Hello, Who can tell me the funktion and intern circuit from Core generator2.1 of seriell FIR-Filter from Xilinx? tanksArticle: 40074
If you want to have a slower clock in your design, the clean way to do it is you generate a flip flop enable at the lower frequency and continue to run the high frequency clock to all the flip flops. Burns power but its what the componant architecture wants to see. The general rule is that the only thing the clock net should drive is a clock pin on a flop, and the only thing a reset line should drive is the reset pin of a flop. If you can structure your logic around those constraits, the tool will be a happy camper and you will get no warnings. The reason for this is that while on the surface, the FPGA seems like a magic black box that can configure itself into any circuit you describe, in reality, it has pre-existing connections, and particular ways of connecting key signals if you want to guarantee hold times. It has to know that the clock skew is always less than the shortest path that the logic must take, therefor special dedicated wires have to be built to route the clock which have constraints on their use. > > Post 'em here, and we'll take a crack at 'em. > So far I have figured most of them out, I think. It looks like it will > complain mightly about anything asynchronous, including things inside > metafunctions they supply! It appears that sometimes you just have to > blow off its warnings? For example, if you want to divide down your > incoming clock, it is going to complain even though that is what you > want to do. Or should I wire my "new" clock to a global? I haven't > tried that. > > I've put in a few examples from the Web and they are mostly done with > ripple clocks that generate plenty of complaints, but seem to work. > Just for the exercise, I've done a timer and an 8-bit PWM circuit and > finally got all the clocks synced and get no warnings except for one > strange one. Keeps telling me my reset line is tied to logic and that > may prevent its use as a global signal. I think it is because I have > one of the resets to a verilog module inverted and I guess that's a > bad thing? I figured out how to tell it to quit trying to globalize > reset and that clears up the message, but that's cheating too, I > suppose. Works either way. > > Sigh... > > Al W.
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