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"Jim Raynor" <chris@ultrasonix.com> schrieb im Newsbeitrag news:h2%v8.3428$n%4.252313@news2.telusplanet.net... > I started thinking of it and I thought it might be the temperature > problem. So, I tried to reproduce the problem again by cooling down the > CPLD with a can coke (!!put the ice cold can coke on the top of the CPLD for > 30 secs) and powered that up afterward. And I got that CPLD problem Funny ;-) > everytime now when I actually let the CPLD cool down and re-powered up. > > Now I have solved the problem by putting some of the CPLD tasks into the > u-controller that used in the same system. And the new program only used up > 79% of the macrocells. > > So I am wondering what did happen to the CPLD when the macrocells is > almost used up? Did you guys experience something like that before? Sounds more like a race-condition problem. Maybe you have made some nasty asynchronus tricks, that fail on cool (=fast) chips. -- MfG FalkArticle: 42326
--Block for down counter
library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_unsigned.all ;
use IEEE.std_logic_arith.all ;
use work.all ;
-- entity counter
entity counter is
port ( clk : in std_logic ; -- clock for counter
reset : in std_logic :='1' ;--
enable_pos : in std_logic := '1' ;
data_in : in std_logic_vector(15 downto 0) ;
out_puls : out std_logic :='1' -- output
) ;
end counter ;
-- end of entity counter
-- architecture arch
architecture arch of counter is
signal counter : std_logic_vector(15 downto 0) ;
signal output : std_logic ;
begin
p2 : process ( clk,reset,enable_pos )
begin
if ( reset = '0' )
counter <= ( others => '0' );
output <= '0' ;
elsif ( enable_pos = '1' ) then
counter <= data_in ;
elsif (clk'event and clk ='0' ) then
if ( counter > 0 ) then
counter <= counter -1 ;
end if ;
if ( counter = 1 ) then
output <= '1' ;
else
output <= '0' ;
end if ;
end if ;
end process p2 ;
out_puls <= output ;
end arch ;
-- end of architecture count_arch
-----------------------------------------------------------------------------
The above counter logic works fine for 32 MHz clock frequency .But it
doesnot work for64 Mhz clk . The chip slected is spartan2 series
(xc2s30 -5 speed grade ) .I am using FPGA express for impimenting and
ModelSim for place and route simulation .Behaviouralsimulation also
works fine.Everything is licensed
version . Doesn't work means counter value remains at zero does not
get decremented
Can anybody tell me why this is not working ? and what is the
maximum
frequency at which the chip(spartan 2 series) works properly ?
regards
yathish
Article: 42327
Kumar wrote:
> if ( reset = '0' )
Missing "then" ^^^^^^
> counter <= ( others => '0' );
> output <= '0' ;
> elsif ( enable_pos = '1' ) then
> counter <= data_in ;
Did you really want to load the counter regardless of clock?
Asynchronous load timing is tricky at best. Unless you really need this
I'd suggest:
**********************************
if ( reset = '0' ) then
counter <= ( others => '0' );
output <= '0' ;
elsif (clk'event and clk ='0' ) then
if ( enable_pos = '1' ) then
counter <= data_in ;
elsif ( counter > 0 ) then
counter <= counter -1 ;
end if ;
****************************************
> The above counter logic works fine for 32 MHz clock frequency .But it
> doesnot work for64 Mhz clk .
How are you testing this?
> The chip slected is spartan2 series
> (xc2s30 -5 speed grade ) .I am using FPGA express for impimenting and
> ModelSim for place and route simulation .
Using the free XST Web pack I get 8.713 ns clock period and less than 4
ns setup time, with the suggested modifications to the design. This is
using the static timing analyser.
--
Phil Hays
Article: 42328Hi! > Come on, the Spartan-II(E)s are really cheap, have a look at > > www.nuhorizons.com I see, an XC2S200-5PQ208 for US$ 26,25. But together with shipment and VAT (or customs) it goes up rapidely. At RS Components http://www.rs-components.at/ such a part costs EUR 64,46 (without VAT). This is double the price at nuhorizons. :-( (but RS at least has Spartan and Spartan-II at Austria (and Germany, I guess)) > even a poor student can afford them. So I really DONT like to play with > a just partly functioning IC, especially NOT for development. Debugging > you own mistakes is hard enough.. Nobody wants you to use partly defect ICs, I only thought to offer them. And that only makes sense if a detailed table with the tested errors is supplied. Or they give instructions how to test it by oneself. I looked at the XC2V6000, which costs up to US$ 8700,--. That is somewhere at a small car. My question to somebody involved in production of such parts: Why are these parts that expensive? Please don't misunderstand me, I really accept the price. I simply don't have any idea what can make a chip that expensive. Another question: What are typical uses of a XC2V6000 with e.g. 1517 pins? :-) Are they used for fast routing of network traffic in Cisco Catalyst routers (or such things)? I guess, a PC will not use these parts. What are typical capabilities, what can one typically put together into one such FPGA? Thanks HansiArticle: 42329
Johann Glaser wrote > Another question: What are typical uses of a XC2V6000 with e.g. 1517 pins? > :-) Are they used for fast routing of network traffic in Cisco Catalyst > routers (or such things)? I guess, a PC will not use these parts. What > are typical capabilities, what can one typically put together into one > such FPGA? To quote the president of General Motors, there is just no substitute for cubic inches.Article: 42330
Johann Glaser wrote: > I looked at the XC2V6000, which costs up to US$ 8700,--. That is somewhere > at a small car. My question to somebody involved in production of such > parts: Why are these parts that expensive? Please don't misunderstand me, > I really accept the price. I simply don't have any idea what can make a > chip that expensive. I've been out of the semiconductor manufacturing world for a while, but this sort of stuff doesn't change. Small die, high yield, low cost. Large die, small yield, high cost. Think of a wafer, with process flaws scattered over its surface. A small device on this wafer will have very many die per wafer, and almost all of them will be good, as only ones with process flaws are bad. These devices can be made fairly cheap, as the cost of the wafer is spread across all of them. Now think of a huge part, with few die per wafer. The yield will be low, a few percent, and only a small number of good die per wafer. These will be very expensive parts to manufacture. -- Phil HaysArticle: 42331
Hi, I've been trying to build an 8-bit ALU to use with FLEX10k and MAX+Plus II. The design were entered using the graphical method using primitives. So far, I've tried normal ripple carry, 1- and 2- stage Carry Lookahead adder. The worst was the 2 stage, using 2x4 bit (4bit 1-stage CLA). Which is quite expected due to the 'overhead'. Surprisingly however, the best was the normal ripple carry, 2X faster than the 2-stage. All of them were compiled using the same option (Fast synthesis), which allows the use of device specific goodies. More interestingly, my friend's design, using different logic gate combinations approach, managed to get even faster time. My ALU was a dedicated 8-bit adder + controls, while his was using 8 1-bit ALUs chained together, with the controls inside. What surprised me the most was that adding a simple "set less than" control which only required 2 gates, 'and' and 'not' cranked the delay up by ~20 ns. Now it is running at ~50 ns for a single 8-bit ALU. Now, the questions are : 1. Is the compiler smarter than me ? So far, it's been counter-intuitive to me. (OK, so I learnt from books that fewer gates == lower prop delay and the combinatorial hardware works in 'parallel', which meant the LookAhead should at least has the same performance as the ripple.) 2. Is there any way to map/fill every single logic element manually, or at least, does anyone know how do you know / how to set the LEs in arithmetic mode manually. 3. Using the most 'speed' compile setting, it does not yield any significant (if any) improvement at all. Whilst in the report file, I can see that in the larger design, the lower level adder actually didn't get the fast carry chain. While my instinct keep saying if I can put the adder in one whole block with dedicated fast carry chain will generate a faster result, again, very counter-intuitive. 4. From the help, by using Quartus fitter, you can't keep all your cliques and assignments. To anyone who has done this before, does assigning stuffs manually could get you better results, and if so, does it worth it ? 5. I've seen many people saying manual floorplanning, can anyone tell me whether it will help with my ALU ? 6. Any suggestions/advices are more than welcome. Thank you.Article: 42332
Any help? Is logic the clkdiv of the dll to have a phase difference with clkin? all other outputs are in phase as the datasheet explains Best Regards, HarrisArticle: 42333
On Fri, 19 Apr 2002 13:33:52 -0700, Austin Lesea <austin.lesea@xilinx.com> wrote: >Jay, > >Not so fast.... > >The devices have a custom test program that assures the part will meet all >requirements at speed for the intended application. > >Who bothers to look for the bits that don't get used by the application? >That would be really hard to do, and cost a lot of money, and take a lot >of time. A couple of questions: 1) How many parts a month does a customer have to buy to offset the cost of developing and running a special test program? Even if the generation of the test program can be automated, I'd think that trying to manage customer-specific test programs at the foundry would be challenging. Foundries are best at doing the very same thing (same die type, same test program) over and over. 2) Is what I pay for an EasyPath part a function of how much of the part I use? If so, is there a rule-of-thumb metric for how much I save for a given utilization? Bob Perlman > >Austin >Jay wrote: > >> I was wondering when someone was going to do this. Correct me if I'm >> wrong but basically the way this works is Xilinx screens parts at >> wafer probe with known defects against a particular design's P&R to >> see if it's fucntion would be adversly effected. If it isn't, then >> the part can be delivered and guaranteed to work for this particular >> design. Xilinx gets to sell silicon that would otherwise be discarded >> (or sold as engineering versions with an erratta sheet) and the >> customer gets some cost break on his mature application. >> >> I guess you still have to use the config parts as always, and you've >> given up the field upgradability benefits touted for FPGA based >> designs but for some applications this could really work. >> >> As an extension of this program, I'd like to these parts made >> available for sale in small quantity without the NRE charges and an >> RLOC file that goes with the serial number of the part or something >> like that to be included in the P&R to work around. The chips can be >> like diamonds where the price varies depending on the amount of >> defects from "flawless", to "slight inclusions". You buy what you >> need.Article: 42334
Russell wrote:
>
> Hi,
>
> When i 'synthesize' the attached vhdl code in xilinx webpack, why
> do i get this error? :
>
> Compiling vhdl file C:/Wave/globals.vhd in Library work.
> ERROR:HDLParsers:340 - C:/Wave/globals.vhd Entity <globals> does not
> exist in library <work>.
>
> Is there a free leonardo version for xilinx devices?
Russell wrote:
>
> Hi,
>
> When i 'synthesize' the attached vhdl code in xilinx webpack, why
> do i get this error? :
>
> Compiling vhdl file C:/Wave/globals.vhd in Library work.
> ERROR:HDLParsers:340 - C:/Wave/globals.vhd Entity <globals> does not
> exist in library <work>.
>
> Is there a free leonardo version for xilinx devices?
Nope, it's only Altera that does that.
I personally will prefer if Altera distributed a free version of
ModelSim instead of LeonardoSpectrum because if I have to, I can live
with QII's native synthesis (Altera in-house synthesis tool) which not
as good as XST (ISE WebPACK's synthesis tool.) or LS-Altera, but I
cannot live with a waveform simulator for simulating my design.
Until that happens, I probably won't use Altera free tools that
seriously.
Having used both XST and LeonardoSpectrum-Altera, I do feel like XST
seems to give better QoR than LS-Altera, and it doesn't have LS-Altera's
problem with their unstable GUI. (LS-Altera 2002 version is somewhat
better, but still occasionally crashes, which I don't think is
acceptable.)
I don't use VHDL, and I don't know much about it, so I am probably not
qualified to comment about your code, but I will say that you probably
shouldn't use a loop structure in a synthesizable code.
Besides that, every synthesis tool has slight differences in the
interpretation of a given HDL code, and it is often frustrating that
when code that works in one tool doesn't work in another tool.
That's just a way things work, and you will have to find a way to write
code where both synthesis tools can accept.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 42335I've been trying to talk to the download cable on Solaris 8 (Enterprise 250 Sparc). I have the cable's TDI pin hooked to a led for the test. If I run ecpptest the led blinks so something is working. I know I have to write to /dev/ecpp0 but everything I've tried doesn't seem to work. I'm hoping someone out there has the magic 4 lines of code so I can complete the port of my software. Thanks in advance Steve -- Remove the .nospam for the correct reply addressArticle: 42336
The Digilent Spartan IIE board is nice, and about $100, including the parallel cable for programming it. Get this and WebPACK, and its probably one of the cheapest ways to get started. I got the board through NuHorizons, and they are great if you get stuck or have any questions. One of their FAEs even lent me his JTAG cable for a week. Check'em out. Spam Hater wrote: > > It looks like a nice board. > > I'll contact you remotely about the software. > > On Tue, 16 Apr 2002 12:06:15 +0200, Johann Glaser > <Johann.Glaser@gmx.at> wrote: > > >Hi! > > > >> I'm looking for a SpartanXL demo board. Any good ones out there? > >> > >> Something I can download with my XChecker cable, and get at all the > >> pins. > > > >Look at http://www.digilent.cc/. They have a nice board. It is available > >with a Spartan or a SpartanXL FPGA (3.3V version). > > > >It is quite cheap, I think less than $100. The only problem is, that > >Spartan and SpartanXL are not supported by Xilinx WebPack. > > > >Downloading the configuration is done by a parallel cable. If you need > >instructions or souce code, you can have mine. I wrote a small Pascal > >program for Linux, but it is easily ported to whatever you need. > > > >Bye > > HansiArticle: 42337
Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in message news:<a9spqt$rpd$1@newsreader.mailgate.org>... > Russell wrote: > > > > Hi, > > > > When i 'synthesize' the attached vhdl code in xilinx webpack, why > > do i get this error? : > > > > Compiling vhdl file C:/Wave/globals.vhd in Library work. > > ERROR:HDLParsers:340 - C:/Wave/globals.vhd Entity <globals> does not > > exist in library <work>. > > > > Is there a free leonardo version for xilinx devices? > > > > > Russell wrote: > > > > Hi, > > > > When i 'synthesize' the attached vhdl code in xilinx webpack, why > > do i get this error? : > > > > Compiling vhdl file C:/Wave/globals.vhd in Library work. > > ERROR:HDLParsers:340 - C:/Wave/globals.vhd Entity <globals> does not > > exist in library <work>. > > > > Is there a free leonardo version for xilinx devices? > > > Nope, it's only Altera that does that. > I personally will prefer if Altera distributed a free version of > ModelSim instead of LeonardoSpectrum because if I have to, I can live > with QII's native synthesis (Altera in-house synthesis tool) which not > as good as XST (ISE WebPACK's synthesis tool.) or LS-Altera, but I > cannot live with a waveform simulator for simulating my design. > Until that happens, I probably won't use Altera free tools that > seriously. > Having used both XST and LeonardoSpectrum-Altera, I do feel like XST > seems to give better QoR than LS-Altera, and it doesn't have LS-Altera's > problem with their unstable GUI. (LS-Altera 2002 version is somewhat > better, but still occasionally crashes, which I don't think is > acceptable.) > I don't use VHDL, and I don't know much about it, so I am probably not > qualified to comment about your code, but I will say that you probably > shouldn't use a loop structure in a synthesizable code. > Besides that, every synthesis tool has slight differences in the > interpretation of a given HDL code, and it is often frustrating that > when code that works in one tool doesn't work in another tool. > That's just a way things work, and you will have to find a way to write > code where both synthesis tools can accept. This was the first time i used webpack. I found that when you add a new source file to the project, there's an option to say if its a vhdl module or vhdl package. Well that fixes that. I still get package type errors tho. In each of the source files, i also have a package declaration that holds entity declarations for each of the entities/architectures in that file. I guess i should take all these package declarions out and put them into a separate file(s) just for packages?Article: 42338
Wayne,
no.There isn't a DLL.Just IBUFG only.
"Wayne" <whalcomb@lucent.com> wrote in message news:<a9mvf6$jd1@nntpb.cb.lucent.com>...
> Is it feeding a DLL ?
>
> "mm" <lunaris_s@yahoo.com> wrote in message
> news:a2d0027.0204180731.3ca28548@posting.google.com...
> > Hi,all
> > I'm now encountering a strange thing with fpga.
> > CLKA is input to fpga through one of the GCLK pin.After IBUFG it
> > has the net name CLKA_IN.I watch CLKA and CLKA_IN on an oscillograph.
> > The strange thing is that sometimes when there are still
> > transitions on CLKA,CLKA_IN will pause for a while either staying "1"
> > or "0".
> > I also have another clk domain in that fpga CLKB and
> > CLKB_IN.CLKB_IN also pauses at the same time as CLKA_IN though CLKB
> > sitll has transitions as usual.
> > Isn't it strange?I've never ever heard of this.What should I do
> > now?
> > thx in advance
> > mm
Article: 42339
Hello all,
I use a XCV812E-BG560 for my design.
I have as input a 155MHz clock that I divide by 2 with the use of CLKDLLHF .
The external clock is LOC
constrained in an LVDS_DLL pin. I want to make use the clock155 and the
clock1/2 so I use 2 CLKDLLHF in
the way described below.
I run the map, PAR simulation vhdl codes and I see that the clkdv output of
the first CLKDLLHF is not in
phase with the clk155 (the clk155_int is in phase, also the clk90 and clk180
are in phase with the clkin of the DLL). The clkdv rising edge has 4 ns
delay in relation to clk155's rising edge
Am I doing something wrong? I have read all xilinx applications about DLLs
and I cant find a solution to this phase difference
------- bufg
----- | clk0 |-------|_|------|----clk155_ to internal logic
<--this signal is ok
clk155| | |
| | |
-- -- | clk1/2 |-----| | <----- the clkdv has a 4 ns
delay in relation to clkin!!!
| ------- | |
|_______________|_______|
_______________|
| -------
| | clk0 | bufg
|-------| |-----|_|--------------clkdv_2 to internal logic
| | |
--------|clkfb | |
| ------- |
|_____________________|
Best Regards,
Harris
Article: 42340
------- bufg
----- | clk0 |-------|_|------|----clk155_ to internal logic<--this
signal is ok
clk155| | |
| | |
-- -- | clk1/2 |-----| | <----- the clkdv has a 4
ns,delay in relation to clkin!!!
| ------- | |
|_______________|_______|
_______________|
| -------
| | clk0 | bufg
|-------| |-----|_|-----|---------clkdv_2 to internal logic
| | |
--------|clkfb | |
| ------- |
|______________________|
Article: 42341"H.L" <alphaboran@yahoo.com> schrieb im Newsbeitrag news:a9ubr7$2gs$1@ulysses.noc.ntua.gr... > Hello all, > I use a XCV812E-BG560 for my design. > > I have as input a 155MHz clock that I divide by 2 with the use of CLKDLLHF . > The external clock is LOC > constrained in an LVDS_DLL pin. I want to make use the clock155 and the > clock1/2 so I use 2 CLKDLLHF in AFAIK for this, you dont need two DLLs. Just connect the CLKDV output to the second BUFG and you are done. BUT you should make sure that the two clock nets have (more or less) equal load, otherwise skew can bite you. Ray Andraka already commented this problem and suggested to do data transfers between the two clock domains on different clock edges. The problem is, that the second DLL is useless, since a DLL can AFAIK only be feed back with a x1 or x2 clock, not with a divided clock. > the way described below. > > I run the map, PAR simulation vhdl codes and I see that the clkdv output of > the first CLKDLLHF is not in > phase with the clk155 (the clk155_int is in phase, also the clk90 and clk180 > are in phase with the clkin of the DLL). The clkdv rising edge has 4 ns > delay in relation to clk155's rising edge Sure, because there is a delay of (6.44 - 4 = 2.4 ns) in the clock buffer. But clk0 and clkdv are (should be) in phase. -- MfG FalkArticle: 42342
*No*. Convert tabs to spaces before posting. "H.L" wrote: > > ------- bufg > ----- | clk0 |-------|_|------|----clk155_ to internal logic<--this > signal is ok > clk155| | | > | | | > -- -- | clk1/2 |-----| | <----- the clkdv has a 4 > ns,delay in relation to clkin!!! > | ------- | | > |_______________|_______| > _______________| > | ------- > | | clk0 | bufg > |-------| |-----|_|-----|---------clkdv_2 to internal logic > | | | > --------|clkfb | | > | ------- | > |______________________|Article: 42343
rjshaw@iprimus.com.au (russell) wrote in message news:<c3771dbf.0204202321.4ee1dd2c@posting.google.com>... > Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in message news:<a9spqt$rpd$1@newsreader.mailgate.org>... > > Russell wrote: > > > > > > Hi, > > > > > > When i 'synthesize' the attached vhdl code in xilinx webpack, why > > > do i get this error? : > > > > > > Compiling vhdl file C:/Wave/globals.vhd in Library work. > > > ERROR:HDLParsers:340 - C:/Wave/globals.vhd Entity <globals> does not > > > exist in library <work>. > > > > > > Is there a free leonardo version for xilinx devices? > > > > > > > > > > Russell wrote: > > > > > > Hi, > > > > > > When i 'synthesize' the attached vhdl code in xilinx webpack, why > > > do i get this error? : > > > > > > Compiling vhdl file C:/Wave/globals.vhd in Library work. > > > ERROR:HDLParsers:340 - C:/Wave/globals.vhd Entity <globals> does not > > > exist in library <work>. > > > > > > Is there a free leonardo version for xilinx devices? > > > > > > Nope, it's only Altera that does that. > > I personally will prefer if Altera distributed a free version of > > ModelSim instead of LeonardoSpectrum because if I have to, I can live > > with QII's native synthesis (Altera in-house synthesis tool) which not > > as good as XST (ISE WebPACK's synthesis tool.) or LS-Altera, but I > > cannot live with a waveform simulator for simulating my design. > > Until that happens, I probably won't use Altera free tools that > > seriously. > > Having used both XST and LeonardoSpectrum-Altera, I do feel like XST > > seems to give better QoR than LS-Altera, and it doesn't have LS-Altera's > > problem with their unstable GUI. (LS-Altera 2002 version is somewhat > > better, but still occasionally crashes, which I don't think is > > acceptable.) > > I don't use VHDL, and I don't know much about it, so I am probably not > > qualified to comment about your code, but I will say that you probably > > shouldn't use a loop structure in a synthesizable code. > > Besides that, every synthesis tool has slight differences in the > > interpretation of a given HDL code, and it is often frustrating that > > when code that works in one tool doesn't work in another tool. > > That's just a way things work, and you will have to find a way to write > > code where both synthesis tools can accept. > > This was the first time i used webpack. I found that when you > add a new source file to the project, there's an option to say > if its a vhdl module or vhdl package. Well that fixes that. > > I still get package type errors tho. In each of the source > files, i also have a package declaration that holds entity > declarations for each of the entities/architectures in that > file. I guess i should take all these package declarions out > and put them into a separate file(s) just for packages? I figured it. Use "analyse hierarchy" on each file to get any package declarations included in library 'work'.Article: 42344
Hi, When i do "Design Entry Utilities|User Constraints|Edit Implementation Constraints (Constraints Editor)" in the "Processes for Current Source" window of ISE4.2, i get an error and the constraints editor doesn't go: Reading NGO file "C:/Wave/main.ngc" ... FATAL_ERROR:Portability:PortDynamicLib.c:309:1.10 - dll open of library <C:/xilinx_webpack/xilinxun/bin/nt/libNxXun_Bld.dll> failed due to an unknown reason. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com EXEWRAP detected a return code of '91' from program 'ngdbuild' Done: failed with exit code: 0091. I couldn't find anything on the xilinx site. System is Win2k, SP2.Article: 42345
I was just wondering if having an external clock running on one of the exterior global clock pins of the device causes problems in programming a Spartan2 device via slave-serial mode? In other words, does that clock need to be disabled during programming?Article: 42346
I post the code because I have some problems with the figure.. sorry for the
mess I may caused
clk155_p is the incoming clock (155MHz)
clock_dll1 : CLKDLLHF
port map (CLKIN => clk155_p, --use LVDS_DLL PIN
CLKFB => clk155, --feedback and the internal
155 clock
RST => gnd, --ground
CLK0 => CLK0,
CLK180 => OPEN,
LOCKED => LOCKED,
CLKDV => clk2_in --the divided internal
clock,input to DLL2
);
In post-MAP and PAR simulation clk2_in has 4 ns delay in relation to
clk155_p!!
clk155 is OK!
clock_feed : BUFG
port map (I => CLK0,
O => clk155 --the internal clk155
clock
);
clock_dll2 : CLKDLLHF
port map (CLKIN => clk2_in, --from dll1 clkdv output,the divided
clock
CLKFB => clk2, --the divided clock I use for
internal logic
RST => gnd,
CLK0 => CLK02,
CLK180 => OPEN,
CLKDV => OPEN,
LOCKED => locked_2
);
clock_2 : BUFG
port map (I => clk02,
O => clk2
);
Thanks in advance,
Harris
Article: 42347"Jim Raynor" <chris@ultrasonix.com> ha scritto nel messaggio news:h2%v8.3428$n%4.252313@news2.telusplanet.net... > I used the CPLD XC95288XL in my design and the program > used up 97% of > the macrocells of that CPLD. [...] > 30 secs) and powered that up afterward. And I got that > CPLD problem > everytime now when I actually let the CPLD cool down and > re-powered up. I have a very similar problem with a XC95144XL, but it isn't related to the temperature and the cell use is quite low. Some devices always work good, while others have several problems at power on. The problem is very strange because: -The system stays in a reset state for 250 ms after the power up; -If I restart the system by software (i.e. I start a debug session via JTAG, I use a TI DSP) after a failure without powering off and on, the CPLD works fine. Are there some tricks to make a CPLD start correctly? I haven't tied the global reset pin to the system reset, should I? -- LorenzoArticle: 42348
Hi all, I have a few queries about Virtex devices and JTAG. Is it possible to verify with JTAG the right function of a design downloaded into a Virtex ? I mean is it possible to pass values from a vector file to the input pins of the design and receive back a vector file with the values of the output pins? If it is so, can someone provide some sample BSDL code for configuration and verification for Virtex?Article: 42349
No Problem. During and before configuration, any Xilinx FPGA ignores activity on non-configuration related pins. Peter Alfke, Xilinx Applications Sean wrote: > I was just wondering if having an external clock running on one of the > exterior global clock pins of the device causes problems in > programming a Spartan2 device via slave-serial mode? In other words, > does that clock need to be disabled during programming?
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