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right to big "Phil Connor" <p.connorXXX@optionYYY.com> ???????:a535fee1911fb52170c541c52125287d.58911@mygate.mailgate.org... > I'm using ModelSim XE. > > On starting the simulation it goes through all the loading up > process OK and then closes with the message below :- > > > Internal error : bad pointer access ........... Closing vsim > vsim is exiting with code 11 > Trouble with peer processes (0), exiting. > > Anybody seen/solved this one. > > Maybe my design is to big for XE at 27k statements??? Would it > bomb out in this way? > > Thanks ! > > Phil > > PS. > > Why don't software packages give a website reference to a list > of error messages with a longer and less cryptic explantation > of what the error message means. > > eg. "Error Code 1175 see www.mentor....." > > > -- > Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 42278
I am having a tough time trying to simulate the following which was
coded for the VIRTEX-E:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
-- pragma translate_off
library unisim;
use unisim.vcomponents.all;
-- pragma translate_on
ENTITY clock_4x IS
-- Declarations
port (clk : in std_logic;
clk_4x : out std_logic);
END clock_4x ;
-- hds interface_end
ARCHITECTURE rtl OF clock_4x IS
component BUFG port (I: in std_logic; O: out std_logic);
end component;
component CLKDLL port (
CLKIN, CLKFB, RST : in std_logic;
CLK2X, CLKDV, LOCKED : out std_logic);
end component;
component SRL16 port (
D, A0, A1, A2, A3, CLK : in std_logic;
Q : out std_logic);
end component;
signal clk_2x, clk_4xi, clk_4xo, locked, q, q_rst, vcc, gd :
std_logic;
BEGIN
q_rst <= not(q);
vcc <= '1';
gd<='0';
U0 : BUFG port map (I=>clk_4xi, O=>clk_4xo);
U1 : CLKDLL port map(
CLKIN=>clk,
RST=>gd,
CLKFB=>clk_2x,
CLK2X=>clk_2x,
LOCKED=>locked);
U2 : SRL16 port map(
D=>locked,
CLK=>clk_2x,
A0=>vcc,
A1=>vcc,
A2=>vcc,
A3=>vcc,
Q=>q);
U3 : CLKDLL port map(
CLKIN=>clk_2x,
RST=>q_rst,
CLKFB=>clk_4xo,
CLK2X=>clk_4xi,
LOCKED=>clk_4x);
END rtl;
I cannot use CLKDLLE because Leonardo Spectrum does not support it.
But anyways, I cannot simulate this. I have compiled the unisim files
for modelsim SE using the xilinx_lib_4.tcl script with no problems.
But still when I load the code into Modelsim, it gives me "component
not bound" warnings and the simluation doesn't work. HELP!!!
- Paulo
Article: 42279Nicholas, Two important things: 1. the 12" fabs are new, and CLEANER than the older fabs. This is something that is known in the fab business: newer technology fabs are always better from a particle point of view, and yield goes up when you compare an 8" fab with a 12" fab. The sooner you can get to 12", the better it can be. 2. easy path does not map around 'bad logic'. You send us your stable design, and we send you chips marked just as ASICs are marked that are 100% good at speed for your application. That is why it is so easy! Customer does nothing, except make a committment to buy X units, non-refundable, non-returnable....hey just like an ASIC. The big difference? About a million $ for the NRE for the ASIC, compared with our NRE for the test program, supply management, and marking. Oh, and no time delay, and no risk. AustinArticle: 42280
When you compiled the unisim library did you create the unisim library mapping? $ vlib <path-to-libraries>unisim $ vmap unisim <path-to-libraries>/unisim $ vcom -work unisim <unisim-source-path>/file.vhd This will put all compiled elements into the unisim library. Drew Reynolds Paulo Valentim wrote: > I am having a tough time trying to simulate the following which was > coded for the VIRTEX-E: > > LIBRARY ieee; > USE ieee.std_logic_1164.all; > USE ieee.std_logic_arith.all; > > -- pragma translate_off > library unisim; > use unisim.vcomponents.all; > -- pragma translate_on > > ENTITY clock_4x IS > -- Declarations > port (clk : in std_logic; > clk_4x : out std_logic); > END clock_4x ; > > -- hds interface_end > ARCHITECTURE rtl OF clock_4x IS > component BUFG port (I: in std_logic; O: out std_logic); > end component; > > component CLKDLL port ( > CLKIN, CLKFB, RST : in std_logic; > CLK2X, CLKDV, LOCKED : out std_logic); > end component; > > component SRL16 port ( > D, A0, A1, A2, A3, CLK : in std_logic; > Q : out std_logic); > end component; > > signal clk_2x, clk_4xi, clk_4xo, locked, q, q_rst, vcc, gd : > std_logic; > BEGIN > q_rst <= not(q); > vcc <= '1'; > gd<='0'; > U0 : BUFG port map (I=>clk_4xi, O=>clk_4xo); > U1 : CLKDLL port map( > CLKIN=>clk, > RST=>gd, > CLKFB=>clk_2x, > CLK2X=>clk_2x, > LOCKED=>locked); > U2 : SRL16 port map( > D=>locked, > CLK=>clk_2x, > A0=>vcc, > A1=>vcc, > A2=>vcc, > A3=>vcc, > Q=>q); > U3 : CLKDLL port map( > CLKIN=>clk_2x, > RST=>q_rst, > CLKFB=>clk_4xo, > CLK2X=>clk_4xi, > LOCKED=>clk_4x); > END rtl; > > > I cannot use CLKDLLE because Leonardo Spectrum does not support it. > But anyways, I cannot simulate this. I have compiled the unisim files > for modelsim SE using the xilinx_lib_4.tcl script with no problems. > But still when I load the code into Modelsim, it gives me "component > not bound" warnings and the simluation doesn't work. HELP!!! > > - PauloArticle: 42281
Patrik, The CLKIN_STOPPED status bit will tell you if the input to the DCM has stopped, and the LOCKED signal will tell you if it has gone unstable (ie lose lock). The problem is that the BUFGMUX switches only between two transistioning clocks: if you stop one or the other, it does not switch, as it is a state machine that requires both clocks to be present. You may use a mux made from the CLB instead to control the source clock. Delay is now not controlled, so you would need to use a third DCM to deskew the new clock if deskew is needed. Otherwise get on the BUFG clock tree and go to work. I would mux between CLKA input, and CLKB input, based on CLKIN_STOPPED OR NOT(LOCKED), and not use the CLK0 outputs of the DCM's, and pass the selected clock from the mux to the CLKIN of the third DCM for deskew. That way, there is no jitter accumulation going through two DCMs. The first DCMs are only used as clock monitors. One would almost surely have to reset the third DCM after a switch to be sure you don't unhinge the third DCM by the asynchronous switch froma bad clock, to the good clock. Austin Patrik Eriksson wrote: > Hi, > > I have a design where the input clock is driven from one of two sources > depending on board configuration i.e. either from osc. A or from osc. B. > The two oscillators are never connected at the same time. > Each of the two input clocks are connected to one DCM respectively. > The clk0 output from the two DCMs are connected to an BUFGMUX which is > used to select which of the two input that should be used for the > internal clock. Is it possible to use the status output from the DCM(s) > to determine which clock input to use, i.e. control the BUFGMUX? > > FPGA > +-------------------------------------------+ > | +----------------+ | > +-----+ | | +---+ fb | | > | osc.| _ | +-|DCM| | | > | A |----->(_)---|-->|in |---+ + | | > +-----+ | | | |__|\ | | > | +---+ | \_|___internal_clk | > +-----+ | +---+ __| / | | > | osc.| _ | |DCM| | |/| | | > | B |----->(_)---|-->|in |---+ | | | > +-----+ | +-| |--------+ | | > | | +---+ status(1)| | > | | | | > | +----------------+ | > | fb | > | | > +-------------------------------------------+ > > Thanks in advance > > Patrik Eriksson > > -- > Patrik Eriksson | patrik.eriksson@netinsight.net > Net Insight AB | phone: +46 8 685 04 89 > Västberga Allé 9 | fax: +46 8 685 04 20 > SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.netArticle: 42282
Phillipe, Many customers use switching power supplies for the Virtex II core. We suggest that the maximum peak to peak ripple shall be less than 50 mV to meet all specifications. 10 mV is quite nice. I would say that 10 to 40 mV is typical of the boards I have seen from customers in my lab that are successful and working. Larger ripple will affect the speed of the design, and may be accomodated by having more margin. Larger ripple will also introduce jitter, and that may also lead to timing errors either in the design, or somewhere else in your system. Be sure the voltage at the pins of the device is 1.5 volts! Recently a customer complained their design did not meet speed. I had them measure their supply at the part: it was 1.28 V!!! No wonder it didn't go very fast. A Bientot, Austin Philippe Robert wrote: > Hi there, > > I have a new project starting ; that's a new board to design with a > Virtex-II FG456-XC2V1000. It is meant to work quite fast (200 MHz) ; I did > an estimation of the power required by the Core. I can't really get the 1.5 > Volts from a linear regulator without using a big heat sink. I would like to > do the power supply around a synchronous switcher. It's got an efficiency of > around 85% and generates ripples on the output lines of 10mV. > > Could the ripples affect the stability of the Virtex-II ? > > Thanks for your help. > > Philippe.Article: 42283
My telecom compagny went lately on second round of firing, and closed all US operation, My charter vacation flight has been canceled, I might not be able to take vacation to take the load of work from the US, My wife is angry after me and I'm afraid of divorce, I lost 10000$ on internet stocks, My parent is angry after because he wants me to pay for my brother education in Canada, I'm seeing a psycholgist and I'm on medication for 8 years.... BUT ON THE BRIGHT SIDE, I HAVE BEEN NAMED BY MY BOSS AS .... .......... F P G A COACH ........... of the compagny So I'm looking for literature to teach beginners FPGAs. Mister the Mayor.Article: 42284
Tsoi Kuen Hung <khtsoi@cse.cuhk.edu.hk> wrote: > Hi, > I have a design using the VirtexE DLL (HF). The Xilinx ISE 4.1i TRACE tools > report a critical path which count the same path twice. The Xilinx ans. for > this is that I use a two phase clock in the design which need to x2 the path > delay. My desing has only two clock (clk and clkdiv from DLL) and only rising > edge is used. What is the possible error. If this is by default, how can I get > the *real* timing report. The original design implementing under 3.1i does not > have this problem. I just add a small DFF in the original datapath to make it > faster and switch to 4.1i. What's wrong? Thanks in advance. > ---- Brittle The actual fact is that I have a register clocked by clk and the output of the register is input to a component clocked by clkdiv. Is this the cause of my problem? If yes, what can I do? The design is correct and run correctly. I just want the real critical path reported. Thanks in advance! ---- BrittleArticle: 42285
In article <3CC028CE.2CEBCABC@xilinx.com>,
Austin Lesea <austin.lesea@xilinx.com> writes:
|> 2. easy path does not map around 'bad logic'. You send us your stable
|> design, and we send you chips marked just as ASICs are marked that are 100%
|> good at speed for your application. That is why it is so easy! Customer does
|> nothing, except make a committment to buy X units, non-refundable,
|> non-returnable....hey just like an ASIC. The big difference? About a million $
|> for the NRE for the ASIC, compared with our NRE for the test program, supply
|> management, and marking. Oh, and no time delay, and no risk.
I wonder how this can be done (technically)... How do you permanently program
the chips? I remember vaguely a similar offer for the XC4k-series a while ago...
--
Georg Acher, acher@in.tum.de
http://www.in.tum.de/~acher/
"Oh no, not again !" The bowl of petunias
Article: 42286On Thu, 18 Apr 2002 16:57:21 -0700, Peter Alfke <peter.alfke@xilinx.com> wrote: (snip) >Within Xilinx, I am known to be the harshest critic of marketing BS in public >seminars, and I have ( successfully?) fought for more and more technical "meat". > >Originally, I had been concerned about PW2002, therefore I attended in San >Jose. And I came away excited, happy, and even proud. In San Jose you could pick and choose which technical training tracks to attend. In Toronto we were shown four preselected videos. The rational for this is obvious, but it results in my experience being much different than your experience. Also, you have to put yourself in the shoes of an engineer that has little or no knowledge of VirtexII Pro. If you were in this position, how much would you have learned at PW2002? If you have not yet seen the IBM (C1) track then I suggest you do. I think you will appreciate my frustration with this presentation. (snip) >Having won the attention, and perhaps even the hearts and minds of most design >engineers, we now face a new challenge: We have to convince engineering and >corporate management to change their mindset, to adopt multi-gigabit >transceivers and on-chip PowerPC for their next-generation designs. Or to give >up on ASICs. And in the larger companies, such decisions are usually not made at >the design engineer's level. So we have to sell our capabilities higher up the >corporate ladder. >FPGAs are not glue-logic anymore, they are now part of high-impact >architectural, system-level, and business decisions. So we have to change the >tone of our story, to appeal to a new audience. As I said, it was clear that the target has shifted away from the engineer. If that's what Xilinx wants to do then that's fine, but this reduces the value of the presentation to me, since I am concerned with the technical aspects. Since Xilinx listed engineers in the "who should attend" list, I expected the same level of technical content as was in previous seminars. > >We still have lots of detailed technical info, app notes, cores, books and CDs >and also training sessions and FAEs, ready to explore the finer details; and >many of these details are really utilized by the software automatically. I agree whole-heartedly. My issue here is only with PW2002. > >So, please, keep coming to our Seminars and Events, but also use all the other >ways to inform yourself about Xilinx products and solutions. The era of FPGAs >has just begun... Maybe Xilinx needs to have two different seminars. Something like PW2002 for managers, and then in-depth technical presentations for engineers. > >BTW, we just finished a great quarter, increasing our sales 20% >quarter-to-quarter, thanks to satisfied customers, like the ones in this >newsgroup. We weathered the storm without any lay-offs, just with >belt-tightening. That's something to be proud of, and thankful to you, our >customers. I have always liked Xilinx technology, and I have no desire to change. Xilinx competitors are always knocking on our door, and we always turn them away. PW2002 rubbed me the wrong way, and I heard other attendees grumble as well. Xilinx should know this, and that's why I posted my review. (snip) =================================== Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.comArticle: 42287
Greg, Thank you for your honest comments. Anyone else out there wish to provide us with some feedback? Too techie? Too marketing? To Rah Rah Rah? Just because some of us are wildly excited doesn't mean that others are. I understand that. In fact, since I have been working on Virtex II Pro for more than a year now (old news for me), I was a more than a little suprised by the numbers attending, and the success of the event. In retrospect, I realize the revolutionary product that it is, and I am exciting about its future. Remote locations vs. the main sites? We reached ~ 10,000 people, and I have to believe some of them are on this newsgroup. If you feel that you do not want your comments in the public eye, I will respect that, and you can send them to Peter or myself directly. We are likely to do this again, and we strive to always be improving. Thanks, Austin Greg Neff wrote: > On Thu, 18 Apr 2002 16:57:21 -0700, Peter Alfke > <peter.alfke@xilinx.com> wrote: > > (snip) > >Within Xilinx, I am known to be the harshest critic of marketing BS in public > >seminars, and I have ( successfully?) fought for more and more technical "meat". > > > >Originally, I had been concerned about PW2002, therefore I attended in San > >Jose. And I came away excited, happy, and even proud. > > In San Jose you could pick and choose which technical training tracks > to attend. In Toronto we were shown four preselected videos. The > rational for this is obvious, but it results in my experience being > much different than your experience. > > Also, you have to put yourself in the shoes of an engineer that has > little or no knowledge of VirtexII Pro. If you were in this position, > how much would you have learned at PW2002? If you have not yet seen > the IBM (C1) track then I suggest you do. I think you will appreciate > my frustration with this presentation. > > (snip) > >Having won the attention, and perhaps even the hearts and minds of most design > >engineers, we now face a new challenge: We have to convince engineering and > >corporate management to change their mindset, to adopt multi-gigabit > >transceivers and on-chip PowerPC for their next-generation designs. Or to give > >up on ASICs. And in the larger companies, such decisions are usually not made at > >the design engineer's level. So we have to sell our capabilities higher up the > >corporate ladder. > >FPGAs are not glue-logic anymore, they are now part of high-impact > >architectural, system-level, and business decisions. So we have to change the > >tone of our story, to appeal to a new audience. > > As I said, it was clear that the target has shifted away from the > engineer. If that's what Xilinx wants to do then that's fine, but > this reduces the value of the presentation to me, since I am concerned > with the technical aspects. Since Xilinx listed engineers in the "who > should attend" list, I expected the same level of technical content as > was in previous seminars. > > > > >We still have lots of detailed technical info, app notes, cores, books and CDs > >and also training sessions and FAEs, ready to explore the finer details; and > >many of these details are really utilized by the software automatically. > > I agree whole-heartedly. My issue here is only with PW2002. > > > > >So, please, keep coming to our Seminars and Events, but also use all the other > >ways to inform yourself about Xilinx products and solutions. The era of FPGAs > >has just begun... > > Maybe Xilinx needs to have two different seminars. Something like > PW2002 for managers, and then in-depth technical presentations for > engineers. > > > > >BTW, we just finished a great quarter, increasing our sales 20% > >quarter-to-quarter, thanks to satisfied customers, like the ones in this > >newsgroup. We weathered the storm without any lay-offs, just with > >belt-tightening. That's something to be proud of, and thankful to you, our > >customers. > > I have always liked Xilinx technology, and I have no desire to change. > Xilinx competitors are always knocking on our door, and we always turn > them away. > > PW2002 rubbed me the wrong way, and I heard other attendees grumble as > well. Xilinx should know this, and that's why I posted my review. > > (snip) > > =================================== > Greg Neff > VP Engineering > *Microsym* Computers Inc. > greg@guesswhichwordgoeshere.comArticle: 42288
"Paulo Valentim" <prv3299@yahoo.com> wrote in message news:5ed45146.0204190606.15737b20@posting.google.com... > I am having a tough time trying to simulate the following which was > coded for the VIRTEX-E: > > LIBRARY ieee; > USE ieee.std_logic_1164.all; > USE ieee.std_logic_arith.all; > > -- pragma translate_off > library unisim; > use unisim.vcomponents.all; > -- pragma translate_on > > ENTITY clock_4x IS > -- Declarations > port (clk : in std_logic; > clk_4x : out std_logic); > END clock_4x ; > > -- hds interface_end > ARCHITECTURE rtl OF clock_4x IS > component BUFG port (I: in std_logic; O: out std_logic); > end component; > > component CLKDLL port ( > CLKIN, CLKFB, RST : in std_logic; > CLK2X, CLKDV, LOCKED : out std_logic); > end component; > > component SRL16 port ( > D, A0, A1, A2, A3, CLK : in std_logic; > Q : out std_logic); > end component; > > signal clk_2x, clk_4xi, clk_4xo, locked, q, q_rst, vcc, gd : > std_logic; > BEGIN > q_rst <= not(q); > vcc <= '1'; > gd<='0'; > U0 : BUFG port map (I=>clk_4xi, O=>clk_4xo); > U1 : CLKDLL port map( > CLKIN=>clk, > RST=>gd, > CLKFB=>clk_2x, > CLK2X=>clk_2x, > LOCKED=>locked); > U2 : SRL16 port map( > D=>locked, > CLK=>clk_2x, > A0=>vcc, > A1=>vcc, > A2=>vcc, > A3=>vcc, > Q=>q); > U3 : CLKDLL port map( > CLKIN=>clk_2x, > RST=>q_rst, > CLKFB=>clk_4xo, > CLK2X=>clk_4xi, > LOCKED=>clk_4x); > END rtl; > > > I cannot use CLKDLLE because Leonardo Spectrum does not support it. > But anyways, I cannot simulate this. I have compiled the unisim files > for modelsim SE using the xilinx_lib_4.tcl script with no problems. > But still when I load the code into Modelsim, it gives me "component > not bound" warnings and the simluation doesn't work. HELP!!! > > - Paulo You can also add these lines into your default modelsim.ini file (i.e. the one loaded when you run modelsim) and you will always "see" the libraries no matter which is your pwd . You can set the default modelsim.ini by setting the enviroment variable MODELSIM to <path_of _your_modelsim.ini>\modelsim.ini [Library] others = $MODEL_TECH/../modelsim.ini modelsim_lib = $MODEL_TECH/../modelsim_lib logiblox = D:/Modelsim-Xilinx/logiblox simprim = D:/Modelsim-Xilinx/simprim unisim = D:/Modelsim-Xilinx/unisim xilinxcorelib = D:/Modelsim-Xilinx/xilinxcorelib The libraries were compiled in D:/Modelsim-Xilinx directory gianziArticle: 42289
> would then like to have an instruction set > simulator for this processor. With the Altera Excalibur NIOS development kit > there is a simulator, but I can't find the source code for it. I have two suggestions: 1) The source for the GNUPro toolkit for Nios is at ftp.altera.com. Login as "doc", password "degree". You'll find the files easily. 2) I highly recommend using the simulation features provided by SOPC Builder. SOPC Builder outputs HDL (ie- a full simulation model) for your Nios system, it automatically generates a testbench to initialize your memories & stimulate your Nios system, and it automatically generates a ModelSim project environment. There is no learning curve to get a basic simulation of your real Nios system booting code in ModelSim. See Altera's App Note 189 for complete documentation. The instruction set simulator has no awareness of the actual hardware environment, and thus does not give you an accurate idea how long your code takes to execute in real hardware. If that's what you need, then great. On the other hand, a simulation in ModelSim will tell you EXACTLY how your hardware will behave, as well as how many clock cycles it takes your software to execute. You can watch the instruction stream for your software issue through the CPU, and see all data transfered between processor and peripherals. Of course, you'll need ModelSim. If you purchase a subscription to Quartus II, then you already have a license for ModelSim Altera Edition, and you're ready to go. Hope this helps. Matthew "Mats Brorsson" <Mats.Brorsson@imit.kth.se> wrote in message news:<a9gnr5$3f7$1@news.kth.se>... > Hi, > > I'm considering using the NIOS processor from Altera for lab exercises in a > computer organization course and would then like to have an instruction set > simulator for this processor. With the Altera Excalibur NIOS development kit > there is a simulator, but I can't find the source code for it. Anyone knows > of another simulator for this architecture? > > Please respond by email since I do not regularly read the news groups. > > Regards > > Mats Brorsson > Mats.Brorsson@imit.kth.seArticle: 42290
"Georg Acher" <acher@in.tum.de> schrieb im Newsbeitrag news:a9pal7$fao$2@sunsystem5.informatik.tu-muenchen.de... > I wonder how this can be done (technically)... How do you permanently program > the chips? I remember vaguely a similar offer for the XC4k-series a while ago... AFAIK they dont. They just test the parts (LUTs/BRAM/interconnects) used by the design and leave the rest untested. Saves a lot of money. -- MfG FalkArticle: 42291
Paul, Thank you for your honest and genuine review, and follow up along with clarifications on your views of the book. A few clarifications: I opted to show the 2 HDLs because I still believe that a user familiar with one HDL can quickly learn the other HDL form both a textbook dedicated to the HDL inquestion, and with my book that contains lots of examples. CHapter 9 address the differences, a topic not really addressed in other books. Incidentally, I ran into those difficulties when I learned Verilog, and Verilog users could'nt really explain to me the intricate differences. Thus, I believe that my claim for the transition from one HDL into the other is still valid. Thanks for clarifying the issue of money. Incidentally, Mike Treseler is pretty close to the target of "The author might get $10 a book", particularly when going with a big publisher. >>It also does take research on the web, >> something that was brought up as a "trivial manner, not worth the effort >> of the consolidation of the necessary, and filtered information". >I never suggested it was 'quick'. I also did not suggest that research on >the web was at all trivial. In fact I don't recall seeing your quoted >statement in the thread. You're correct. My quote was really a summary of what I undertood from the various postings. For a moment it sounded like I just copied/pasted all material from the web to throw a book in 1 week. That did not happened, as you clarified. Thank you for finding value in this book. I would like to see other authors writing advanced books on methodologies/processes/circuit design/real issues. -------------------------------------------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------------Article: 42292
I was wondering when someone was going to do this. Correct me if I'm wrong but basically the way this works is Xilinx screens parts at wafer probe with known defects against a particular design's P&R to see if it's fucntion would be adversly effected. If it isn't, then the part can be delivered and guaranteed to work for this particular design. Xilinx gets to sell silicon that would otherwise be discarded (or sold as engineering versions with an erratta sheet) and the customer gets some cost break on his mature application. I guess you still have to use the config parts as always, and you've given up the field upgradability benefits touted for FPGA based designs but for some applications this could really work. As an extension of this program, I'd like to these parts made available for sale in small quantity without the NRE charges and an RLOC file that goes with the serial number of the part or something like that to be included in the P&R to work around. The chips can be like diamonds where the price varies depending on the amount of defects from "flawless", to "slight inclusions". You buy what you need.Article: 42293
For what it's worth - the Xilinx MicroBlaze development kit *does* include a cycle accurate instruction set simulator. Thus cycles, and user designated Hz (0 to 150Mhz), yields real clock time. Of course you may also use Model Tech - but you are not forced to do this to get the real execution time of your program. Matthew Mahr wrote: > The instruction set simulator has no awareness of the actual hardware > environment, and thus does not give you an accurate idea how long your > code takes to execute in real hardware. > > Matthew > -- Mark Aaldering Sr. Director IP Solutions Division Xilinx.comArticle: 42294
1) Do you know when the Multilinx changes the DIN output in respect with the CCLK output in the serial slave programming mode? 2)Do you know the timing relationship between Multilinx's CCLK and the signals CS_B, RDWR_B and D(0:7) in the slave selectMAP programming mode ? In other words when the Multilinx changes the above control signals in respect with the CCLK. At the positive or negative edge of the CCLK ? ThanksArticle: 42295
How do you take this into account in your IOB's? In an ASIC you can ripple the timing of the outputs so they don't all slam all at once but more of a cascade fashion. The whole point of the FPGA output flop in the IOB is to reduce "clock to out" time and this a constant in an FPGA for a particular output configuration. As for the hundreds of MHz speeds. Ya, sure it possible for specific types of designs, but we aren't helping anyone by convincing people new to the technology that they are speed equivalents. I mean, an FPGA is made from an ASIC process. I can buy the same processing from TSMC Xilinx can (especilly these days). Every couple weeks we get another newbee in here saying "Hi, I'm thinking about prototyping my 100,000 flip-flop ASIC design in a Vertex 2. It has to run at 200MHz, is this a problem?" They both have their place is the solution space. An ASIC will never be able to do what an FPGA can, and an FPGA will never be able to completely do what an ASIC can do. Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3CBF35B9.4ACDFBF3@xilinx.com>... > Jay, > > I disagree with 3, below, as we take this into account when we design our IOBs. > > The SSO guidelines in the datasheets takes into account both AC and DC currents (ie for DCI), so > that it makes design easier. > > It is a manual operation, however. > > The guideline does assume near perfect bypassing. By that I mean that if you can not bypass every > power ground pin pair with a cap, then the guideline must be reduced by the reduction in bypassing. > > Near perfect bypassing is a cap from 0.1uF to 0.01 uF (not much difference) 604 surface mount, with > at least two vis at each end abutting the pads to the power planes, along with some lo esr > tantalums (maybe 1 390 uF or larger) per IO bank. > > Traces to pads, minimum via diameters, are all very bad for ground bounce. > > Flip chip packages, and minimal inductance is very good for minimizing ground bounce. > > After all, V= - L di/dt. > > As for low frequencies, 420 MHz in Virtex II, and 500 MHz in Virtex II Pro doesn't sound all that > low to me. > > Wake up: FPGAs are right up there with the ASICs.....and we are available NOW. About the time you > finish that ASIC that you claim beats us flat out, we will already have our next generation, after > the next one, and still be ahead. > > Austin > > > > Jay wrote: > > > There is a also an equivalent limitation for simultanious switching > > outputs in ASIC's as well. Basically you can't try to dump a ton of > > current out one side of the chip (ASIC or FPGA) all at once because > > the supply pin inductance is too high to do so without significant > > voltage droop. Its usually not as big an issue in FPGA's because they > > generally operate at low frequencies (and thus lower required edge > > rates) compared to the ASIC cousins. So do the tools automatically > > handle this? The answer is no, but it most cases your FPGA emulation > > of your ASIC will be a in a completely different package anyway. > > > > Ways to help SSO (simulatanious switching outputs) > > 1) Use the slowest edge rate you can get away with > > 2) Use the lowest current driver you can get away with > > 3) Don't use flops in the output cells they tend to synchronize (by > > design) the output changes. > > > > Regards > > > > Sujatha Sriram <sujathasriram@yahoo.com> wrote in message news:<3CBE8A79.FB53A92C@yahoo.com>... > > > I have read that there is a limitation to the number of adjacent output > > > drivers that can switch at the same time in an FPGA. There are rules > > > stated in terms of SSO(simultaneous switching outputs) pads between > > > power/gnd pins. Can anyone please elaborate on that.. > > > In such a case, consider a RTL written for ASIC, and say it has to be > > > prototyped. Tools are used to partition the design into multiple FPGA's. > > > How is this condition taken care of by the tool. Does it place the > > > interface signals taking the limitation into account? or does the > > > designer have to take care of it manually.. > > > > > > > > > > > > --Article: 42296
Austin Lesea wrote: > Anyone else out there wish to provide us with some feedback? Too techie? Too > marketing? To Rah Rah Rah? I found it to be a complete waste of time and will never again attend one of these "seminars". I sat next to a Xilinx FAE who laughed and joked about the hokiness of the whole thing making it impossible to even hear what was being said, not that anything was worth hearing. If this was for managers, why didn't you invite them? I'm not a manager, why was I invited? As my boss said, the way to learn about new Xilinx products is invite *them* to come to *us* and present exactly what we want to know. So I already knew way more about Virtex 2 Pro than was presented at this seminar because we'd had it presented to us. The fact that one had no choice (at the outlying locations) to pick which sessions to view was NOT mentioned at all. I only discovered it while looking through the brochure during one of those silly "Good Morning America" type episodes. This was what angered me the most. I assure you that many many people came away with a bad taste in their mouths on this one.Article: 42297
"Cyrille de Brébisson" wrote: > Hello, > > Does anybody knows when the Virtex II pro boards will be available for sale? > > regards, Cyrille I've been told late summer by some reps. -- Tullio Grassi ====================================== Univ. of Maryland - Dept. of Physics College Park, MD 20742 - US Tel +1 301 405 5970 Fax +1 301 699 9195 ======================================Article: 42298
Believe it or not we have a design strictly sinchronous (ALL flip-flops with the same clk), the logic simulation and the static timing analysis are fine, but the post-P&R simulation reports several timing violation from VirtexE dual-port RAMs (we use ISE4.2). Also in my case the Xilinx support (Case # 420370 and another one) was not satisfactory. Tullio Grassi Ray Andraka wrote: > I don't concur. It is very, no extremely, rare that the P&R tools screw up a > design. A post P&R won't tell much of anything that a thorough static timing > analysis and functional (pre-PAR) simulation won't tell you. It can actually be > rather dangerous, as it can be very difficult to come up with a set of vectors > that cover all paths, especially in a large design. > > To check on the synthesized results, use the mapped output from the synthesis > for a post synthesis functional simulation. It will run a lot faster than the > timing annotated post PAR simulation.Article: 42299
hi guys,
I used the CPLD XC95288XL in my design and the program used up 97% of
the macrocells of that CPLD. Functional and Timing simulation were done and
everything is good. However, my co-workers kept complaining the CPLD was
mulfuntion sometimes. I tried to reproduce the problem that he was having
but I couldn't, the CPLD worked for me everytime. I started to check the
VHDL program and the signals using scope but they looked fine for me.
The problem for the CPLD kept coming. He experienced that the problem
happened 3 times out of 10 times when he powered up the CPLD. And he said
the problem happened everytime when he first powered up the CPLD when he
came in in the morning.
I started thinking of it and I thought it might be the temperature
problem. So, I tried to reproduce the problem again by cooling down the
CPLD with a can coke (!!put the ice cold can coke on the top of the CPLD for
30 secs) and powered that up afterward. And I got that CPLD problem
everytime now when I actually let the CPLD cool down and re-powered up.
Now I have solved the problem by putting some of the CPLD tasks into the
u-controller that used in the same system. And the new program only used up
79% of the macrocells.
So I am wondering what did happen to the CPLD when the macrocells is
almost used up? Did you guys experience something like that before?
Jim Raynor
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