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Hello, I'm looking for some references about the comparaison in terms of power, performance, and cost between a FPGA implementation and a multi-DSP system. I believe, that in all cases the FPGA is a better solution, but I would like to find some figures (at least for a few applications) so far, I didn't find anything on the web, so if someone has some links or paper ... Thank you, StevenArticle: 42501
In article <d049f91b.0204251000.62472132@posting.google.com>, Jay <kayrock66@yahoo.com> wrote: >Your proposed project sounds like you'd be making use of a lot of >other peoples code, and you'd be playing tool custodian to bring them >all together. Maybe a better project would be to design and impliment >a simple processor on your FPGA. If you feel gutsy you could drive a >video display in addition. ALso, keep the ISA simple: the minimum feature set to do what you want to do, and build just a very simple assembler. If you want a compiler, then use LCC. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 42502
Thanks for the reply, Austin, Using an external PLL together with a VCO would multiply my frequency up. However, is it possible to multiply this frequency up internally? Or am I missing something here. Adrian > Noddy, > > To use a DDFS, you need 2 X the highest output frequency as the input > frequency. I would take the 5 MHz maser, multiply it up externally with a PLL > to > 100 MHz, and then run the DDFS with that. You also may have to filter the > 1/CLK jitter from the DDFS output, and another PLL that is 1:1 will do that > fine. > > Or, you can synthesize a 2 MHz output with your 5 MHz clock, and run it to a PLL > that is 1:16 to get your 32 MHz AND filter the jitter at the same time. > > For ultra low jitter and stability, I would use a VCXO as part of the PLL doing > the filtering. > > I designed GPS Stratum 1 clock sources for 12 years, and that is how I did it. > Note I have the patent on the techniques, so be sure to read the patent and do > it differently (not hard to do), or license it from my former employers. > > Austin > > Noddy wrote: > > > I suppose maybe I should've been a bit clearer. If I am correct in saying, a > > DDFS will generate digital values for a synthesised waveform, to be used as > > input into a DAC. What I need is to generated a square wave output at a > > given frequency, using the 5MHz signal as a reference... ideally i am trying > > to generate a 32MHz signal. > > > > Noddy > > > > > Noddy, > > > > > > Use a DDFS (direct digital frequency Synthesizer). > > > > > > Austin > > > > > > Noddy wrote: > > > > > > > Hi, > > > > > > > > I am trying to design a high precision (30 bit) frequency synthesiser > > inside > > > > a Spartan II. Of course, normal way to do this is with a charge pump, > > > > voltage controlled oscillator and a phase lock loop. > > > > > > > > Can anyone point me to some good references? I have a very high > > precision > > > > 5Mhz which is generated from a hydrogen maser and will be used as the > > input > > > > clock signal. > > > > > > > > thanks > > > > adrian > > > >Article: 42503
Why would changing input frequency cause skew? Are you talking about changing frequency dynamically? Regards "Felipe Joffre Romano Renon" <Felipe.Renon@ic.unicamp.br> wrote in message news:<aa461q$v4a$1@aracaju.ic.unicamp.br>... > How i can change frequence input from Kit Excalibur Altera (33Mhz), without > Skew ?Article: 42504
Hy Jay,
Yes .. The input frequence can exchange as operations in circuit.
Thanks
"Jay" <kayrock66@yahoo.com> escreveu na mensagem
news:d049f91b.0204251014.7bb8ef36@posting.google.com...
> Why would changing input frequency cause skew? Are you talking about
> changing frequency dynamically?
>
> Regards
>
> "Felipe Joffre Romano Renon" <Felipe.Renon@ic.unicamp.br> wrote in message
news:<aa461q$v4a$1@aracaju.ic.unicamp.br>...
> > How i can change frequence input from Kit Excalibur Altera (33Mhz),
without
> > Skew ?
Article: 42505Spartan-II parts are 5V tolerant when using the PCI33_5 IO standard. rickman <spamgoeshere4@yahoo.com> wrote in message news:<3CC81A57.6E0E0EE4@yahoo.com>... > Actually, you are violating the max Vih spec for these chips. Spartan > II devices are not 5 volt tolerant and should not be used in this > application. We are doing the same thing with the same chip and we are > using a CoolRunner part as a large buffer chip to isolate the ISA bus > from the Spartan II chip. > > If you are just designing an IO mapped, 8 bit peripheral, then you only > need 8 data bits plus 10 address bits and 3 or so control lines. You > can interface all this with three 245 chips. But as another poster > said, you have to decode the address inside the FPGA to generate the > enable to the 245 data buffer chip. If you are enabling it on just > IORD, then you are responding when any IO device is being read and > corrupting that data. This is why your PC won't boot. > > So add the decoding to the SpartanII, use a pullup on the enable to the > data bus 245, enable the address and control line 245s at all times with > the direction fixed to input from the bus and your design should start > to work. > > > Sean wrote: > > > > Hi everyone again. > > > > I think I solved my problem, but I did it by completely getting rid of > > the transciever and simply putting 4.7k ohm pullup (to 5V) resistors > > to the bus outputs. It seems to work fine, aside from some single > > glitches on a few occasions. In any case it's much more reliable now > > that it was. I'm not doing something foolish by using pullup > > resistors on the bus though am I? It doesn't seem to cause any harm > > or impede the operation of the PC in any way, at least visibly. > > > > Sean A Laughter <s2salaug@mail2.vcu.edu> wrote in message news:<Pine.SGI.4.33.0204241846190.308721-100000@neptune.vcu.edu>... > > > Hi everyone. > > > > > > I'm interfacing a Spartan-II to an ISA/PC-104 bus. I have had no success > > > with tying the Spartan directly to the bus, it is just not reliable and > > > gives me sporadic values when reading from the Spartan. Since I have no > > > trouble writing to the Spartan I'm assuming it has something to do with > > > the 3.3V just basically not making it over the wires to the bus (because > > > all my errors appear to be 1's that are being interpreted as lows). > > > > > > Anyway, to rectify this problem I'm attempting to use a 74HCT245 > > > transciever to pull the Spartan outputs to a full 5V. I'm tying the > > > IOread signal to the direction pin of the transciever, but I can't get the > > > PC to boot when the setup is attached to the ISA data bus. > > > > > > I've decided this is probably because the transciever needs to be in > > > isolation mode at the appropriate time. However, I can't think of a way > > > to do this during boot. It would be easy enough to control this once the > > > Spartan is programmed because I'd have my ISA port code and I could just > > > output a few signals to tell the 74HCT to go into isolation. This > > > obviously isn't possible before the chip is programmed though, and so I'm > > > stuck with a PC that won't boot with the spartan (via the transciever) > > > attached to the data bus. The "enable" signal is active low. So when it > > > is high the chip goes into isolation, which is what I would want at > > > boot-up. > > > > > > Has anyone else used this chip in this fashion and can tell me how they > > > solved this problem, or does anyone have any ideas on how to solve this > > > problem? Thanks. > > > > > > Sean > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 42506
It's me again, in my ongoing saga and struggle with this ISA bus implementation. I am communicating over the bus fine now, but am having problem with my synthesizable VHDL. The way it is working is that we have VHDL modules describing an input (as seen by the PC) port and an output ISA port. We're going to have about four input ports and one or two output ports in the description of the chip (meaning it will respond to about six I/O address, some for read, some for write). The input port description synthesizes with a tristate data bus. However, the output port synthesizes with only an input bus since it will only be reading the bus, and only doing that when it's address is present (hence, no bus contention). When I do a top-level design using one input port and one output port it creates the data bus fine and creates iobufs on the bus. However, for some reason when I have one ouput port and two input ports the synthesis tool gives a warning saying there is no port type for the data bus and automatically gives it only output buffers. This results in the following problem. Once the chip is programmed by the PC the data bus automatically causes contention on the bus and so the PC goes crazy. I just don't understand why it would suddenly not be able to determine the my bus needs to be a tristated iobuf instead of just an output buffer.Article: 42507
Jeremy D. Grotte wrote: > > Cool. I really didn't expect any responses, much less a > couple here and a half a dozen e-mails in one day... > > I did some thinking about the circuit, and I really don't > need the latches. The circuit I've designed already has the > latches, I just need a high speed method of controlling > them. But on that same note, I am going to check out the > T89C51SND1 chip. The only thing that chip doesn't have on > it is an MP3 decoder, which is easily done by a VS1001K. ... actually, it does :-) ( you didn't say you needed one !) -jgArticle: 42508
Lasse Langwadt Christensen wrote: > snip > > How can it almost work, anyone with an explanation ??? > Mystery solved; It was an ES part, with the ES env variable set (can't remember the name) it works as expected. Is x2v3000bg676-5 only available as ES or did I get some left over stock?? -Lasse -- // Lasse Langwadt Christensen // Aalborg, DanmarkArticle: 42509
Even when using LVTTL, I read that Spartan-II is still 5V tolerant. What is the current drive number of the pins connected to the ISA bus? Doesn't it have to be at least 8mA? You might be saying that it is not a good idea to use 5V tolerant devices like Spartan-II for ISA bus, but if I remember correctly, most PCI-to-ISA bridges released after 1997 were 5V tolerant devices. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) Sean wrote: > > Spartan-II parts are 5V tolerant when using the PCI33_5 IO standard. >Article: 42510
Thats very courious and we've noticed a similar difference between JTAG config and xc18v04 config in our design as well. Used to work the same but not any more. Sounds like its reset related. Lasse Langwadt Christensen <langwadt@ieee.org> wrote in message news:<3CC70F1B.1B86751B@ieee.org>... > Hi, > > I've just fired up a board with a x2v3000 and some xc18v04's > > just as a go-no-go test I a very very simple design something > like; > > module test(clk,rst_b,test1,test2,test3); > > input clk,rst_b; > output [15:0] test1; > output test2; > output test2; > > reg [15:0] test_reg1; > reg test_reg2; > > assign test1 = test_reg1; > assign test2 = test_reg2; > assign test3 = clk; > > always@(posedge clk or negedge rst_b) > begin > if(!rst_b) test_reg1 <= 16'hABCD; > else test_reg1 <= 16'h0001; > end > > always@(posedge clk or negedge rst_b) > begin > if(!rst_b) test_reg2 <= 1'b0; > else test_reg2 <= ~test_reg2; > end > > endmodule > > > here's the mystery, > > If I configure the FGPA directly with JTAG everything works as expected > clk on test3, clk/2 on test2, counting on test1 > > If I put the design in flash, test3 is the clk as expected, test2 is > the clk divided by two as expected, but test1 is 16'hFFFF unless I > hit reset then test1 is 16'hABCD > > How can it almost work, anyone with an explanation ??? > > thanks, > -LasseArticle: 42511
CALL FOR PAPERS - LATE BREAKING PAPERS FOR RTC 2002 **************************************************************************** WE ARE ACCEPTING LATE BREAKING PAPERS (Complete Submission only) for the Reconfigurable Technology: FPGAs & Reconfigurable Processors for Computing and Applications. Deadline for submission of complete papers (no abstracts) is May 8th '02. Submissions are to be emailed to the Chairman of the Conference directly. jas@vcc.com **************************************************************************** Reconfigurable Technology: FPGAs & Reconfigurable Processors for Computing and Applications (7th Year) at SPIE sponsored ITCOM 2002 29-30 July 2002, Boston MA **************************************************************************** RTC Website: http://www.vcc.com/RTC/RTC.html ITCOM Website: http://spie.org/Conferences/calls/02/itcom/confs/IT203.html INTRODUCTION: In the late 1980's, when Reconfigurable Technology (RT) was in its infancy, the largest programmable logic devices (FPGAs) had 2K gates of reconfigurable logic. Far from enough logic real-estate to build computing devices or systems. Recent advances in the manufacturing process promises 50 million gates of reconfigurable logic by 2005 at substantially lower costs. The increased gate count along with richer embedded feature sets have greatly improved the economics for using RT in the general marketplace. ASIC manufacturers are embedding reconfigurable logic into ASICs and FPGA manufacturers are embedding Hard Cores into FPGAs. The design tools and system platforms for ASICs and FPGAs are merging. Furthermore, embedding processors in FPGAs as either hard cores or as soft macros leads to many new target applications, as well as many new design and tool challenges. Toolmakers are actively building high-level compilers for hardware design implementation based upon the C and Java programming languages to make system programming easier. These factors have added to the acceleration of the commercial use for reconfigurable technology and their applications. PURPOSE: To bring together researchers, manufacturers and users of reconfigurable technology for processors, communications, computing and applications. Contributions are solicited on all aspects of reconfigurable technologies, including but not limited to: 1) processors, devices and systems 2) tools and techniques 3) applications & designs 4) commercial implementations The conference will present papers that illustrate applications and techniques for using reconfigurable technology in both design and production cycles. Papers relating to the following areas are solicited: · RT-based communications & networking applications · Field programmable devices & reconfigurable processors · Adaptive computing systems and architectures · Programming tools and methodologies · Applications utilizing RC Technologies Conference Chairs: John Schewel, Virtual Computer Corp.; Philip James-Roxby, Xilinx Inc.; John T. McHenry, National Security Agency, Herman Schmit, Carnegie Mellon University IMPORTANT DATES: Conference Dates: 29 July - 30 July 2002 Late Submissions Due Date: 8 May, 2002 Manuscript Due Date: 13 May, 2002 SUBMIT ABSTRACT DIRECTLY John Schewel Chairman: jas@vcc.com ****************************************************************************Article: 42512
Kevin Brace wrote: > > Even when using LVTTL, I read that Spartan-II is still 5V tolerant. > What is the current drive number of the pins connected to the ISA bus? > Doesn't it have to be at least 8mA? > You might be saying that it is not a good idea to use 5V tolerant > devices like Spartan-II for ISA bus, but if I remember correctly, most > PCI-to-ISA bridges released after 1997 were 5V tolerant devices. > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) > > Sean wrote: > > > > Spartan-II parts are 5V tolerant when using the PCI33_5 IO standard. > > I hope I have not made a significant mistake. Yes, I see what is wrong. I am referring to the XC2SxxE chips running from 1.8 volts. This thread is about the XC2Sxx chips running from 2.5 volts... never mind. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 42513
I theory this is very straightforward, so I knocked together a quick Windows program with the MS TreeView control. Really amusing timing. The program could read and (sort of) parse a multi-megabyte EDIF file in a few seconds, but the TreeView took absolutely ages to build and draw. I guess Micro$oft designed their control to display a few hundred files, not a million or so EDIF nodes. Then they delegated the programming of the control to someone who slept through the data structures class. Good luck with the hunt. Pls post if you find something. Gunther May wrote: > Hello FPGA experts, > > does anybody know a freeware graphic EDIF viewer? > > Thank you very much, > Gunther May > >Article: 42514
We have a few experimental points... For general purpose DSP, the 2MBit on the SHARC was viewed as inadequate for many applications. Not enough space for the debugger+application. Others can say how the TI memory options work out. OTOH, the transputer had 4KBytes per processor, and lots of applications used these (in arrays) with little or no external memory. Of course the transputers had a very capable ROM'd executive and hardware support for processor-to-processor links. My view is that the X&A architects should look closely at the successes (and eventual dramatic failure) of the transputer boys and girls. Are ST still advertising for FPGA architects? For a current data point (this morning's announcement in one of the comics), the Hitachi SH7290, which does JPEG, MPEG-4, MP3, Linux, and WinCE, has 128KByte on-chip, plus a 32K cache. And I guess the top end per processor, for the next few years, is the 16MBytes (128Mbit) at which the Linux MCMs seem to have settled. My guess is that for the sort of applications at which the killer FPGA matrix excels a reasonable allowance is 32Kbyte per processor, plus anything needed by a big executive, plus application-specific memory. And an application which cannot be rearranged to use a massive array should be approacched cautiously. Another cut at this can be formed by browsing fpgacpu.org, where Jan is proposing hundreds of processors per FPGA. The record I have seen (not on fpgacpu.org) is over 800 processors in one of the big Virtex-EM parts. Three processors per block RAM - giving some pretty severe limitations on control flow changes. The design was fractionally application-specific :) HTH Austin Lesea wrote > Tim, > > Aw, come on. Be serious for a moment. > > Is 2 Mbytes enough for video, or is that just not even close for > something like a high performance MPEG4 coder? Is 1 Mbyte enough for a > packet processor? What if you are using a 405PPC? How much code space > do you need for a control program? For a DSP support program (with all > of the hard stuff in the FPGA like the FFT cores, etc.)? > > If you look at SDRAM prices, are you willing to pay twice the commodity > price in an FPGA? Three times? How much is it worth to you? > > I already know that programs grow to fit the available memory space, and > that data grows to fill the disk..... > > Austin > > Tim wrote: > > > Austin Lesea wrote > > > > > How much RAM is enough? > > > > Dorothy Parker isn't always quoted in full, but as the lady said: > > "you cannot be too thin or too rich, or have too much RAM" > > > > Maybe 640K would be enough :-) > > > > Of course, almost any on-chip RAM hugely increases the bandwidth > > compared with off-chip memory, so we immesurably better off than > > we were five years ago. >Article: 42515
Hi, I noticed that Xilinx is claiming on their website that they have a Vertex II PRO with a 3.125 Gbps Transceiver and up to 4 IBM PowerPC Processors? Can you actually get silicon for this or is this just Marketing BS? (do not e-mail me.. just post here) >Hideout<Article: 42516
"ybc" <ybc@ms4.hinet.net> wrote in message news:<a9p7pg$dvm@netnews.hinet.net>... > right to big > > "Phil Connor" <p.connorXXX@optionYYY.com> > ???????:a535fee1911fb52170c541c52125287d.58911@mygate.mailgate.org... > > I'm using ModelSim XE. > > > > On starting the simulation it goes through all the loading up > > process OK and then closes with the message below :- > > > > > > Internal error : bad pointer access ........... Closing vsim > > vsim is exiting with code 11 > > Trouble with peer processes (0), exiting. > > > > Anybody seen/solved this one. > > > > Maybe my design is to big for XE at 27k statements??? Would it > > bomb out in this way? > > > > Thanks ! > > > > Phil > > > > PS. > > > > Why don't software packages give a website reference to a list > > of error messages with a longer and less cryptic explantation > > of what the error message means. > > > > eg. "Error Code 1175 see www.mentor....." > > > > > > -- > > Posted via Mailgate.ORG Server - http://www.Mailgate.ORG Hi, I am using Modelsim 5.6 and it crashes with the same error... are you by chance using a permenent licese key? >Hideout<Article: 42517
Jay wrote: > > Read below... > > Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3CC57702.2620F2DB@xilinx.com>... > > Jay, > > > > How much RAM is enough? > > About 8Mbits are required. > > > Is the 405PPC core in Virtex II Pro fast enough (>300 MHz)? On the subject of on-chip memory, I see the Intel Madison info specs 6M BYTES of Cache ! ( 48 MBits ) - no clock speed info yet Milestone: This chip has more in the cache, than IBMs first PC hard drive ! -jgArticle: 42518
Austin Lesea wrote: > rickman wrote: > > > Austin, > > > > I think you need to read the original post more carefully. He is not > > working with a 1 MHz clock, it is an 11 MHz clock. > > OK. Still no reason for a DLL. > > > The other clock is > > either 4 MHz or 4 GHz depending on if he is using the comma as a decimal > > point or as a thousands marker. I find that whole comma vs. period > > thing very confusing. How did we get to a state where half the > > technical world uses an opposite notation from the other half? > > And how many miles per gallon does your car get? I am lost. What are you trying to say??? > If it is 4 GHz, then I can't help at all. If it is 4 MHz, it is no > different that 1 or 11 MHz. I agree, but my point is that it is not clear. > > But even if he is working with a 1 MHz clock, how does that eliminate > > the need for clock deskewing? If he has a minimum hold time that is not > > met without the clock deskewing, then he will need to use it. > > Well, he can use the time honored techiques of using the falling edge of the > clock to sample, or some other technique that was used for thirty years > before the DLL came into being. You are assuming that he has control over all aspects of the design. He may be working with a signal that is only defined over a very small window around a single clock edge, say 2 nS setup and 1 nS hold. Of course you can start making assumptions about the nature of the setup time or hold time if you understand the other half of the circuit, but often a user has to work with a spec that gives no insight into that. > > I think he was asking for a little more info on how DLLs work, what they > > accomplish and in which situations you would want to use them. > > For that, I recommend the website, and the original Virtex DLL app note. > > > > > I personally would like to understand SpartanII clocking better. I need > > six clocks in my design and I am not sure what pins to use to assure > > that they are routed using low skew paths inside the chip. Only two of > > these clocks need the DLLs for deskewing inside vs. outside the chip. > > Well, there are only four clock resources in the chip, so two of them are > going to have be very carefully placed, perhaps even by hand. I would put > the highest frequency ones on the internal BUFG resources, and then tightly > constrain the slowest two, and then verify the results. I would use the > DLLs are requried for deskew of the highest speed clocks. I am not clear about what the four clock resources are. Are you saying that there are only four BUFGs in the Spartan II and they go hand in hand with the DLLs? > Why six clocks? Anyway to use fewer clocks and use clock enables? I once > had a design that had 10 clocks, and I had a consultant come in who reduced > that to two global clocks. All of the others went away through the use of > the clock enables on the FF's in the design. Four clocks with clock enables is not the clean approach I would like. I have a memory bus clock at 100 MHz, an MCU bus clock at 30.xxx MHz and four IO clocks at independant rates from 8 kHz to 60 MHz set according to the application which varies. Even if we use clock enables, that requires the reclocking of the data and the IO clocks would need to be distributed for the data reclocking. How would that be accommodated? Is there a way to use conventional routing and keep the skew low for a small number of clock inputs? > I know sometimes it is not possible, but this experience really opened my > eyes (E1 <> E2 asynchronous multiplexer/demultiplexer). -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 42519
Thank you very much ..
> They are both clocks, since everything with signalname'event is a clock.
> The problem is not that htey are clocks, the problem is, that you tried to
> playe one of these clock inputs to a general purpose IO.
Right !! My mistake is the use of 'event attribute: i tried to detect falling
edge of a signal using a clock attribute ... now i'm changing my code
as follow:
process(clock,p_strobe_n)
begin
if(clock'event and clock='1') then
if (p_strobe_n='0') then
byte <= p_data;
end if;
end if;
end process;
Sorry for my beginner question.
Thanks everybody.
--
Stefano Mora
email: stefano.mora@*libero.it
(remove *)
Article: 42520"Michback" <michael.kleinkes@cryptovision.com> skrev i meddelandet news:c3a560c5.0204250117.11a3db17@posting.google.com... > I want to manipulate the bitstream file for an AT40k and need to know, > how I can get more information, where the window addresses come from > and how the 4 byte data block is set, so that I can manipulate the > muxer in the logic cells. > > Thanks. > Greetings. > Michael Kleinkes Contact Atmel, Sign a Non Disclosure Agreement, and get the info ? -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden.Article: 42521
Ulf Samuelsson wrote: > > "Michback" <michael.kleinkes@cryptovision.com> skrev i meddelandet > news:c3a560c5.0204250117.11a3db17@posting.google.com... > > I want to manipulate the bitstream file for an AT40k and need to know, > > how I can get more information, where the window addresses come from > > and how the 4 byte data block is set, so that I can manipulate the > > muxer in the logic cells. > > > > Thanks. > > Greetings. > > Michael Kleinkes > > Contact Atmel, Sign a Non Disclosure Agreement, and get the info ? Are there any free vhdl tools for the AT40k series?Article: 42522
Ah... herein lies the problem... as mentioned in my original post, I am using a Spartan II (200k). Hence the need to design one from scratch. adrian > Adrian, > > The DFS in Virtex II or II Pro can provide an output that is M/D times the > input. > > For example, you could multiply the 5 MHz input by fifteen over one, to get 75 > MHz as an output frequency. The jitter will be: 0.89 ns Peak to peak, (6.7%) or > less. This is from our jitter calculator that predicts the worst case output > jitter of the DFS CLKFX output. Number above is for Viretx II, Virtex II Pro > might be less (the predictor program is just being finished now). > > Ultimately, you would want to clean up the jitter of the DDFS output, which > could be done by the ICS 8745 part. > > http://www.icst.com/pdf/ics8745.pdf > > This reduces the jitter by a factor of ~ 15 to 1. For even more jitter > reduction, a VCXO would have to be used (need long time constants and stable > oscillator). > > Austin > > Noddy wrote: > > > Thanks for the reply, Austin, > > > > Using an external PLL together with a VCO would multiply my frequency up. > > However, is it possible to multiply this frequency up internally? Or am I > > missing something here. > > > > Adrian > > > > > Noddy, > > > > > > To use a DDFS, you need 2 X the highest output frequency as the input > > > frequency. I would take the 5 MHz maser, multiply it up externally with a > > PLL > > > to > 100 MHz, and then run the DDFS with that. You also may have to > > filter the > > > 1/CLK jitter from the DDFS output, and another PLL that is 1:1 will do > > that > > > fine. > > > > > > Or, you can synthesize a 2 MHz output with your 5 MHz clock, and run it to > > a PLL > > > that is 1:16 to get your 32 MHz AND filter the jitter at the same time. > > > > > > For ultra low jitter and stability, I would use a VCXO as part of the PLL > > doing > > > the filtering. > > > > > > I designed GPS Stratum 1 clock sources for 12 years, and that is how I did > > it. > > > Note I have the patent on the techniques, so be sure to read the patent > > and do > > > it differently (not hard to do), or license it from my former employers. > > > > > > Austin > > > > > > Noddy wrote: > > > > > > > I suppose maybe I should've been a bit clearer. If I am correct in > > saying, a > > > > DDFS will generate digital values for a synthesised waveform, to be used > > as > > > > input into a DAC. What I need is to generated a square wave output at a > > > > given frequency, using the 5MHz signal as a reference... ideally i am > > trying > > > > to generate a 32MHz signal. > > > > > > > > Noddy > > > > > > > > > Noddy, > > > > > > > > > > Use a DDFS (direct digital frequency Synthesizer). > > > > > > > > > > Austin > > > > > > > > > > Noddy wrote: > > > > > > > > > > > Hi, > > > > > > > > > > > > I am trying to design a high precision (30 bit) frequency > > synthesiser > > > > inside > > > > > > a Spartan II. Of course, normal way to do this is with a charge > > pump, > > > > > > voltage controlled oscillator and a phase lock loop. > > > > > > > > > > > > Can anyone point me to some good references? I have a very high > > > > precision > > > > > > 5Mhz which is generated from a hydrogen maser and will be used as > > the > > > > input > > > > > > clock signal. > > > > > > > > > > > > thanks > > > > > > adrian > > > > > > > > >Article: 42523
1. use rising_edge().
2. p_strobe_n is not needed in the sensitivity list.
3. comp.lang.vhdl is the right place for VHDL discussions
process (clock)
begin
if rising_edge(clock) then
if (p_strobe_n='0') then
byte <= p_data;
end if;
end if;
end process;
Stefano M wrote
> Thank you very much ..
>
> > They are both clocks, since everything with signalname'event is a clock.
> > The problem is not that htey are clocks, the problem is, that you tried to
> > playe one of these clock inputs to a general purpose IO.
>
> Right !! My mistake is the use of 'event attribute: i tried to detect falling
> edge of a signal using a clock attribute ... now i'm changing my code
> as follow:
>
> process(clock,p_strobe_n)
> begin
> if(clock'event and clock='1') then
> if (p_strobe_n='0') then
> byte <= p_data;
> end if;
> end if;
> end process;
Article: 42524From the current ESNUG... The FPGA connection is that 'FPGA weenies' are truly envious of software which needs 8GByte :-) / From: Bob Alverson <bob@........> / / Hey, John, / / I just had to share with you that the Synopsys R&D Q&A in ESNUG 392 #5 / was classified by our e-mail filters here at Cray as spam. The kicker / is it claims the Synopsys people were writing about penis enlargement! / / X-Cray-SpamScore: 4.2 / X-Cray-SpamSigns: PENIS_ENLARGE2 / / What triggered it was: / / 47. I've noticed that the Design Compiler budgeter uses 8G of / memory on a 400 K design, versus 1G with the PrimeTime / budgeter. Is this normal? / / No. Design Compiler budgeter offers many advantages for synthesis / (faster, accuracy, RTL budgeting, and so on). However, it might / require more memory for some designs. For large designs a 50 percent / increase in memory might be normal, but an 8x increase is definitely / not normal and should be reported. / / Our spam detector is primative; the two uses of the word "increase" in / the same line is assumed to be talking about penis enlargement. But it / also wouldn't surprise me to discover that Synopsys Marketing was using / subliminal techniques to sell more copies of DC. :) / / - Bob Alverson / Cray Computers Seattle, WA
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