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"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> schrieb im Newsbeitrag news:b0o9nh$su0$1@news.tu-darmstadt.de... > Does anybody succeed in coercing Webpack to use unbonded pads on the XC95 > CPLD family for such a task. How do I code it, what constraints need to be > given? Use the chip with all IOs bonded and adjust your pin constraints. Depending on how smart the unbonded pins are handled by xilinx, this more or less difficult. -- MfG FalkArticle: 51851
> B. Joshua Rosen <bjrosen@polybus.com> wrote: > >TECO wsa great. For those of you too young to remember it, TECO was a > >line editor that was the grandfather of today's EMACS. All of the > >commands in TECO were control characters I'm not sure that's right. IIRC most TECO commands were single printable characters, some of which expected arbitrary text to follow them; you terminated the arbitrary text with the ESCape key. After you had written a few lines of this gibberish, you could hit ESC twice and the whole disgusting mess would execute. It was a standing joke to guess what would happen if you typed your own name into TECO. It may be (though memory is very flaky at around 25 years' remove) that there were some control-character bindings to common commands. "Caleb Hess" <hess@cs.indiana.edu> wrote > My favorite from the DEC TECO manual: "MUNG - a recursive acronym for > Mung Until No Good". I don't remember what mung acually did, though. MUNG applied a TECO macro to a file. One of the things that TECO folk loved to do was to MUNG a TECO script, patching it so it did what you want, and then MUNG another file with the modified macro. Structured programming, eat your heart out. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 51852
B. Joshua Rosen wrote > TECO wsa great. For those of you too young to remember it, TECO was a > line editor that was the grandfather of today's EMACS. All of the > commands in TECO were control characters or a control character followed > by another character (the key bindings in EMACS are based on these > sequences). You could write large macros in TECO and save them just as > you can write GNULISP programs in EMACS today. The difference is that the > code was so cryptic that you had to get it right the first time because > even the author of the code couldn't read it. Text Editor and Corrector. Whit Diffie (the crypto guy) reputedly wrote an accounting system in TECO.Article: 51853
Hello, everyone, The xilinx website appears to be down. Anyone know the price of the lowest cost Virtex-II device, +/-10% is OK. Likewise lowest cost Stratix device. Size/speed is not important, just need the I/O capability (PECL, LVDS, etc) along with programmability. Thanks, Tim.Article: 51854
Tim At This Newsgroup <tim@thisnewsgroup.com> wrote: : Hello, everyone, : The xilinx website appears to be down. Anyone know the price of the lowest : cost Virtex-II device, +/-10% is OK. Likewise lowest cost Stratix : device. Size/speed is not important, just need the I/O capability (PECL, : LVDS, etc) along with programmability. www.nuhorizons.com has a online price and availability query. Other Xilinx distributors too... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 51855
Interesting . . .
Although the original poster claims he is a student from Hamburg,
Germany, the poster's NNTP-Posting-Host says this posting came from
proxy3.via.com.tw (61.13.36.3).
Is this poster a VIA (an x86 vendor) employee claiming to be a
student?
I don't know any free x86 processor cores available, although
there are some commercial 8086 class soft cores available.
Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)
"Michael" <mich@ael.de> wrote in message news:<b0ocbd$rjt9l$1@news.hansenet.net>...
> hi guys,
>
> i am a student in hamburg and for my final thesis i want to experiment with
> a x86 compatible processor loaded into a fpga.
>
> can anybody tell me, if there is any free x86 compatible processor core? if
> yes, where can i get it?
>
> thank you
>
> micha
Article: 51856Many thanks, Uwe, and to www.nuhorizons.com, too, of course... Prices start at 32 dollars for xc2v40 (1 off), xc2v250 is 80 dollars (1 off) - seems quite reasonable to me. On Thu, 23 Jan 2003 19:55:04 +0000 (UTC), Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: >Tim At This Newsgroup <tim@thisnewsgroup.com> wrote: >: Hello, everyone, > >: The xilinx website appears to be down. Anyone know the price of the lowest >: cost Virtex-II device, +/-10% is OK. Likewise lowest cost Stratix >: device. Size/speed is not important, just need the I/O capability (PECL, >: LVDS, etc) along with programmability. > >www.nuhorizons.com has a online price and availability query. Other Xilinx >distributors too... > >Bye >-- >Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > >Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt >--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 51857
I'm have no doubt that you instantiate dual ports using Synplify. You just can't infer them. John_H wrote: > I instantiate dual ports fine in Synplify. If you want different clock > domains or advances features, the synthesizer may fall short leaving direct > instantiation of the Xilinx primitives as a better implementation method. > If you need simple operation, the tool works fine. I can't comment about > XST either but the limitations of Synplify are reasonable. > > "name" <nospamforme@someplace.com> wrote in message > news:3E1B3B35.4000302@someplace.com... > >>Just watch out if you intend to use Synplify for DP RAM inferrence >>because it can't do it. I can't speak for the other tools >> >>Igor Orlovich wrote: >> >>>Have you tried simply following Xilinx's examples of inferring Dual Port >> > Ram > >>>instead? >>>sean da wrote: >>> >>> >>> >>>>I used Xilinx Core Generator to build simulation model for dualport >>>>Ram, and it went through the synthesis phase by XTS, but during >>>>implementation phase, I got the error message said "dualport_ram is >>>>unexpected, ....", dualport_ram is my dualport RAM name. What is the >>>>black box name should I put in my code to pass this implementation >>>>phase as well as Place/Route phase? Thanks! >>> >>> > >Article: 51858
assaf_sarfati@yahoo.com (Assaf Sarfati) wrote in message news:<44b0ca4e.0301222211.65fb7320@posting.google.com>...
> hmurray@suespammers.org (Hal Murray) wrote in message news:<v2sjnrbd1f2k3c@corp.supernews.com>...
> > Thanks.
> >
> > >* VHDL is much more strongly typed: Verilog has only some basic types
> > >and allows automatic conversion of vectors of mismatching widths. In
> > >VHDL you often need a conversion function to assign a value from one
> > >signal to another. It is a true PITA, but in a large design can save
> > >you weeks of searching for odd errors caused by automatic conversion
> > >of widths. In addition, in VHDL you can create new types of signals as
> > >needed (very common: create an enumerated type for all states in each
> > >FSM in the design or each control-signal group). Verilog will only
> > >allow you to assign names to numeric constants.
> >
> > I consider the wires/vectors sort of "type" system to be a major
> > fuckup. Note that's all you get with most schematic packages too.
> >
> > It seems really stupid and error prone to be stuffing things like
> > control signals into the back end of a vector so you can avoid
> > a major amount of clutter as a bus gets passed around.
> >
> >
> >
> > >* The other side of VHDL's strong typing is that usually VHDL
> > >simulations are slower.
> >
> > Could you please say more? I think of strong typing as a compile time
> > issue. The final circuit is going to be just wires and gates. Why
> > does it take longer to simulate if they came from one language
> > or another?
>
>
> A lot of the checking must be done at simulation time. For example:
> you have two signals, one defined as an integer range of 3 to 57 and
> the other as an integer range of 5 to 55. Every time you assign a
> value to each signal, the simulator must check if the signal is within
> the valid range FOR THIS SIGNAL, and come to a screeching halt if it
> is not.
And that's a bad thing? I mean, really.
Consider: you've got a state machine, and in one of the states, it
increments a counter. If your state machine is broken, perhaps that
counter will increment forever. With Verilog, the counter will simply
roll over, or whatever. With VHDL, with the counter implemented as an
unsigned with a specific range, once the code tries to increment past
the range, the simulator barks at you. That's a Good Thing.
> In Verilog, the simulator simply assigns a bit-vector of the
> required width and sets the value as needed. This is also why VHDL
> simulators require more memory - the data-structure representing each
> signal must contain more information.
OK, so there's some "simulation overhead." In this era of 2 GHz PCs
with a gigabyte of RAM, that's a detail.
Verilog gives you enough rope to hang yourself.
Do this comparison in verilog and tell me what you expect:
reg [1:0] foo;
if (foo == 2)
$display ("foo is two!");
else
$display ("foo ain't two!");
-a
Article: 51859
"Jeff Cunningham" <jcc@sover.net> wrote in message news:<4_RX9.69013$wQ1.3195@fe01>...
> > >* The other side of VHDL's strong typing is that usually VHDL
> > >simulations are slower.
> >
> > Could you please say more? I think of strong typing as a compile time
> > issue. The final circuit is going to be just wires and gates. Why
> > does it take longer to simulate if they came from one language
> > or another?
>
> I think he was refering to pre-synthesis simulation of the HDL design,
> before the design is synthesized to gates and wires.
>
>
> Someone earlier mentioned that there is less typing (i.e. keystrokes) with
> Verilog. While true,
Not necessarily. F'rinstance, you have a module declaration:
module foo(
clk,
reset,
bar,
bletch);
And then you have to indicate which signals are inputs and outputs:
input clk;
input reset;
input [31:0] bar;
output bletch;
And then you have to indicate if the outputs are regs or wires:
reg bletch;
That's a lot of typing.
Why not:
module foo(
input clk,
input reset,
input [31:0] bar,
output bletch);
????
> I have never understood why this is an advantage. How
> much of the design cycle is really spent pressing keys on the keyboard?
Emacs VHDL mode deals with most of the typing. Emacs Verilog mode, on
the other hand, sucks.
> On
> the other hand, the increased verbosity of VHDL makes it more readable in
> the sense that when you come back to a piece of code you wrote two years ago
> it is easier to grok what it is doing
I agree.
--a
Article: 51860"Jonathan Bromley" <jonathan@oxfordbromley.u-net.com> wrote in message news:<b0oujn$5p5$1$8300dec7@news.demon.co.uk>... > However, it's no fun if you try to be unbiased and fair all > the time. Me, I rather fancy the conspiracy theory arguing that > a large section of the engineering community will fight to the death > against any attempt to introduce clear and readable programming > languages, on the grounds that it would threaten their job > security. It's hard to think of any other reason for the > imbecilic syntax of Perl, Verilog, C++... You could include LISP in that list ...Article: 51861
In article <cc7b0b5f.0301231205.7df4346d@posting.google.com>, Kevin Brace <kevinbraceusenet@hotmail.com> wrote: >Interesting . . . >Although the original poster claims he is a student from Hamburg, >Germany, the poster's NNTP-Posting-Host says this posting came from >proxy3.via.com.tw (61.13.36.3). >Is this poster a VIA (an x86 vendor) employee claiming to be a >student? Why would VIA really care, they have their own x86 core (bought from Cyrix) which they produce: 900 MHz, 50 mm^2 die size (.18 uM process), 5 watts peak power. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51862
Patrick Twomey wrote: > I am a student and am using a Celoxica RC100 demo board as part of my > project. > > It has a Spartan II XC2S200-5-FG456 chip on it. This board is designed > to be programmed with using Handel-C. Unfortunately I do not have DK1 > the support software to use Handel-C. That surprises me - Celoxica has some reasonable deals bundling University licenses of DK1 with the RC boards. In fact, I would have thought they'd be actively encouraging a new generation of designers to "cut their teeth" on DK1 :) But anyway... > I am currently trying to write a controller in VHDL for video in via > the Philips SAA7111A Enhanced Video Input Processor (accepts S-video > or composite video as input and outputs a digital video stream). Any > assistance from someone who has used the Rc100 board previously for a > similar purpose would be greatly appreciated. Go to www.xess.com and look for the examples page, there you'll find an extended list of projects and modules that people have developed for the Xess prototyping boards. If I'm not mistaken, they use the SAA7111A in the XSV boards, and I think there's at least one demo project there which does the sort of thing you are talking about. With any luck you could have something up and running just by changing the UCF file and a bit of fiddling around the edges. Good luck, John > > Regards, > > Patrick TwomeyArticle: 51863
My apologies. "I infer them just fine." As I'm sure I stated, it's just when you go to different clocks or advanced features that the primitves are required. Otherwise, Synplify has done great with my register memory elements (e.g., reg [7:0] byte_array [511:0];). If you want distribute CLB SelectRAM, the read value can be used asynchronously. If you use BlockRAM, the output must be synchronous. Inference is fine. "Michael" <nospamforme@someplace.com> wrote in message news:3E30683F.5020209@someplace.com... > I'm have no doubt that you instantiate dual ports using Synplify. You > just can't infer them. > > John_H wrote: > > I instantiate dual ports fine in Synplify. If you want different clock > > domains or advances features, the synthesizer may fall short leaving direct > > instantiation of the Xilinx primitives as a better implementation method. > > If you need simple operation, the tool works fine. I can't comment about > > XST either but the limitations of Synplify are reasonable. > > > > "name" <nospamforme@someplace.com> wrote in message > > news:3E1B3B35.4000302@someplace.com... > > > >>Just watch out if you intend to use Synplify for DP RAM inferrence > >>because it can't do it. I can't speak for the other tools > >> > >>Igor Orlovich wrote: > >> > >>>Have you tried simply following Xilinx's examples of inferring Dual Port > >> > > Ram > > > >>>instead? > >>>sean da wrote: > >>> > >>> > >>> > >>>>I used Xilinx Core Generator to build simulation model for dualport > >>>>Ram, and it went through the synthesis phase by XTS, but during > >>>>implementation phase, I got the error message said "dualport_ram is > >>>>unexpected, ....", dualport_ram is my dualport RAM name. What is the > >>>>black box name should I put in my code to pass this implementation > >>>>phase as well as Place/Route phase? Thanks! > >>> > >>> > > > > >Article: 51864
Michael wrote: > hi guys, > > i am a student in hamburg and for my final thesis i want to experiment with > a x86 compatible processor loaded into a fpga. > > can anybody tell me, if there is any free x86 compatible processor core? if > yes, where can i get it? > > thank you > > micha > > www.opencores.org is a good starting point, i think...Article: 51865
On 23 Jan 2003 14:19:34 -0800, Andy Peters <Bassman59a@yahoo.com> wrote:
>
>Why not:
>
>module foo(
> input clk,
> input reset,
> input [31:0] bar,
> output bletch);
>
>????
Why indeed? This would be my number one request for the
language standards body. The C language made this transition
what, 15 years ago? And of course, VHDL is just as deficient
in this respect.
- Larry
Article: 51866I asked: > What's a "D-MIPS"? The Xilinx press release for their Virtex-IIE > Multimedia development board says that the MicroBlaze running at > 150 MHz delivers 102 D-MIPS. nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) writes: > Probably Dhrystone Mips, aka Bogomips. Sure would have been more convenient if they'd just called it that. Sigh.Article: 51867
because i just do an internship at via. miach "Kevin Brace" <kevinbraceusenet@hotmail.com> wrote in message news:cc7b0b5f.0301231205.7df4346d@posting.google.com... > Interesting . . . > Although the original poster claims he is a student from Hamburg, > Germany, the poster's NNTP-Posting-Host says this posting came from > proxy3.via.com.tw (61.13.36.3). > Is this poster a VIA (an x86 vendor) employee claiming to be a > student? > I don't know any free x86 processor cores available, although > there are some commercial 8086 class soft cores available. > > > Kevin Brace (If someone wants to respond to what I wrote, I prefer if > you will do so within the newsgroup.) > > > > "Michael" <mich@ael.de> wrote in message news:<b0ocbd$rjt9l$1@news.hansenet.net>... > > hi guys, > > > > i am a student in hamburg and for my final thesis i want to experiment with > > a x86 compatible processor loaded into a fpga. > > > > can anybody tell me, if there is any free x86 compatible processor core? if > > yes, where can i get it? > > > > thank you > > > > michaArticle: 51868
Roger wrote > Which one is the "best"? > > What are the various advantages and disadvantages of each one? FPGA design is harder than ASIC design. You need the extra control given by the 'first class' attributes in VHDL. IMHO.Article: 51869
> Well, if the schematics offer standard blocks like registers, multifunction > combinatorial logic, FSM's, RAM's, ROM's, FIFO's, LIFO's, CAM's, sub- > schematics, stacks of identical sub-schematics - then I think you have to > figure out much *less* than using HDL's and you can concentrate upon the > actual architecture you're designing. Exactly, and I've been doing exactly that for over ten years for my FPGA designs, as have others here. The problem was the vendors were pushing the HDL tool flow, and just when schematics were starting to actually get some good support, the plug was, for the most part, pulled... > Forget about schematics to draw gates and FF's or even SSI/MSI components - > they're at a too low level of abstraction for today's complex designs. Exactly, and with schematics, as well as HDLs if you do a good hierarchical design, that should be inherent in your design methodology. > Oh, and the fact that so many books are written on HDL's to make you an > 'expert' - doesn't that say that they are darn hard to use correctly and > efficiently ?-) Agreed, but you can learn just enough to think you know what you are doing...which for some makes them dangerous ;-) Regards, AustinArticle: 51870
On Fri, 24 Jan 2003 00:09:19 +0000 (UTC), ldoolitt@recycle.lbl.gov (Larry Doolittle) wrote: >On 23 Jan 2003 14:19:34 -0800, Andy Peters <Bassman59a@yahoo.com> wrote: >> >>Why not: >> >>module foo( >> input clk, >> input reset, >> input [31:0] bar, >> output bletch); >> >>???? > >Why indeed? This would be my number one request for the >language standards body. The C language made this transition >what, 15 years ago? And of course, VHDL is just as deficient >in this respect. > > - Larry Actually your wish has been granted recently. Verilog 2001 includes this feature. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 51871
> FlexLM, at least some versions of it, store a special sequence in disk sector > lba 0x20 (dec 32) of the boot harddrive. This is an unused area on all > harddrives larger than 8GB. Hum. Sorry to be cynical, but, it sounds like SOMEONE DOES use it...and if one uses it, and thinks they are the only one using it, and then someone else gets the bright idea to use it...then there is certainly a problem. Doing "things" like this is how problems are created... AustinArticle: 51872
Hi all Anbody familier with the implementation of AES(Rijindal) --- CTR with CBC MAC in FPGA ( a C implementation can be found at http://fp.gladman.plus.com/cryptography_technology/ccm/index.htm ) I have certain quries about the implementation of a block cipher How the implemetation can be tested ? (a sample test setup) How the perfomance ie throughput,latency etc can be measured? With regards geekoArticle: 51873
Hi, I am a newbie in Virtex.I found in Virtex the RAM can be LUT,RAM and ROM,what's the difference between these three? Thank you very much! sincerely ------------- Kuan Zhou ECSE departmentArticle: 51874
Hi all
I have a problem with developing a AES core with AMBA AHB interface
for programming and data access.I am new to AMBA and AHB.Anybody familiar
with the implementation of AMBA AHB compliant cores.Any documentation
available
Thanks in advance
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