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I wrote: > Well, don't keep us in suspense. Tell us what manual it is. I'd like > to see for myself this manual that allows one to predict what code will > be generated from an arbitrary C function. "Austin Franklin" <austin@da98rkroom.com> wrote: > It's not arbitrary, it's entirely deterministic. That's the POINT! I wrote: > No, the point was that I should be able to take any arbitrary C code > of my choosing, and use that book to determine what code the compiler > will generate. Austin wrote: > Er, Eric, that IS what deterministic means. Same input always generates > same output. Yes, so my choice of an arbitrary C function to use as an example doesn't make the process non-deterministic.Article: 51826
Andrew Rogers <andrew@rogerstech.co.uk> writes: > I discovered the problem when I ran XST on Linux using Wine. First I > set the XILINX variable David Rogoff <david@therogoffs.com> writes: > Why don't you run the Linux version? Because there *isn't* a native Linux version yet, is there? I thought 4.2i and 5.1i only supported Linux via the use of Wine. I've been hoping that 5.2i, reportedly due to be released in February, will include a native Linux release. I just tried to look at the Xilinx web site to confirm, but I can't get to it. Both of the DNS servers that are supposed to be authoritative for xilinx.com are unreachable. :-( Domain servers in listed order: DBRU.BR.NS.ELS-GMS.ATT.NET 199.191.128.106 DMTU.MT.NS.ELS-GMS.ATT.NET 12.127.16.70 I recommend to my own customers to have multiple name servers, not all of which are provided by the same entity, in order to avoid exactly this sort of problem.Article: 51827
Eric Smith <eric-no-spam-for-me@brouhaha.com> writes: > I just tried to look at the Xilinx web site to confirm, but I can't get > to it. Both of the DNS servers that are supposed to be authoritative > for xilinx.com are unreachable. :-( They're back. The feature support summary for ISE Foundation 5.1i says that the platforms are PC, Sun Solaris, Linux (with WINE). The 19-Feb-2001 press release for Linux suport debuting in 4.2i stated "with later versions of ISE moving to native Linux in 2003." It didn't give a specific target though, so it's uncertain whether 5.2i will have native Linux support, but we can hope. The web site says 5.2i is scheduled for release on 20-Feb-2003. I'd keep my fingers crossed, but I know that it's bad luck to be superstitious.Article: 51828
What's a "D-MIPS"? The Xilinx press release for their Virtex-IIE
Multimedia development board says that the MicroBlaze running at
150 MHz delivers 102 D-MIPS.
http://www.xilinx.com/prs_rls/silicon_vir/0311v2_multi.htm
Article: 51829
John Providenza wrote:
> I'm trying to use a Spartan 2 device with more than 4 external
> clocks and am running into the following error message from the
> Xilinx tools:
>
> ------------
> ERROR:MapLib:94 - The design contains more than 4 GCLKIOBs. The maximum number
> of GCLKIOBs in this device is 4. Please correct the design.
> Errors found during the mapping phase. Output files will not be written.
> ------------
>
> I'm using the Xilinx WebPACK tools (I believe version 4.1). The code
> is Verilog using the Xilinx XST synthesizer.
In VHDL, for the signals that are not going to use BUFGs you add:
attribute clock_buffer: string;
attribute clock_buffer of signal_name: signal is "ibuf";
Presumably there is a similar thing for Verilog.
--
My real email is akamail.com@dclark (or something like that).
Article: 51830In article <qhptqoha5m.fsf@ruckus.brouhaha.com>, Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote: >What's a "D-MIPS"? The Xilinx press release for their Virtex-IIE >Multimedia development board says that the MicroBlaze running at >150 MHz delivers 102 D-MIPS. Probably Dhrystone Mips, aka Bogomips. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51831
Dhrystone MIPS - Dhrystone is a benchmark program written in C, or Java that tests a system's integer performance. The objective is to compare the performance of a machine against the performance of a reference machine. The industry has adopted the VAX 11/780 as the reference 1 MIPS (Million Instruction Per Second) machine. Above is taken from http://www.xilinx.com/ipcenter/processor_central/embedded/processor_glossary .pdf --Neeraj "Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message news:qhptqoha5m.fsf@ruckus.brouhaha.com... > What's a "D-MIPS"? The Xilinx press release for their Virtex-IIE > Multimedia development board says that the MicroBlaze running at > 150 MHz delivers 102 D-MIPS. > > http://www.xilinx.com/prs_rls/silicon_vir/0311v2_multi.htmArticle: 51832
hmurray@suespammers.org (Hal Murray) wrote in message news:<v2sjnrbd1f2k3c@corp.supernews.com>... > Thanks. > > >* VHDL is much more strongly typed: Verilog has only some basic types > >and allows automatic conversion of vectors of mismatching widths. In > >VHDL you often need a conversion function to assign a value from one > >signal to another. It is a true PITA, but in a large design can save > >you weeks of searching for odd errors caused by automatic conversion > >of widths. In addition, in VHDL you can create new types of signals as > >needed (very common: create an enumerated type for all states in each > >FSM in the design or each control-signal group). Verilog will only > >allow you to assign names to numeric constants. > > I consider the wires/vectors sort of "type" system to be a major > fuckup. Note that's all you get with most schematic packages too. > > It seems really stupid and error prone to be stuffing things like > control signals into the back end of a vector so you can avoid > a major amount of clutter as a bus gets passed around. > > > > >* The other side of VHDL's strong typing is that usually VHDL > >simulations are slower. > > Could you please say more? I think of strong typing as a compile time > issue. The final circuit is going to be just wires and gates. Why > does it take longer to simulate if they came from one language > or another? A lot of the checking must be done at simulation time. For example: you have two signals, one defined as an integer range of 3 to 57 and the other as an integer range of 5 to 55. Every time you assign a value to each signal, the simulator must check if the signal is within the valid range FOR THIS SIGNAL, and come to a screeching halt if it is not. In Verilog, the simulator simply assigns a bit-vector of the required width and sets the value as needed. This is also why VHDL simulators require more memory - the data-structure representing each signal must contain more information.Article: 51833
Austin Lesea <austin.lesea@xilinx.com> writes: > How much jitter is on the incoming clock? Peak to peak? How > measured? (LeCroy scope best way, plain scope can be 30% less jitter > than actually there as they can't sample enough clocks to measure, and > delaying the trigger to "catch" jitter is a really bad way to see > jitter!) Just out of interest - is there any feature a LeCroy scope has that a Tektronix one, for example, doesn't that makes jitter measurement easier/better? Cheers, MartinArticle: 51834
Hallo, well, I know, using delays generated by signals going through logic is bad. However I would like to insure that a pulse has a certain length before I react on the trailing edge. Feeding the delayed puls to Clock Enable and the undelayed pulse to clock can achieve that task. One way to generate a delay is feeding the signal to an IO Pad and reading back the Pad value via the IO buffer. All bonded IO resources are already allocated to external signals in my design. Does anybody succeed in coercing Webpack to use unbonded pads on the XC95 CPLD family for such a task. How do I code it, what constraints need to be given? I've tried a lot of things, to no avail so far. Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 51835
hi guys, i am a student in hamburg and for my final thesis i want to experiment with a x86 compatible processor loaded into a fpga. can anybody tell me, if there is any free x86 compatible processor core? if yes, where can i get it? thank you michaArticle: 51836
Hi all is it possible to use impact on a SUN/Solaris to download bit files over a parallel cable? the GUI only shows me serial connections? br ThomasArticle: 51837
> I've heard of that, but didn't know that you can delete that sector. Which > tool (disc sector editor) do you use ? WinHex (for example) is able to edit disk sectors.Article: 51838
Thomas Buerner <buerner@lrs.eei.uni-erlangen.de> wrote: : Hi all : is it possible to use impact on a SUN/Solaris to : download bit files over a parallel cable? : the GUI only shows me serial connections? Not to my knowledge with the Xilinx tools. I use naxjp http://member.nifty.ne.jp/nahitafu/naxjp/naxjp-e.html to download to XC95 and XC18. Somehow experimental, but its works. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 51839
I am a student and am using a Celoxica RC100 demo board as part of my project. It has a Spartan II XC2S200-5-FG456 chip on it. This board is designed to be programmed with using Handel-C. Unfortunately I do not have DK1 the support software to use Handel-C. As a result I am using VHDL to program the FPGA. I have succesfully written a VHDL controller for video out from the fpga via a 24-bit Video DAC connected to a VGA connector for display on a monitor. I am currently trying to write a controller in VHDL for video in via the Philips SAA7111A Enhanced Video Input Processor (accepts S-video or composite video as input and outputs a digital video stream). Any assistance from someone who has used the Rc100 board previously for a similar purpose would be greatly appreciated. Regards, Patrick TwomeyArticle: 51840
I'm working a design on Xilinx VirtexII There are many warnings in the map report like: WARNING:Pack:266 - The function generator Mmux__n0067_inst_lut3_7561 failed to merge with F5 multiplexer MUXF5.I1. The design will exhibit suboptimal timing. The design was synthesized by XST. What's the reason and how to resolve them? Thanks for any advance.Article: 51841
> >* The other side of VHDL's strong typing is that usually VHDL > >simulations are slower. > > Could you please say more? I think of strong typing as a compile time > issue. The final circuit is going to be just wires and gates. Why > does it take longer to simulate if they came from one language > or another? I think he was refering to pre-synthesis simulation of the HDL design, before the design is synthesized to gates and wires. Someone earlier mentioned that there is less typing (i.e. keystrokes) with Verilog. While true, I have never understood why this is an advantage. How much of the design cycle is really spent pressing keys on the keyboard? On the other hand, the increased verbosity of VHDL makes it more readable in the sense that when you come back to a piece of code you wrote two years ago it is easier to grok what it is doing (at least this is what I have been told by people who are experts in both languages - I must confess I only know VHDL). -JCArticle: 51842
"Jeff Cunningham" <jcc@sover.net> wrote > Someone earlier mentioned that there is less typing (i.e. keystrokes) with > Verilog. While true, I have never understood why this is an advantage. How > much of the design cycle is really spent pressing keys on the keyboard? On > the other hand, the increased verbosity of VHDL makes it more readable in > the sense that when you come back to a piece of code you wrote two years ago > it is easier to grok what it is doing (at least this is what I have been > told by people who are experts in both languages - I must confess I only > know VHDL). Personally I heartily agree, though there are real benefits and real drawbacks to both languages. As Janick Bergeron has wisely pointed out, the one you like most is the one you're not using at the time. However, it's no fun if you try to be unbiased and fair all the time. Me, I rather fancy the conspiracy theory arguing that a large section of the engineering community will fight to the death against any attempt to introduce clear and readable programming languages, on the grounds that it would threaten their job security. It's hard to think of any other reason for the imbecilic syntax of Perl, Verilog, C++... and if you're of a certain age and you want proof positive of this theory, just look at TECO and APL. (No, I didn't make them up!) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 51843
On Thu, 23 Jan 2003 09:35:26 -0500, Jonathan Bromley wrote: > "Jeff Cunningham" <jcc@sover.net> wrote > >> Someone earlier mentioned that there is less typing (i.e. keystrokes) >> with Verilog. While true, I have never understood why this is an >> advantage. How much of the design cycle is really spent pressing keys >> on the keyboard? On the other hand, the increased verbosity of VHDL >> makes it more readable in the sense that when you come back to a piece >> of code you wrote two years > ago >> it is easier to grok what it is doing (at least this is what I have >> been told by people who are experts in both languages - I must confess >> I only know VHDL). > > Personally I heartily agree, though there are real benefits and real > drawbacks to both languages. As Janick Bergeron has wisely pointed out, > the one you like most is the one you're not using at the time. > > However, it's no fun if you try to be unbiased and fair all the time. > Me, I rather fancy the conspiracy theory arguing that a large section of > the engineering community will fight to the death against any attempt to > introduce clear and readable programming languages, on the grounds that > it would threaten their job security. It's hard to think of any other > reason for the imbecilic syntax of Perl, Verilog, C++... and if you're > of a certain age and you want proof positive of this theory, just look > at TECO and APL. (No, I didn't make them up!) -- Jonathan Bromley, > Consultant > TECO wsa great. For those of you too young to remember it, TECO was a line editor that was the grandfather of today's EMACS. All of the commands in TECO were control characters or a control character followed by another character (the key bindings in EMACS are based on these sequences). You could write large macros in TECO and save them just as you can write GNULISP programs in EMACS today. The difference is that the code was so cryptic that you had to get it right the first time because even the author of the code couldn't read it. APL was similar. In APL you could write a very powerful program in a single line of code but no human could read it.Article: 51844
In <b0ocbd$rjt9l$1@news.hansenet.net> Michael wrote: > i am a student in hamburg and for my final thesis i want to > experiment > with a x86 compatible processor loaded into a fpga. > > can anybody tell me, if there is any free x86 compatible processor > core? if yes, where can i get it? while I don't know about any free x86 cores out there, I have the following comments: * x86 is not too well suited for FPGA implementations. Most FPGA-based system-on-chip designs use proprietary RISCs, e.g. Xilinx MicroBlaze. * if you are looking for industry contacts and somebody to guide you through your thesis, drop me a mail or meet me at TUHH. Best regards FelixArticle: 51845
Thanks to everyone for the input. After working with xilinx tech support, we seem to have come to a solution. In the design, I have three different clock inputs, each going to a DCM with variable phase shifting enabled. After configuration, these DCM's are shifted to provide enough setup time on several clock forwarded interfaces. It appears that xilinx has noticed problems when attempting to use variable phase shift DCM's with high input clock frequencies (> 200 MHz). The fix is to use a bitgen option that sets the centerpoint of the DCM from tap 64 to tap 0. According to xilinx, each tap in the delay path adds some additional rise/fall skew resulting in duty cycle distortion. By setting the center point to tap 0, 64 taps are removed from the delay line reducing the distortion. This change does appear to have solved my problem, although further testing is needed to make absolutely sure. John Ray Andraka <ray@andraka.com> wrote in message news:<3E2EEB6E.388602FB@andraka.com>... > John, > > Try bringing the clock back out of a package pin and look at the jitter on the internal clock. I had > a case a couple years ago where single ended outputs switching on the same bank as the clock input > caused the clock input threshold to modulate, adding jitter to the clock. There was enough jitter > added that the DLL was coming unlocked. While that was in a Virtex part, the same effect can be seen > on a Spartan part. If you have the spare pins, put a virtual ground on either side of the clock pin > (drive a low out, and tie the pin to hard ground). Check to make sure your clock trace isn't picking > up crosstalk from other traces on the board (that also adds jitter). If possible, move the I/O off > the bank with the clock input altogether. You might also try reducing the drive strength and slew > rate of those outputs. > > John M wrote: > > > I do have a case open with xilinx, and I have gone through all of the > > steps you mention below. I have taken steps to make sure both Vcco > > and Vccaux are within spec. I have also added separate decoupling on > > each power pin. The ground bounce is currently withing reasonable > > values, 60 mV peak-to-peak. I am suspect of the package, and just > > wanted to see if anyone else has similar problems with it. > > Unfortunately, the 500 does not come in a flip-chip package, and it > > would not be cost effective to move to a larger part (although this > > may be the end result). Thanks for the suggestions. Anyone else out > > there successfully use this package with a large percentage of the I/O > > utilized? > > > > John > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 51846
Eduardo, Do you have modular design flow enabled? 5.1i and prior software requires the Modular flow to be unlocked by files. I've run through the design without any problem. Regards, Wei "Eduardo Wenzel Brião" wrote: > Did somebody already work with XAPP 290 example (xapp290.zip)?? > > I tried to run modular design flow to use partial reconfiguration. But > when I execute run_flow.bat file from XAPP290 example (CALCPR10 > design) at once, it happens errors in UCF file (calctop.ucf). This > erros are related when NGDBUILD command is executed. > > There are errors on the INST tags on the UCF file (INST > DisplayLCD/Internal_GND issued errors on the NGBuild command) > > If somebody already worked with this example, I´d like ideas to > continue to run modular design flow for partial reconfiguration. > > Regards > > Eduardo Wenzel BriãoArticle: 51847
Thomas Buerner <buerner@lrs.eei.uni-erlangen.de> writes: > is it possible to use impact on a SUN/Solaris to > download bit files over a parallel cable? > the GUI only shows me serial connections? I've used the MultiLINX/serial cable under Solaris. I think this is the only supported programming device available under Solaris. I don't know about the new MultiPRO. However, you can generate SVF files under Solaris and use a third party JTAG programmer or similar. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 51848
Duane Clark <junkmail@junkmail.com> wrote in message news:<3E2F56BC.8020507@junkmail.com>... > John Providenza wrote: > > I'm trying to use a Spartan 2 device with more than 4 external > > clocks and am running into the following error message from the > > Xilinx tools: > > > > ------------ > > ERROR:MapLib:94 - The design contains more than 4 GCLKIOBs. The maximum number > > of GCLKIOBs in this device is 4. Please correct the design. > > Errors found during the mapping phase. Output files will not be written. > > ------------ > > > > I'm using the Xilinx WebPACK tools (I believe version 4.1). The code > > is Verilog using the Xilinx XST synthesizer. > > In VHDL, for the signals that are not going to use BUFGs you add: > attribute clock_buffer: string; > attribute clock_buffer of signal_name: signal is "ibuf"; > > Presumably there is a similar thing for Verilog. Duane - Thanks for the tip. Here's what I've found (for Verilog & XST) 1) to route a general purpose pin onto a global clock line: // a) tell Xilinx to bring the signal in with a normal buffer // synthesis attribute clock_buffer clk_on_gp_pin ibuf; input clk_on_gp_pin; wire clk_as_global_clock // b) use a magic XIlinx buffer to get the signal onto a global // clock line. BUFG u2BUFG ( .I (clk_on_gp_pin), .O (clk_as_global_clock) ); 2) to route a general purpose pin as a non-critical clock: // a) tell Xilinx to bring the signal in with a normal buffer // synthesis attribute clock_buffer clk_on_gp_pin ibuf; input clk_on_gp_pin; 3) to route a general purpose pin as a low skew clock: // a) tell Xilinx to bring the signal in with a normal buffer // synthesis attribute clock_buffer clk_on_gp_pin ibuf; // b) tell Xilinx to use low skew clock resources // synthesis attribute uselowskewlines clk_on_gp_pin yes; input clk_on_gp_pin; 4) to convert a signal coming in on a global clock pin into a general purpose signal: input signal_on_gclk_pad; wire signal_for_gp_use; // Xilinx magic buffers for the data signals that come in // on GCLK signals IBUFG u1IBUFG ( .I (signal_on_gclk_pad), .O (signal_for_gp_use) ); OR TRY // synthesis attribute clock_buffer signal_on_gclk_pad ibufg; input signal_on_gclk_pad; Wouldn't you think that Xilinx would have a nice App note that **clearly** describes this? John PArticle: 51849
In article <b0p4th$s18sp$1@ID-78650.news.dfncis.de>, B. Joshua Rosen <bjrosen@polybus.com> wrote: > >TECO wsa great. For those of you too young to remember it, TECO was a >line editor that was the grandfather of today's EMACS. All of the >commands in TECO were control characters or a control character followed >by another character (the key bindings in EMACS are based on these >sequences). You could write large macros in TECO and save them just as >you can write GNULISP programs in EMACS today. The difference is that the >code was so cryptic that you had to get it right the first time because >even the author of the code couldn't read it. APL was similar. In APL you >could write a very powerful program in a single line of code but no human >could read it. My favorite from the DEC TECO manual: "MUNG - a recursive acronym for Mung Until No Good". I don't remember what mung acually did, though. -- Caleb Hess hess@cs.indiana.edu
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