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"Tim Olson" <mf0ttjk02@sneakemail.com> wrote in message news:<mf0ttjk02-20207E.09081329012003@central.isp.giganews.com>... > > A simple basic port (without working out all the subtle bugs) can be > done in a man-month or so. It depends upon how far you want to take it. > Basic code generation can be done fairly quickly, but getting really > good code generation out requires more work (and is why many of the > existing .md files are so non-intuitive). > mmm... that's about 4 months of my spare time. Hope I can get a friend to join me then :-) "dimmy" <diwil@eis.ru> wrote in message news:<b1646b$itl$1@news.wplus.spb.ru>... > Yes Marc, > it is possible. > pull gcc from somewhere and check stormy16 port (h8300 more complex, yet understandable). > this looks similar to yours and easy to understand. > Also, you may want to ckeck msp430 port (mspgcc.sf.net) which is simple as well. > I've worked with the H8300. It's a great processor family, but waaayyyy more complicated than my core. The mps430 seems to be less complicated. I'm checking the ports out now to see if I can make sense of it. "Alan Fitch" <alan.fitch@doulos.com> wrote in message news:<b15qvh$5up$1$8300dec7@news.demon.co.uk>... > > Have you looked at lcc? It's a C compiler generator. Have a look > at the Gray Research web-site, and the XR16 processor etc. Jan > Gray used lcc to create a C compiler for his processor, > Yep, studied this earlier. I've been thinking about modifying this core for my own purposes. But then again I thought it would be more fun/instructive to really start from scratch. Some ideas I'd like to implement are also totally not conforming to this architecture. Thanks all, MarcArticle: 52076
A couple of points: Firstly I'm running Quartus II ver. 2.2 on a Windows XP Professional PC (P4 @ 1.8GHz, 384MB). Now and again, particularly during simulation, the application hangs up. I have to close it down with the Task Manager and start again. Interestingly there's still a Quartus process running according to the Task Manager, something like Quartussim.exe ? Has anyone else had any similar problems? Secondly, being new to this I'm exclusively using Quartus but I'm well aware that Altera supplies Leonardo and Model Sim tools. Basically why would / should I use these 3rd party tools? Is Quartus deficient in some way? True the simulator seems a little strange. It seems I enter waveforms in one file but see the results in another (part of the simulation report). What am I missing? Any comments gratefully received. Rog.Article: 52077
I find it easier to leave the XILINX variable pointing at c:\xilinx and just swap over the directory names, for example c:\xilinx and c:\xilinx_4.3 /Mike "Noddy" <g9731642@campus.ru.ac.za> wrote in message news:1043822841.580942@skink.ru.ac.za... > I have two versions installed on Win98 and it works fine... just got to > change the XILINX variable (either in your registry, or easier still in your > autoexec.bat) to point to the right path. > > adrian > > > Hello, > > Can any conflict occurs if i install 2 versions of the xilinx tool in > > the same machine. > > thanks > >Article: 52078
Hey folks, Does anybody know how to trigger an exception in Microblaze from software? I'm porting uClinux and am considering using this as a means of implementing the system call interface. The SW docs indicate the vector for exception handlers etc, but don't actually explain (as far as I can see) what triggers exceptions, and how to do it synchronously from within assembly (short of placing an invalid opcode I guess, but that's ugly). The other alternative is to use BRK/BRKI, however this is currently used by xmdstub to set dubugger traps and I don't want to destroy my ability to do remote debugging (cos I'm sure gonna need it!!). Thanks, JohnArticle: 52079
"Pat Ford" <pat.ford@nrc.ca> wrote in message news:b0roij$4nn$1@moonstone.imsb.nrc.ca... > > "Austin Franklin" <austin@da98rkroom.com> wrote in message > news:v31ialjlc52sa4@corp.supernews.com... > snip > > > Oh, and the fact that so many books are written on HDL's to make you an > > > 'expert' - doesn't that say that they are darn hard to use correctly and > > > efficiently ?-) > > > > Agreed, but you can learn just enough to think you know what you are > > doing...which for some makes them dangerous ;-) > > > > Regards, > > > > Austin > > > > Which books would you recommend for a HDL newby ( I'm a C programmer, who > also does hardware) > Thanks > Pat Hi Pat, Don't take this the wrong way, but most programmers I know who try to design hardware don't really do it very well, because of lack of understanding and ability in the hardware area. Because you may be a very good C programmer doesn't mean you have the mindset and skill necessary to design hardware with an HDL, simply because it is a "programming" language. It's just a tool that merely allows for the implementation of concepts that aren't generally used in common C programming. IMO, the skill set for really doing FPGA/ASIC design, to do it right that is, is reasonably high. So, in order to answer your question, I'd need to know what your actual hardware background is. What have you done? Before recommending you simply "pick up a book" and "learn" an HDL, you might be better off with a more formal hardware engineering text that gives you some basic principles that you may not have...and reading an HDL book wouldn't necessarily help unless you had that understanding. Kind of like picking up a book on automotive suspension theory when you might not even know much about how cars work. Regards, AustinArticle: 52080
"Magnus Homann" <d0asta@mis.dtek.chalmers.se> wrote in message news:lt4r82jyut.fsf@mis.dtek.chalmers.se... > "Austin Franklin" <austin@da98rkroom.com> writes: > > > > The issue is that the rules set is a very complex set of > > > rules, > > > > Why do you say it is VERY complex? I do not see a set of rules that defines > > what hardware Verilog constructs gets compiled down to as being VERY > > complex. I am only talking about in general, as in, what does a case > > statement compile down to? > > Depends on architecture, doesn't it? Absolutely. > And constraints. Depending on what you mean by constraints, yes. AustinArticle: 52081
Hi John, It's depend on what you want to accomplish with system call. If you want to just change execution, use the normal branch instructions If you want to have more protection, the I would use the BRK/BRKI instruction. Since the BRK/BRKI instruction can have an address as an argument, you can branch to whatever place you want. The remote debugger can still use it since it jumps with the BRKI instruction into the remote debugger code. The debugging capabilities on MicroBlaze is going to be much better with the next release. Just wait a little. Göran John Williams wrote: > Hey folks, > > Does anybody know how to trigger an exception in Microblaze from > software? I'm porting uClinux and am considering using this as a means > of implementing the system call interface. > > The SW docs indicate the vector for exception handlers etc, but don't > actually explain (as far as I can see) what triggers exceptions, and how > to do it synchronously from within assembly (short of placing an invalid > opcode I guess, but that's ugly). > > The other alternative is to use BRK/BRKI, however this is currently used > by xmdstub to set dubugger traps and I don't want to destroy my ability > to do remote debugging (cos I'm sure gonna need it!!). > > Thanks, > > JohnArticle: 52082
The following link describes the steps to setup this capability: http://www.altera.com/support/kdb/rd05082002_6624.html - Subroto Datta Altera Corp. "david lamb" <david.lamb@videotron.ca> wrote in message news:YYf_9.27663$LR3.999729@charlie.risq.qc.ca... > Hi, > How do you tell Quartus where to find the leonardo executable file so that > it is able to launch it automatically? In the project settings, I assigned > Leonardo as the synthesis tool but when I start the compiler, it cannot find > Leonardo executable file. > Thanks > David > >Article: 52083
Goran Bilski wrote: > Hi John, > > It's depend on what you want to accomplish with system call. > If you want to just change execution, use the normal branch instructions I am emulating the unix/linux concept of a system call - which requires a transition from user space to kernel space (switch stacks and all sorts of stuff). The system call stub (which executes in user space) sets up registers to pass parameters and identify the required system call, then throws an exception (or does an INT 0x80 on intel architectures). This causes a transition to kernel mode at a predetermined address, where a dispatcher unpacks the registers and makes the appropriate call, then puts the return value back in a register and returns back to user mode. > If you want to have more protection, the I would use the BRK/BRKI instruction. > Since the BRK/BRKI instruction can have an address as an argument, you can > branch to whatever place you want. Yes that's what I thought. What happens to interrupts when the BIP flag is set? > The remote debugger can still use it since it jumps with the BRKI instruction > into the remote debugger code. So the debugger implements breakpoints by placing the opcodes for "BRKI debug_entrypoint" into memory, then jumping into the user code, finally restoring the original opcodes after the BRK? Regarding my original question though - what conditions cause an exception to be generated and control thrown to the exception handler at (I think) 0x10? For instance, does the software library thow some kind of exception on divide by zero? If so, how is this exception triggered? I setup an example that put an invalid opcode in the execution, and tried it on the software simulator, expecting flow to jump to the exception handler but nothing happened. Thanks, JohnArticle: 52084
Roger, The Quartus simulator process is designed to exit cleanly when it finishes. However the condition that you describe will require some further investigation, and it may be a function of this particular design/vector file/OS. In the menatime as you have correctly pointed out, the orphaned simulator process should be removed using the Task Manager. The ModelSim OEM version provided by Altera provides the behavioral simulation capability, which is not supported in the simulator that is available as a part of Quartus. The choice of Leonardo or Quartus II as a synthesis tool is one of preference. Regarding entering waveforms in one file and seeing the results in the simulation report, the reasoning is that the user does not want to overwrite the original source vectors with the final simulation result which contains both the input waveforms plus the outputs. The final result is shown in the simulation report in a non-editable window. Quartus has the capability to overwrite the original source vectors with the contents of the simulation report. If you try and edit any of the waveforms in the simulation report it brings up the Edit Input Vector File Dialog, which gives you two choices as to how to merge the results with the original source vectors. - Subroto Datta Altera Corp. "Roger" <rogerwilson@hotmail.com> wrote in message news:SZi_9.2550$T03.883746@newsfep2-win.server.ntli.net... > A couple of points: > > Firstly I'm running Quartus II ver. 2.2 on a Windows XP Professional PC (P4 > @ 1.8GHz, 384MB). Now and again, particularly during simulation, the > application hangs up. I have to close it down with the Task Manager and > start again. Interestingly there's still a Quartus process running according > to the Task Manager, something like Quartussim.exe ? Has anyone else had any > similar problems? > > Secondly, being new to this I'm exclusively using Quartus but I'm well aware > that Altera supplies Leonardo and Model Sim tools. Basically why would / > should I use these 3rd party tools? Is Quartus deficient in some way? True > the simulator seems a little strange. It seems I enter waveforms in one file > but see the results in another (part of the simulation report). What am I > missing? > > Any comments gratefully received. > > Rog. > > >Article: 52085
Eric Smith <eric-no-spam-for-me@brouhaha.com> writes: > Andrew Rogers <andrew@rogerstech.co.uk> writes: > > I discovered the problem when I ran XST on Linux using Wine. First I > > set the XILINX variable > > David Rogoff <david@therogoffs.com> writes: > > Why don't you run the Linux version? > > Because there *isn't* a native Linux version yet, is there? I thought > 4.2i and 5.1i only supported Linux via the use of Wine. I've been hoping > that 5.2i, reportedly due to be released in February, will include a native > Linux release. > Sorry - I was confusing it with Cadence tools. I just asked our FAE a couple of days ago and confirmed that Wine is currently the only way to run under Linux. DavidArticle: 52086
rahul_js53@yahoo.com (Rahul) wrote in message news:<feb07729.0301292057.178fcd8@posting.google.com>... > Hi all, > It would be of great help if you could provide me with links from > where i can download models in verilog/vhdl for huffman coding scheme. > Thanks in advance > Regards > Rahul Check out: http://www.opencores.org/projects/video_systems/ or my companies web site (www.asics.ws), for a free Huffman Encoder / Decoder Soft IP core. Regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----Article: 52087
hi all, for my particular design I need 7 clocks. Four of them are fixed for those I use the four global clock inputs. I would like to use three additional clocks for decoding three serial synchronous lines. Each line has a clock and a serial data line. Now the question: Is it possible to feed this three pairs in the chip and to use their clock signals very locally in the design to drive internal serial to parallel converters? For that purpose I would need to clock some CLB's from other than the four global clock lines. I'am using VHDL. How do I constraint the design that this will work, if it is possible? best regards markus meng -- Mit freundlichen Grüssen Markus Meng P.S. Achtung wir haben eine neue FAX-Nummer ******************************************************************** ** Meng Engineering Telefon 056 222 44 10 ** ** Markus Meng Natel 079 230 93 86 ** ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** ** CH-5400 Baden Email meng.engineering@bluewin.ch ** ** Web www.meng-engineering.ch ** ******************************************************************** ** You cannot create experience. You must undergo it. Albert Camus** -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 52088
Other than basic simulation of a synthesised design with waveforms, larger projects use VHDL etc to create testbench code that tests your design as part of the simulation. Typically Quartus can't handle as much of those aspects of simulation which become essential as projects get larger. Non-synthesisable constructs (like file i/o or screen display) aren't supported as well by Quartus Both Quartus and the ModelSim OEM supplied are far slower than your commercial equivalents. I recommend ActiveHDL but ModelSim is also well regarded. I only have v2.1 of Quartus but would say Leonardo is a better synthesis tool and you should be able to try synthesis with both for comparison. It definitely helps to get used to Leonardo as well - it can identify a whole different set of problem areas in the design, supports more of the VHDL synthesis subset and generally performs better results. That said, Quartus has made a fair bit of progress in this area. Good luck. You'll need it because you'll have lots of frustrating experiences to come :) PaulArticle: 52089
Thanks for your replies, I'll use ModelSim from now on .. DaveArticle: 52090
Hi Is there anyone working on implementing IEEE 802.11a WLAN in Handel-C? If there is someone, would you like to share some your knowledge and expereince with us? Thank you. Regards Imad Aalborg University, DenmarkArticle: 52091
Hi, What is the difference between the Xilinx Foundation Series and the Xilinx ISE. Regards, MuthuArticle: 52092
> Both Quartus and the ModelSim OEM supplied are far slower than your > commercial equivalents. I recommend ActiveHDL but ModelSim is also well > regarded. Paul, one thing to bear in mind is that full versions of ActiveHDL and Modelsim aren't cheap (Modelsim's about £5K in the UK). ModelsimOEM is free with an Altera subscription. I think ModelsimOEM is about 1/2 the speed of the 'full' version. This speed difference can be somewhat recovered by updating your PC to the latest 'best spec' (a few hundred pounds). > I only have v2.1 of Quartus but would say Leonardo is a better synthesis > tool and you should be able to try synthesis with both for comparison. It > definitely helps to get used to Leonardo as well - it can identify a whole > different set of problem areas in the design, supports more of the VHDL > synthesis subset and generally performs better results. That said, Quartus > has made a fair bit of progress in this area. I have wondered why Altera bother developing a synthesis tool in house. I would have thought they'd have been better concentrating on P+R tool development unless Exemplar are charging an arm and a leg to include Leonardo. Nial. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 52093
Hi i'm trying to program a atmel fpga configuration memory (AT17C128). I've made the ATDH 2225 programming cable http://www.atmel.com/atmel/acrobat/doc2288.pdf when i use their programming software ftp://www.atmel.com/pub/atmel/cpsinstall.exe and connect leds to the 10-pin header, they turn on and off. so i think the cable is alright. when i connect the eeprom to the 10pin header as follows, the software times out. or does not receive an 'ack': isp pin at17c128 pin 1 1 2 4 3 2 4 3 10 5 (gnd) 6 (connected to ground) 7 (to vcc for VRFY, to gnd for PGM, the atmel cps software says what is must be) 8 8 (vcc) does anyone have any tips for me ? Thanks, ThijsArticle: 52094
Indeed, but just using a counter can also be used to count the exact time after startup. I do this with a 56bit counter (for some 10years before it rolls over) and I use the first 32 bits for "random nr" Because the big counter "never" rolls over, it can be used without much software hassle to implement timeouts, ... "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:b18m7d$6g6$1@news.tu-darmstadt.de... > svhb <svhb@pandora.be> wrote: > : Depends on when you need that number, > > : If you need it only now and then, and not on regulary times, just read out a > : counter that never stops. > > : This can be usefull if you have a CPU on board, and you must for example > : generate a random nr for a TCP-packet sequence nr. Reading out a 32 bit > : counter can save you much processing time. > > > Implementing ringoscillators to clock those counters could add some more > stochastics to the numbers read... > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 52095
"Nial Stewart" <nial@spamno.nialstewart.co.uk> wrote in message news:3e3a591d$0$29908$fa0fcedb@lovejoy.zen.co.uk... > > > Both Quartus and the ModelSim OEM supplied are far slower than your > > commercial equivalents. I recommend ActiveHDL but ModelSim is also well > > regarded. > > Paul, one thing to bear in mind is that full versions of ActiveHDL and > Modelsim > aren't cheap (Modelsim's about £5K in the UK). ModelsimOEM is free with an > Altera subscription. > > I think ModelsimOEM is about 1/2 the speed of the 'full' version. This > speed difference can be somewhat recovered by updating your PC to the > latest 'best spec' (a few hundred pounds). > > > > I only have v2.1 of Quartus but would say Leonardo is a better synthesis > > tool and you should be able to try synthesis with both for comparison. It > > definitely helps to get used to Leonardo as well - it can identify a whole > > different set of problem areas in the design, supports more of the VHDL > > synthesis subset and generally performs better results. That said, Quartus > > has made a fair bit of progress in this area. > > I have wondered why Altera bother developing a synthesis tool in house. I > would have > thought they'd have been better concentrating on P+R tool development unless > Exemplar are charging an arm and a leg to include Leonardo. > Certainly agree with your points Nial though I thought ModelSim OEM is 1/4 full speed (half the speed of the ModelSim intermediate product but 1/4 of the £5k software) My PC is dual 3GHz processor with lots of RAM, but occasional 10 hr simulations are still a pain. Note also that students and colleges will get these product very very cheaply but the rest of us do indeed have to pay £5k plus (PS If you are a small consultancy in the UK, talk to Aldec's distributor parallel systems for potentially a substantial discount on Active HDL or rental options.)Article: 52096
Your question about the quality of these tools is a good one. The evolution of Altera's DSP Builder has been extremely rapid over the last two years. With the latest release of DSP Builder 2.1, major strides have been made in overall capability and quality. These tools are targetted for DSP dataflow sub-systems that are well suited to block diagram capture, not as a replacement for HDL based design. The major benefits of these types of flows are: - Integrated system verification - try writing sine/cosine waves in HDLs, let alone complex wireless comms system stimulus (or other DSP based systems). - Enables system algorithm engineers to implement hardware architectures without learning HDLs - Integrates nicely into HDL design flows The above benefits can deliver large productivity gains when used appropriately in the system design flow. With respect to the quality of the HDL generated, with DSP Builder, what you see is what you get. The HDL generation is very straightforward such that the resulting design will match the hardware you implied in your diagram. DSP Builder allows an easy path from DSP dataflow design capture to hardware implementation directly into an FPGA development system. DSP Builder Key Features - support for multiple clocks - these are taken directly from Altera's PLLs - intuitive DSP numeric type system - this is one of the biggest advantages over HDLs - direct links to FPGA development systems from Altera - DSP Development Kits - integrated IP library support - FIRs, FFTs, etc. - specific hardware features (DSP Blocks) can be directly targetted from DSP Builder - Signaltap II that enables real-time signal probing within the FPGA - product stability is excellent as it is built on Mathworks Simulink product These are all features that are available in HDLs except for the DSP datatypes. DSP Builder Weaknesses - DSP Builder does have a graphical Finite State Machine, however, many consider language based control capture significantly more productive (assuming you know how to write HDL). - DSP Builder only supports a sub-set of all Altera and 3rd party IP because it requires Mathworks C models for every block. - Currently, DSP Builder only supports VHDL. If you compare the capabilities of DSP Builder and Simulink against comparable tools like SPW, DSP Builder does essentially the same thing for a fraction of the cost. If you compare DSP Builder to HDL's and you are more comfortable with HDL's, the main reasons for working with DSP Builder will be for the verification flow. If you want a graphical tool for implementing DSP hardware, DSP Builder and Simulink have leading edge capabilities and a low price. Justin Cowling Director IP Marketing Altera Corp Bernhard Holzmayer <holzmayer.bernhard@deadspam.com> wrote in message news:<2892655.dgt8TP90lu@holzmayer.ifr.rt>... > Dave wrote: > > > Hi, > > Does anyone know the quality of those tools thant translate a > > Matlab/simulink model into vhdl, ready to be programmed in a > > targetted fpga. I'm mostly talking about DSPbuilder(Altera) and > > SystemGenerator(Xilinx). A couple of years ago, tools like that > > were doing a horrible job. How are they now? > > Thanks > > Dave > > Hi Dave, > > sorry for the delayed answer.... > > I'm currently working with SystemGenerator (on Xilinx' Spartan2). > I started with it 18 months ago, and in the very beginning, it was > really a horror. > Everything started with long lasting installation sessions - > it took me more than two weeks until everything worked together. > After that, a lot of library models were buggy and couldn't be used. > I dropped that project, then, and implemented it manually in VHDL. > > Meanwhile somebody from Xilinx had contacted me, and he was very > successful to convince me that I should give these tools another > try. > > In October last year, I upgraded to the newest version. > Installation was still a tough job, and we had to add some scripts > which would accomplish the post-processing. > > Since then, I've been working with SystemGenerator in a project and > it does a perfect job: > > 1. There's nothing to be done manually "between" Simulink and > loading the FPGA except pressing "Generate" in Simulink and > "Rerun all" in the Xilinx Project Navigator. > > 2. As soon as the Simulink project's simulation runs, > the generated VHDL code is synthesizable; > for me this means that I save a lot of time. > > 3. I enjoy the fact that a simulink model needs almost no additional > documentation; and even someone who's not familiar with VHDL or > with FPGAs should be able to do slight modifications on a project. > > 4. I do all simulations within Simulink which seems to me to be more > comprehensive or at least intuitive than ModelSim. > > Need to say that my project is not using most of the ressources > of the FPGA and is not too critical in timing. > > There might be some limitations for critical and/or big projects, > because the two-phase optimization might be slightly suboptimal, > but for me it's perfect. > > But: > don't expect that the tool would teach you VHDL, or that you > would receive readable VHDL code. > Instead, it's made of a huge amount of files full of templates, > which > are autogenerated and keep changing across modifications. > > Sometimes, it's difficult to find a reason, why Simulink refuses to > simulate a project with Xilinx model parts. > Xilinx should improve their error feedback messages > (I guess, they work on it, but sometimes you need some > "enlightenment"). > > XST produces a lot of warnings during the generator process. > Maybe they are important in some special situations: for my part, > I've learned just to launch the process, close my eyes, rely on it, > and afterwards use the produced file, and it works. > If you merely cannot ignore the warnings, there might be a lot of > work until they vanish - I don't know. > > Hope this gives you some impressions, and encourages you. > > BernhardArticle: 52097
David,
This article should help answer your question. Basically the EDA tool
needs to be available in your search path.
http://www.altera.com/support/kdb/rd05082002_6624.html
- Subroto Datta
Altera Corp.
"david lamb" <david.lamb@videotron.ca> wrote in message
news:YYf_9.27663$LR3.999729@charlie.risq.qc.ca...
> Hi,
> How do you tell Quartus where to find the leonardo executable file so that
> it is able to launch it automatically? In the project settings, I assigned
> Leonardo as the synthesis tool but when I start the compiler, it cannot
find
> Leonardo executable file.
> Thanks
> David
>
>
Article: 52098Hi John, John Williams wrote: > Goran Bilski wrote: > > Hi John, > > > > It's depend on what you want to accomplish with system call. > > If you want to just change execution, use the normal branch instructions > > I am emulating the unix/linux concept of a system call - which requires > a transition from user space to kernel space (switch stacks and all > sorts of stuff). > > The system call stub (which executes in user space) sets up registers to > pass parameters and identify the required system call, then throws an > exception (or does an INT 0x80 on intel architectures). This causes a > transition to kernel mode at a predetermined address, where a dispatcher > unpacks the registers and makes the appropriate call, then puts the > return value back in a register and returns back to user mode. > > > If you want to have more protection, the I would use the BRK/BRKI instruction. > > Since the BRK/BRKI instruction can have an address as an argument, you can > > branch to whatever place you want. > > Yes that's what I thought. What happens to interrupts when the BIP flag > is set? > When the BIP is set, interrupt are disabled. In your system call, you can then take the decision to reenable them again by clearing the BIP bit or your can leave it and have interrupt protection if you have more of a kernel functionality. The BIP bit is also blocking the external break signal EXT_BRK but it will NOT block the nonmaskable external break signal EXT_NM_BRK. > > > The remote debugger can still use it since it jumps with the BRKI instruction > > into the remote debugger code. > > So the debugger implements breakpoints by placing the opcodes for "BRKI > debug_entrypoint" into memory, then jumping into the user code, finally > restoring the original opcodes after the BRK? > Correct. > > Regarding my original question though - what conditions cause an > exception to be generated and control thrown to the exception handler at > (I think) 0x10? For instance, does the software library thow some kind > of exception on divide by zero? If so, how is this exception triggered? > As stated in the documentation there is currently no exceptions generated in MicroBlaze. That will probably change as more feature are added to MicroBlaze. > > I setup an example that put an invalid opcode in the execution, and > tried it on the software simulator, expecting flow to jump to the > exception handler but nothing happened. That is the expected behavior. > > Thanks, > > John Have you looked at the kernel that we ship with the EDK? It's has most of all the kernel functionality's and are shipped as source code with no royalties. GöranArticle: 52099
Antonio, I thought about this issue some more and this is what I think is going on..... I am assuming you are putting a period constraint on the input clock to the DCM and the tools are generating the period constraint for the output clocks. Since you are using the CLK_2X, CLK90 and CLK270, it is creating period constraints and timegroups for all three clocks even though you are not using CLK90 and CLK270 as clocks. (You can check the Translate report (design.bld file) to see if this is true.) The software doesn't take into account what pin the net is going to since the TNM_NET constraint is used for both clocks and data signals. Since you have two clocks (the clock enable and the clock) going to a component, each component is in two different timegroups. This is confusing the software and not getting the arrival times correct, therefore the requirement is incorrect (I think that is what is going on). The arrival times are shown in the Source Clock and Destination Clock descriptions. I am not sure why it would work with a FF and not a Blockram but sometimes the ordering in the PCF will do strange things like this. You would need to file a case with the Xilinx Hotline to be sure. If this is the situation, I agree that there is a problem with the software. I also thought more about your design. Since your clock enables are coming from the DCM (CLK90, CLK270) and the DCM is not considered a synchronous source, the paths from the DCM to the FFS/RAMS that use CLK90 and CLK270 as a clock enable are not covered by the time constraints. The other issue is the CLK_2X will be on a global clock and the clock enables will be local routing. You could end up with a race condition and sometimes the design will work and sometimes it won't. A better design solution would be to create the clock enables using the CLK_2X clock. I think what you want to do is capture data on every other edge of CLK_2X and sometimes see if consecutive edges of CLK_2X both have data? or something like that. If you did a clock divider and basically generated CLK_IN again this could be used to get every other CLK_2X edge. Invert this signal to get the other CLK_2X edge. This way the clock enable path will be covered by time constraints and you will have a synchronous design. Kate Antonio Pasini wrote: > Kate, > thanks for your suggestions. > > In fact, the help pages of timing analyzer are very clearly written. Still > don't understand what happens... > > Here is an extract of the timing report, when I enable the "NOTE 2" case > (the one that fails). > > ============================================================================ > ==== > Timing constraint: TS_clk2x_int = PERIOD TIMEGRP "clk2x_int" ts_clk_in / > 2.000000 HIGH 50.000 % ; > > 24 items analyzed, 9 timing errors detected. > Minimum period is 16.010ns. > ---------------------------------------------------------------------------- > ---- > Slack: -0.505ns (requirement - (data path - clock skew)) > Source: bram1.B (RAM) > Destination: dout_12 (FF) > Requirement: 7.500ns <---------- why this ???? should > be 15 ns! > Data Path Delay: 8.005ns (Levels of Logic = 0) > Clock Skew: 0.000ns > Source Clock: clk2x rising at 22.500ns > Destination Clock: clk2x rising at 30.000ns > > Data Path: bram1.B to dout_12 > Location Delay type Delay(ns) Physical Resource > Logical Resource(s) > ------------------------------------------------- ------------------- > RAMB4_R0C0.DOB12 Tbcko 3.414 bram1 > bram1.B > P125.O net (fanout=1) 3.528 ram_out<12> > P125.CLK Tioock 1.063 dout<12> > dout_12 > ------------------------------------------------- --------------------- > ------ > Total 8.005ns (4.477ns logic, > 3.528ns route) > (55.9% logic, 44.1% > route) > > What is really strange is: > > - the blockram and the following flip flop are clocked by the same clock, > clk2x, with 15 ns period. > - substituting the blockram with FF all goes well.... ! > - if I use, instead, CLK 90° output, negating it, all goes well, as you can > see below: > > ============================================================================ > ==== > Timing constraint: TS_clk2x_int = PERIOD TIMEGRP "clk2x_int" ts_clk_in / > 2.000000 HIGH 50.000 % ; > > 24 items analyzed, 0 timing errors detected. > Minimum period is 8.224ns. > ---------------------------------------------------------------------------- > ---- > [snip...] > ---------------------------------------------------------------------------- > ---- > Slack: 6.782ns (requirement - (data path - clock skew)) > Source: bram1.B (RAM) > Destination: dout_12 (FF) > Requirement: 15.000ns > Data Path Delay: 8.218ns (Levels of Logic = 0) > Clock Skew: 0.000ns > Source Clock: clk2x rising at 0.000ns > Destination Clock: clk2x rising at 15.000ns > > Data Path: bram1.B to dout_12 > Delay type Delay(ns) Logical Resource(s) > ---------------------------- ------------------- > Tbcko 3.414 bram1.B > net (fanout=1) 3.741 ram_out<12> > Tioock 1.063 dout_12 > ---------------------------- ------------------------------ > Total 8.218ns (4.477ns logic, 3.741ns route) > (54.5% logic, 45.5% route) > > I'm really not qualified to state that, but seems a problem of timing > constraints. > > > Does it not work in the lab or does it not meet timing? > > I didn't try on the actual hw... hoping next days. > > > > > > That same requirement dissolves if I substitute the block ram with a > bank of > > > FF. Why ? > > > > This should not matter either but I am not exactly sure what is going on. > > Yes, I agree with you; should not matter... > > > > At the block ram input port, all signals are already synchronized to > CLK2X; > > > why timing requirement should change so drastically ? > > > > I don't understand either since you aren't using CLK90 or CLK270 as a > clock, > > just clock enables. > > Exactly.
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