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Hi Arkaitz, Either add xmdstub.elf (and the .bmm file) to the Project Navigator project - associated with the top level HDL file in the project. Alternatively, you have a few other options. One would be to use the hardware debug module (MDM) if you're using the newest version of MicroBlaze (2.00.a). The other would be to not add any .elf file to the ISE project and import the uninitialized .bit file and the <system>_bt.bmm file from ISE back into XPS. There you can update bitstream with whichever .elf file you want (xmdstub or executable) without regenerating the hardware from ISE. I hope this information helps. Best regards, Ryan Laity Xilinx Applications arkaitz wrote: > Hi all, > > I want to export my design in XPS to Project Navigator but when the > design is in XMDSTUB mode and not in Executable Mode. > > I have exported and opened the design with Project Navigator but when > I download the bitstream to the FPGA I cannot connect with MicroBlaze > via XMD. > > Does anybody know if is needed to add to the project any other file in > the Project Navigator? > > I have tried adding "executable.elf" file with no success. > > Thanks in advance, > > Arkaitz.Article: 64151
arkaitz wrote: > I have exported and opened the design with Project Navigator but when > I download the bitstream to the FPGA I cannot connect with MicroBlaze > via XMD. > > Does anybody know if is needed to add to the project any other file in > the Project Navigator? The usual modus operandi(us?) for going between XPS and PN is to export your project to PN, create the bitstream, then reimport it into XPS, and update the bitstream there. I've done this many times and never had a problem, but I've never tried to integrate the executable in PN. Is there a specific reason you want to bypass the standard flow? -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --Article: 64152
Hi. I am designing PCI-X interface on Xilinx virtex2 pro with 100 MHz frequency. What IOSTANDARD should I use in the .ucf file ? I see only PCI33_3 and PCI66_3 in Xilinx litrature as "PCI" I/O's. ThankX NAHUMArticle: 64153
You should definitely use the multipliers if you are using a V2. Why burn up the fabric with DA logic if you have unused, fast, embedded multipliers? If your output sample rate is 10Msps, then you should only need 256 * 10/200 multipliers, where 200MHz is the estimated pipeline multiplier speed. You will need about the same number of adders and you will accumulate over 200/10=20 cycles. You will need to store 20 coeffs for each multiplier, which you can do with LUT RAMs or with blockRAMs if you have extra. If the coeffs are symmetric, you can halve the number of multipliers required (if you are short) by adding symmetry adders in the CLB fabric. -Kevin "Jim George" <jimgeorge@softhome.net> wrote in message news:8775ef2b.0312180717.8369906@posting.google.com... > Hello All, > I'd like to know if the generally held advice that Distributed > Arithmetic (DA) filters are the "best" way to implement FIR filters on > an FPGA still holds good when one uses a Virtex-][. > In my application, I require a 256-tap filter which takes in > 18-bit samples at 50 MSPS and decimates it down to 10 MSPS (coeffs are > 16-bit). I use an XC2V3000. Currently, we don't have the hardware > required to synthesize the complete design (not enough memory), so > I've synthesized just the filter with a simple testbench. It turns out > that MAC FIR filters require far less resources than a DA-FIR one with > an equivalent spec. Could this be due to Virtex-]['s multipliers or is > this some quirk I'm not taking into account? > Thanks in advance. > -Jim.Article: 64154
If you are using Xilinx PCI-X LogiCORE, all the constraints are defined in core's UCF file and the wrapper files instantiate PCIX buffers. So you don't need to add any IOSTANDARD constraint in UCF file. PCIX IO buffers are listed in docs @ http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/lib/lib0310_278.html -Vikram Nahum Barnea wrote: > Hi. > > I am designing PCI-X interface on Xilinx virtex2 pro with 100 MHz frequency. > > What IOSTANDARD should I use in the .ucf file ? > > I see only PCI33_3 and PCI66_3 in Xilinx litrature as "PCI" I/O's. > > ThankX > NAHUMArticle: 64155
Hi all, I'am having troubles finding the VHDL models on the micron site. Do others have the same problem? Markus -- Mit freundlichen Grüssen Markus Meng P.S. Achtung wir haben eine neue FAX-Nummer ******************************************************************** ** Meng Engineering Telefon 056 222 44 10 ** ** Markus Meng Natel 079 230 93 86 ** ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** ** CH-5400 Baden Email meng.engineering@bluewin.ch ** ** Web www.meng-engineering.ch ** ******************************************************************** ** You cannot create experience. You must undergo it. Albert Camus** -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 100,000 Newsgroups - 19 Different Servers! =-----Article: 64156
Hi, I'm building a simple board with Spartan IIE ( XC2S100E), and wondering is it OK to derive power for VCCINT (1.8V) and VCCO (3.3V) from something simple, such as LM317. I know it can source enough current during start-up, but I'm not sure about voltage ramp, power sequencing etc. Any hints are welcome. Thanks in advance, GoranArticle: 64157
Try AccelChip: http://www.accelchip.com/ Satish K wrote: >Dears > >Can anybody help me in realizing below Mathlab code to VHDL >This is just a deceptive one, Tried in both DSPBuilder or >SystemGenerator. > >If not possible by tool ,can anybody help me in hinting in Converting >this to VHDL. > >Have many doubt's in DSPBuilder >How to insert the FOR loop in DSP Builder and Variable and >assignment's realized form it. >Thanks in advance. >Satish > >---------mathlab code------------- > >% Inputs : Signal : 256 Samples, 16 bits each >% constants Any value may be assigned to them for time being >% XP : 256 * 16 Bits () >% YP : 256 * 16 Bits >% A >% B >% C >% Rmin >% Rmax >% dR >% D > > >% Array : array 65536*16 or block RAM > >fftSig = fftshift(fft(fftshift(signal)),512)); > >for k = 1:256, > for k2 = 1:256 > tst =sqrt(( XP (k2)-A).^2+ (YP(k)-B)^2 +C^2); > if (tst > Rmin & tst < Rmax-dR); > IL = (tst –Rmin)/dR+1; > Ind = floor (IL); > Q =IL-Ind; > px = fftSig(Ind)+Q .*… > (fftSig(Ind+1)-fftSig(Ind)); > INDEX = k + (k2 – 1)*256; > ARRAY(INDEX)= ARRAY(INDEX) +px.*exp(-j*D*tst); % j= sqrt(-1) > End > End >end >-------------------------------------------- > >Article: 64158
I'm looking at table 2-62 on p.331 of my 2VP databook that lists PCI33_3, PCI66_3, and PCIX I/O specs. Maybe you were searching for PCI-X instead of PCIX. Nahum Barnea wrote: > Hi. > > I am designing PCI-X interface on Xilinx virtex2 pro with 100 MHz frequency. > > What IOSTANDARD should I use in the .ucf file ? > > I see only PCI33_3 and PCI66_3 in Xilinx litrature as "PCI" I/O's. > > ThankX > NAHUMArticle: 64159
There seems to be some confusion about Spartan3 availability. According to a Xilinx press release in October, several Spartan3 chips should be in production. However, Insight Memec, the UK distributor, has just told me that they haven't any in stock and don't even know when they will be getting some! They were able to give me some prices, though. Does anyone know what is going on? Leon -- Leon Heller, G1HSM Email: aqzf13@dsl.pipex.com My low-cost Philips LPC210x ARM develpment system: http://www.geocities.com/leon_heller/lpc2104.htmlArticle: 64160
Peter Seng wrote: > Hello, > > have problem to access following web site: > > http://www.fpga-faq.com > > > Know that it worked in the past, now following error occures (using IE 6.0): > > HTTP-Fehler 403 - Verboten > Internet Explorer > > > When using Mozilla 1.41 on MS or Linux machine we get following message: > > Forbidden > You don't have permission to access / on this server. It works for me, using Netscape 7.1. Leon -- Leon Heller, G1HSM Email: aqzf13@dsl.pipex.com My low-cost Philips LPC210x ARM develpment system: http://www.geocities.com/leon_heller/lpc2104.htmlArticle: 64161
PO Laprise wrote: >> If you write -- at the beginning of a line and then press Enter, the >> next line will also be commented. > > Not to start an emacs vs. vim war, but a properly set-up vhdl plug-in in > vim will do this as well. > > Don't , emacs people won't like :-p -- Jos De LaenderArticle: 64162
On Thu, 18 Dec 2003 16:07:33 +0100, "Peter Seng" <NOSPAM@seng.de> wrote: >Hello, > >have problem to access following web site: > >http://www.fpga-faq.com > >Know that it worked in the past, now following error occures (using IE 6.0): Hello Peter and others, The problem with www.fpga-faq.com is ME. I am the owner and webmaster and maintainer for this site. I am sorry to say it has nothing to do with which browser you are using, it is my lack of experience in handling web access abuse. Currently I am implementing some fairly draconian access controls on the site due to my lack of experience in doing it more nicely. A little history: I created this site a few years ago and have maintained it and paid for it with my own money. As you know, it is vendor neutral, and has no advertising, popups or other trash. Sort of a charity project. In October and November 2003, someone using 2 IP addresses attacked the site and in a matter of 1 or 2 days, early in both months, managed to use more than the total bandwidth allowance for the whole months (20 GB per month) This lead to some very high excess bandwidth charges, that were about 10 times my monthly costs. (normal bandwidth for a whole month is about 10 to 12 GB) While researching the problem, I found that there were multiple other webcrawler type accesses that were not comming from known search engines. Google, Inkotomi, Yahoo, Altavista, AskJeeves together represent about 97% of all referrer traffic. In particular, some of these crawlers are deliberately masking their identity. Most of this high bandwidth traffic is coming through DHCP IP management, and so the IP address changes within various blocks. I have now started blocking IP addresses, and you have been unfortunately caught up in this. Although I have enabled the IP address that you used earlier today, I believe your IP is dynamic, and so this may not have helped you. (your IP was 80.145.86.184, gatewayed through online.de) If there is someone who is very knowledgeable about Apache web servers, the .htaccess files, and the rewriting rules creation, I would appreciate some help. My other alternative would be to use a service with higher bandwidth limits, but to support that I would have to have advertising or some other way to fund the change. I am glad that this was a service that was useful for you, and really sorry it isn't working for you currently. I am actively trying to find a solution to this problem. ======== Separately, for those of you still using the Xilinx gateway to this news group, could you please change over to using the Google Groups gateway. Both are free, but the Xilinx one is still turning nice text posts into HTML, which then wastes a few hours of my time each month cleaning up the mess. All the best for the Holliday Season! =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COMArticle: 64163
Hi Leon, Same situation here in Germany. I ordered Spartan-3 FPGAs in September. My distributor cannot tell me when I'll get them. It seems that Xilinx serves the "big players" first and does not care about small customers at all ! An "unofficial" statement from a Xilinx employee was "Spartan-3 is for high-volume customers only" I believe they have yield problems. Maybe someone from Xilinx can comment this. -Manfred Kraus "Leon Heller" <aqzf13@dsl.pipex.com> wrote in message news:3fe1fea1$0$25666$cc9e4d1f@news.dial.pipex.com... > There seems to be some confusion about Spartan3 availability. According > to a Xilinx press release in October, several Spartan3 chips should be > in production. However, Insight Memec, the UK distributor, has just told > me that they haven't any in stock and don't even know when they will be > getting some! They were able to give me some prices, though. > > Does anyone know what is going on? > > Leon > -- > Leon Heller, G1HSM > Email: aqzf13@dsl.pipex.com > My low-cost Philips LPC210x ARM develpment system: > http://www.geocities.com/leon_heller/lpc2104.html >Article: 64164
Goran, If you place a 470uF, 680uF or a 1000 uF on the output of the LM317, you should have enough stored charge to start up the Spartyan IIE. Check out the app notes 450 and 451 which detail start up tricks. Austin Goran wrote: > Hi, > I'm building a simple board with Spartan IIE ( XC2S100E), and > wondering is it OK to derive power for VCCINT (1.8V) and VCCO (3.3V) > from something simple, such as LM317. I know it can source enough > current during start-up, but I'm not sure about voltage ramp, power > sequencing etc. Any hints are welcome. > Thanks in advance, > GoranArticle: 64165
Philip Freidin wrote: > On Thu, 18 Dec 2003 16:07:33 +0100, "Peter Seng" <NOSPAM@seng.de> wrote: > >>Hello, >> >>have problem to access following web site: >> >>http://www.fpga-faq.com >> >>Know that it worked in the past, now following error occures (using IE 6.0): > > > Hello Peter and others, > > The problem with www.fpga-faq.com is ME. I am the owner and webmaster and > maintainer for this site. > > I am sorry to say it has nothing to do with which browser you are using, > it is my lack of experience in handling web access abuse. > > Currently I am implementing some fairly draconian access controls on the site > due to my lack of experience in doing it more nicely. > > A little history: I created this site a few years ago and have maintained > it and paid for it with my own money. As you know, it is vendor neutral, > and has no advertising, popups or other trash. Sort of a charity project. > > In October and November 2003, someone using 2 IP addresses attacked the > site and in a matter of 1 or 2 days, early in both months, managed to use > more than the total bandwidth allowance for the whole months (20 GB per month) > This lead to some very high excess bandwidth charges, that were about > 10 times my monthly costs. (normal bandwidth for a whole month is about > 10 to 12 GB) Hmmm indeed. There was certainly 'a global lurch' in internet miss-use/bandwidth around this timeframe. It is still having effects. Not sure if the cause is/was a)- Bored teenagers b)- Cynical ISP's wanting to bump customers into higher $$ zones c)- Geo political infrastructure attacks or some combination there-of... > My other alternative would be to use a service with higher bandwidth > limits, but to support that I would have to have advertising or some > other way to fund the change. I'd suggest you send a copy of this issue to both Altera, and Xilinx, with a request for suggestions/assistance. They should view www.fpga-faq.com as an important infrastructure to the FPGA industry generally, and one that can actually reduce their own support bandwidth (in personnel terms). If such a community-interest web site can save both companies even one support person each, there is good scope for some support... Examples of how they could help, would be to sponsor the bandwidth, or provide a physical host node under your admin, or.... > I am glad that this was a service that was useful for you, and really > sorry it isn't working for you currently. I am actively trying to find > a solution to this problem. It is appreciated. Merry Xmas. -jgArticle: 64167
DSP Builder is a tool which converts Simulink model (*.MDL) to VHDL. For conversion of MATLAB m-scripts to VHDL, you have to first translate the matlab code to DSP Builder blocksets in Simulink. For instance, the 'if-else' statements can be converted to mux blocks. 'For loops' can be converted to counters with comparators. Variables can be just plain registers. If you would like more examples of how to do this using DSP Builder, please send me an email at hneoh@altera.com You may also want to look at AccelChip's website. They have a tool which allows you to go directly from MATLAB code to synthesizable HDL. Regards, Hong Shan hneoh@altera.com satishkmys@yahoo.com (Satish K) wrote in message news:<380e8c67.0312180513.36368710@posting.google.com>... > Dears > > Can anybody help me in realizing below Mathlab code to VHDL > This is just a deceptive one, Tried in both DSPBuilder or > SystemGenerator. > > If not possible by tool ,can anybody help me in hinting in Converting > this to VHDL. > > Have many doubt's in DSPBuilder > How to insert the FOR loop in DSP Builder and Variable and > assignment's realized form it. > Thanks in advance. > Satish > > ---------mathlab code------------- > > % Inputs : Signal : 256 Samples, 16 bits each > % constants Any value may be assigned to them for time being > % XP : 256 * 16 Bits () > % YP : 256 * 16 Bits > % A > % B > % C > % Rmin > % Rmax > % dR > % D > > > % Array : array 65536*16 or block RAM > > fftSig = fftshift(fft(fftshift(signal)),512)); > > for k = 1:256, > for k2 = 1:256 > tst =sqrt(( XP (k2)-A).^2+ (YP(k)-B)^2 +C^2); > if (tst > Rmin & tst < Rmax-dR); > IL = (tst ?Rmin)/dR+1; > Ind = floor (IL); > Q =IL-Ind; > px = fftSig(Ind)+Q .*? > (fftSig(Ind+1)-fftSig(Ind)); > INDEX = k + (k2 ? 1)*256; > ARRAY(INDEX)= ARRAY(INDEX) +px.*exp(-j*D*tst); % j= sqrt(-1) > End > End > end > --------------------------------------------Article: 64168
Amontec Team <laurent.gauch@www.DELALLCAPSamontec.com> wrote in message news:<3fe1ccda$1@news.vsnet.ch>... > hi all, > > I have to design a VHDL CRC-32 rtl macro cell (100BASE-T framing) for my > tiny MAC design. > > I have to place my macro in a small spartan-3 where each Flip-Flips are > precious. > > Is that possible to place a part of my CRC-32 in a LUT based shift > register (feature of virtex to spartan-3). > > Since CRC-32 = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + > x5 + x4 + x2 + x + 1, is that possible to do the job with LUTs based > shift register. > > I know a lut only has 1 output, but is that possible to do partial > shifts, like x31<-x30<-x29<-x28<-x27 in the same LUT ? > Thanks for all I don't think this is really possible. I mean, it's possible to use SRLs instead of individual FFs, but you would need multiple clk cycles to read out the bits that make up the CRC result. And you would need FFs to store those bits. This means that you could not be continuously generating the CRC... you need to stop the circuit to read the result. The smallest Spartan-III device (3s50) has 1536 LUTs and 1536 FFs, you really can't spare 32 FFs and 2 LUTs? MikeArticle: 64169
Tom wrote: > Is there anybody who has experience at interfacing a WishBone IP core > to a CoreConnect bus. Specifically the design of a bridge ? No, but I would be very interested in such a thing! Opening up the whole opencores library to use with microblaze would be a great boost for both. Regards, JohnArticle: 64170
It really depends on your specific design. I've used DA as well as mac based
filters in V2.
the multpliers will often be smaller realizations, provided you have enough
multipliers on the chip, however for larger filters, you may find it is more
efficient to use DA to keep stuff together. Multipliers also have a fixed
width, so if your data or coefficients are greater than 17 bits it will often
pay to use DA instead, likewise, if the coefficients are only a couple of bits.
Kevin Neilson wrote:
> You should definitely use the multipliers if you are using a V2. Why burn
> up the fabric with DA logic if you have unused, fast, embedded multipliers?
> If your output sample rate is 10Msps, then you should only need 256 * 10/200
> multipliers, where 200MHz is the estimated pipeline multiplier speed. You
> will need about the same number of adders and you will accumulate over
> 200/10=20 cycles. You will need to store 20 coeffs for each multiplier,
> which you can do with LUT RAMs or with blockRAMs if you have extra. If the
> coeffs are symmetric, you can halve the number of multipliers required (if
> you are short) by adding symmetry adders in the CLB fabric.
> -Kevin
>
> "Jim George" <jimgeorge@softhome.net> wrote in message
> news:8775ef2b.0312180717.8369906@posting.google.com...
> > Hello All,
> > I'd like to know if the generally held advice that Distributed
> > Arithmetic (DA) filters are the "best" way to implement FIR filters on
> > an FPGA still holds good when one uses a Virtex-][.
> > In my application, I require a 256-tap filter which takes in
> > 18-bit samples at 50 MSPS and decimates it down to 10 MSPS (coeffs are
> > 16-bit). I use an XC2V3000. Currently, we don't have the hardware
> > required to synthesize the complete design (not enough memory), so
> > I've synthesized just the filter with a simple testbench. It turns out
> > that MAC FIR filters require far less resources than a DA-FIR one with
> > an equivalent spec. Could this be due to Virtex-]['s multipliers or is
> > this some quirk I'm not taking into account?
> > Thanks in advance.
> > -Jim.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 64171John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<brtbfq$2ut$1@bunyip.cc.uq.edu.au>... > Tom wrote: > > Is there anybody who has experience at interfacing a WishBone IP core > > to a CoreConnect bus. Specifically the design of a bridge ? > > No, but I would be very interested in such a thing! Opening up the > whole opencores library to use with microblaze would be a great boost > for both. > > Regards, > > John An interesting aside for those using Altera products: The Avalon bus interface and Wishbone are close enough to each other to make this very simple. A while ago I studied the feasibility of this using Avalon and the Ethernet MAC core on opencores.org. You can wire up a Wishbone slave to Avalon in the SOPC Builder tools with a few mouse clicks. No bus bridge required. Wishbone masters require a bit of RTL to implement their "acknowledge" signal but other than that everything falls together automatically. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 64172
"Manfred Kraus" <makra7960@tiscali.de> writes: > Same situation here in Germany. I ordered Spartan-3 FPGAs in > September. My distributor cannot tell me when I'll get them. It seems > that Xilinx serves the "big players" first and does not care about > small customers at all ! An "unofficial" statement from a Xilinx > employee was "Spartan-3 is for high-volume customers only" That shouldn't be a surprise, since it's the same thing that happened with the Spartan 2. It was nearly a year between availability to high-volume customers, and availability to everyone else. > Maybe someone from Xilinx can comment this. Seems unlikely that you'll get any official comment. They allocate the limited production where it will do them the most good. I would do the same in their position. If you're not going to buy in high volumes, you shouldn't try to use the latest bleeding-edge chips. That's true of chips of any sort, not just FPGAs.Article: 64173
This sounds like a grounding problem, whose LVDS drivers are you using? "Masoud Naderi" <naderimisc@yahoo.com> wrote in message news:2ba3bbea.0312152232.5d87d9d2@posting.google.com... > Hi, > Our LVDS Drivers failed when their power supply starts(it has soft > start feature). On some boards only positive output or input of > differential side failed (probably because of high current sourcing in > failure mode). > I checked power suppply yesterday and found some negative (-2.7v) but > very narrow (200ns) spikes on power supply rail. I think it is one of > the problems. LVDS drivers are from TI and spikes below -0.5 damage > them. I look for more problem, e.g. grounding and ... > > here are some shematic of our system: > > LVDS+/- <-............3meter twisted-pair cable...............-> > LVDS+/- > GND ----------------------------------------------------------> GND > > regards >Article: 64174
Hate to say it, but this is why I use Altera. I can get Cyclones -- today. And their free tools support the entire family. Hard to beat that. "Leon Heller" <aqzf13@dsl.pipex.com> wrote in message news:3fe1fea1$0$25666$cc9e4d1f@news.dial.pipex.com... > There seems to be some confusion about Spartan3 availability. According > to a Xilinx press release in October, several Spartan3 chips should be > in production. However, Insight Memec, the UK distributor, has just told > me that they haven't any in stock and don't even know when they will be > getting some! They were able to give me some prices, though. > > Does anyone know what is going on? > > Leon > -- > Leon Heller, G1HSM > Email: aqzf13@dsl.pipex.com > My low-cost Philips LPC210x ARM develpment system: > http://www.geocities.com/leon_heller/lpc2104.html >
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