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Dear Sir or Madam,
I have a question concerning Modelsim:
In a VHDL testbench I instantiate the module "packetfile_ctrl.vhd"
as U1
In the attached macro I add waves. These waves are inputs and outputs
of the module "packetfile_ctrl.vhd".
But what if I want to view internal signals? For example the internal
signal
last_block:
If I write the following command in my macro I do not get a wave of
this signal
"add wave sim:/tb_packetfile_ctrl/u1/last_block"
So how can I add an internal signal?
Is there an alternative way without using the macro (this means
adding a wave belatedly when the waveform - editor is already opened)
?
Thank you for your help.
Best regards
Andrés Vázquez
G&D
MACRO:
cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim
vlib modelsim_work
vmap work modelsim_work
vsim -sdftyp /U1=packetfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRL
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.vho}
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CTRL.vhd}
view signals
view wave
vsim work.TB_PACKETFILE_CTRL
add wave sim:/tb_packetfile_ctrl/u1/P_clk_in
add wave sim:/tb_packetfile_ctrl/u1/P_clk_out
add wave sim:/tb_packetfile_ctrl/u1/Reset
add wave sim:/tb_packetfile_ctrl/u1/Write
add wave sim:/tb_packetfile_ctrl/u1/Read
add wave sim:/tb_packetfile_ctrl/u1/last_block ?????????????????
Article: 64451Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> writes: > We have a dual processor box here with hyperthreading (i.e. 2 > processors, each capable of running 2 threads at the same time) that > we use for running xilinx software. > > I don't notice any great difference in speed when hyperthreading is > switched on or off. I have it switched *off* at the moment, because > that is supposed to be faster for the single threaded apps we are > running (at most two apps at a time). > > The benefit of hyperthreading would be much more significant if there > was only a single processor, or if there were lots of threads running. > I've found that enabling HT makes my machine useful for writing documentation, reading email and other non-demanding tasks whilst PAR is running. > Note that hyperthreading doesn't work with win2k; you need XP (or SMP > Linux). > Not quite - Win2K treats the "extra" processor as a whole extra (real) processor for scheduling purposes. Apparantly the XP scheduler understands the difference, and schedules things differently - I don't know what the differences are though. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 64452
For starters make sure that your sensitivity list is complete. It isn't at present and some simulators will simply ignore statements where the "input" signals are not in the sensitivity list. Synthesisers should do something similar in theory but most "assume" the sensitivity list. John Adair Enterpoint Ltd. This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Simone Winkler" <simone.winkler@gmx.at> wrote in message news:1073153426.69428@news.liwest.at... > Hello! > > I've got a strange problem that I don't know any solution for - up to now I > tried everything, but it didn't work. > The state machine always stops to go to the next state - I > really don't understand why. > > I've got a state machine with 5 states: SEL_EP, WRITE_INIT, WRITE_DATA, > VAL_BUF and IDLE. It gets stuck after the WRITE_INIT state, just remains in > the WRITE_INIT state all the time. WHY???? > The 2nd (smaller) problem is, that the data at write_out comes one clock > cycle too late. I understand why, but how can i change this? > > I don't know if it's a good idea to solve my problem with my kind of code, > i'm an "advanced beginner" and as I am used to program "sequential > programming languages" I've got big problems with doing sequential things in > vhdl. What is the easy way to do things one after the other, e.g. write one > byte after the other? (also to be synthesizable). > > I put the code at http://members.liwest.at/simsi/stuff/usb.vhd, because it's > quite long to put it here. (don't be afraid - no virus!) > > Please help me! I really don't know where to go on. > > Thank you, > Simone > >Article: 64453
When I was debugging my modules I did it separately. Send a stream out of UART, make sure it is working prperly. Make sure that receiver is working by observing debug pins on PLD. Revise quartz rate and divider. Do you synchronize Rx input? I don't and everything working OK; however, there are multibit counters depending on the input, thus I think it should.Article: 64454
Hello, I need to program CoolRunner CPLD using an embedded controller. How to set the CPLD registers to work in the ISP mode? Please explain how to do. Regards, ChiArticle: 64455
chi wrote: > Hello, > > > I need to program CoolRunner CPLD using an embedded controller. How to > set the CPLD registers to work in the ISP mode? > > Please explain how to do. > > Regards, > Chi just put PORT_EN pin to '1' ! Laurent Gauch www.amontec.comArticle: 64456
"Martin Thompson" <martin.j.thompson@trw.com> wrote in message news:u65fqln2u.fsf@trw.com... > Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> writes: > > > We have a dual processor box here with hyperthreading (i.e. 2 > > processors, each capable of running 2 threads at the same time) that > > we use for running xilinx software. > > > > I don't notice any great difference in speed when hyperthreading is > > switched on or off. I have it switched *off* at the moment, because > > that is supposed to be faster for the single threaded apps we are > > running (at most two apps at a time). > > > > The benefit of hyperthreading would be much more significant if there > > was only a single processor, or if there were lots of threads running. > > > > I've found that enabling HT makes my machine useful for writing > documentation, reading email and other non-demanding tasks whilst PAR > is running. > > > Note that hyperthreading doesn't work with win2k; you need XP (or SMP > > Linux). > > > > Not quite - Win2K treats the "extra" processor as a whole extra (real) > processor for scheduling purposes. Apparantly the XP scheduler > understands the difference, and schedules things differently - I don't > know what the differences are though. > I think (but is not sure) that if you have a Multiprocessing system, then there could be a problem using HT. I believe that Win2k and maybe WinXP restricts you to use 2 processors. If you want to use 2 physical processors with HT enabled, then this should count as 4 processors, and you will maybe need the server edition of Win2k/XP. I see that the major benefit is improved response time when windows (mis) behaves in the background... Got my Multiprocessor server board mainly to get more PCI slots. -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden.Article: 64457
In comp.arch.fpga Wouter van Ooijen (www.voti.nl) <wouter@voti.nl> wrote: >>If I were your prof, and I caught you blatantly trying to get others to do your >>thinking for you, I'd make you design it using nothing but BC547's, resistors >>and diodes. That way you might l-e-a-r-n something. That is why you are at uni? > > Why would he need diodes? > > > > Wouter van Ooijen > > -- ------------------------------------ > http://www.voti.nl > PICmicro chips, programmers, consulting That would be diode transitor resistor logic, stuff from 1st year electronic engineering. Diode and resistors to make and gates and transitor invertors. -- Wing Wong. Webpage: http://wing.ucc.asn.auArticle: 64458
Hello all: I am a new guy for the fpga region. I get some problem recently, is waveform can simulate the varable which declared as "signal" in VHDL program? I stick over there for 3 days, please advice....Article: 64459
Some additional question:
Is the shown macro for functinal or for timing simulation ?
The background of this question: When I run the simulation and
open the "signals" window --> ADD WAVE ---> ALL SIGNALS IN DESIGN
I can find the original names of the primary inputs and outputs
but I can NOT find the original internal names, these seem to be
renamed by the compiler.
If I want to analyse a state machine it is impossible without
the original names.
So my question: How can I simulate (functional) without losing
the original names ?
>
> MACRO:
> cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim
> vlib modelsim_work
> vmap work modelsim_work
> vsim -sdftyp /U1=packetfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRL
> vcom -93 -reportprogress 300 -work work
> {H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.vho}
> vcom -93 -reportprogress 300 -work work
> {H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CTRL.vhd}
> view signals
> view wave
> vsim work.TB_PACKETFILE_CTRL
> add wave sim:/tb_packetfile_ctrl/u1/P_clk_in
> add wave sim:/tb_packetfile_ctrl/u1/P_clk_out
> add wave sim:/tb_packetfile_ctrl/u1/Reset
> add wave sim:/tb_packetfile_ctrl/u1/Write
> add wave sim:/tb_packetfile_ctrl/u1/Read
> add wave sim:/tb_packetfile_ctrl/u1/last_block ?????????????????
Article: 64460ALuPin <ALuPin@web.de> wrote in message news:b8a9a7b0.0401050612.5fce329a@posting.google.com... > Some additional question: > Is the shown macro for functinal or for timing simulation ? > The background of this question: When I run the simulation and > open the "signals" window --> ADD WAVE ---> ALL SIGNALS IN DESIGN > I can find the original names of the primary inputs and outputs > but I can NOT find the original internal names, these seem to be > renamed by the compiler. > If I want to analyse a state machine it is impossible without > the original names. > > So my question: How can I simulate (functional) without losing > the original names ? Off the top of my head, open the Structure window (View->Structure) and navigate down through your design hierarchy to find the instantiated component you want. All signal names/state machine states should be available here. When a signal's selected select View->Wave->Selected Signals, it's added to the Waveform window and the command to show it in the waveform window is displayed at the command prompt in the Main window. Signals can also be dragged and dropped into the Waveform window but you don't get the command in the main window. Hope this helps, Nial Stewart ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 64461
Hi folks, I've purchased an FPGA prototyping board with a p160 expansion slot. What sort of connector fits into this slot? Where to get it from? Thanks in advance, HenningArticle: 64462
Kevin, Yopu need a separate BUFG for each. All BUFG resources are matched, so that the skew specs apply at the end of a BUFG, not at the output of the DCM. Austin Kelvin @ SG wrote: > Hi, there: > > Assume my chip uses the CLK180 and CLK90 at same time, does it mean CLK180 & > CLK90 uses > the same global clock tree? Or, do I need to instantiate a BUFG for each of > them? > > Best Regards, > Kelvin > > > >Article: 64463
I haven't used any cores released in the past year, so I'm not sure what the *_i.* stuff is. The rest of this applies to what I learned using it a year ago. The core comes with several ucf and lc files associated to either "core" or "fast". All three files will need to be included in the project. The pcix_fast.* (for 133MHz) stuff requires the use of the *_64xf.*. Use the pcix_core.* for all the other lc and ucf files. All the *_64x*.* stuff only supports PCIX mode. Hence, for a mixed PCI/PCIX, use the *_64s.*. It will only run at 66Mhz, but seems to be much easier to use than the others. You will need to maintain the same structure as in the *top.* file coming from Xilinx if you are going to use their ucf files. Either that or change the paths in your ucf files. I never use FPGA Express, so I'm not sure what additional issues that may cause. "owner" <kanglc@starhub.net.sg> wrote in message news:265f36a.0401041841.14caff4a@posting.google.com... > Hi, > > I am using Xilinx PCI_64_66_CORE Build 106 (04-04-2003) with ISE > 4.2i/FPGA Express/VHDL design flow. When I try to translate, a.k.a. > NGDBUILD, the design, I encounter the following errors: > > ERROR:NgdBuild:393 - Could not find INST(S) > 'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD' > in design 'gefsc_top'. INST entry is 'INST > "PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD" IOB = TRUE ;' > > ERROR:NgdBuild:393 - Could not find INST(S) > 'PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD' > in design 'gefsc_top'. INST entry is 'INST > "PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD" IOB = TRUE ;' > > ERROR:NgdBuild:393 - Could not find INST(S) > 'PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD' > in design 'gefsc_top'. INST entry is 'INST > "PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD" IOB = TRUE ;' > > The error continues for the whole bus width, and for other signals as > well. > I think the ucf file specifies the constraints using "/" to reference > the instance, but the core instantiates in a different way. There is a > file by the name of "pci_lc_i.vhd" which I found the instance > PCI_AD64_IO31_OFD instantiated as: > > PCI_AD64_IO31_OFD : X_FF > port map( > ..... > > Does this mean I have to change the ucf file's constraint statements? > Can anyone in the group who has used xilinx logicore pci64 advice me > on this? > > Any help is greatly appreciated. > > Regards, > LCArticle: 64464
Something else I thought of is to make sure you are using the same compile options as the example that comes with the core. i.e., don't loose your hierarchy, don't balance the registers, don't insert buffers, etc. "owner" <kanglc@starhub.net.sg> wrote in message news:265f36a.0401041841.14caff4a@posting.google.com... > Hi, > > I am using Xilinx PCI_64_66_CORE Build 106 (04-04-2003) with ISE > 4.2i/FPGA Express/VHDL design flow. When I try to translate, a.k.a. > NGDBUILD, the design, I encounter the following errors: > > ERROR:NgdBuild:393 - Could not find INST(S) > 'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD' > in design 'gefsc_top'. INST entry is 'INST > "PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD" IOB = TRUE ;' > > ERROR:NgdBuild:393 - Could not find INST(S) > 'PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD' > in design 'gefsc_top'. INST entry is 'INST > "PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD" IOB = TRUE ;' > > ERROR:NgdBuild:393 - Could not find INST(S) > 'PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD' > in design 'gefsc_top'. INST entry is 'INST > "PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD" IOB = TRUE ;' > > The error continues for the whole bus width, and for other signals as > well. > I think the ucf file specifies the constraints using "/" to reference > the instance, but the core instantiates in a different way. There is a > file by the name of "pci_lc_i.vhd" which I found the instance > PCI_AD64_IO31_OFD instantiated as: > > PCI_AD64_IO31_OFD : X_FF > port map( > ..... > > Does this mean I have to change the ucf file's constraint statements? > Can anyone in the group who has used xilinx logicore pci64 advice me > on this? > > Any help is greatly appreciated. > > Regards, > LCArticle: 64465
Does that cable support the DMA stuff in ISE 6? "Socrat" <socrat@rogers.com> wrote in message news:U87Jb.257021$ea%.18244@news01.bloor.is.net.cable.rogers.com... > Hi, > > JTAG cable , > $25 USD + same day shiping (~$3) > see at > www.seytronix.com > > Regards! > > Seiran > > Sumit Gupta wrote: > > > Hi > > > > Is there is cheap source or alternative to Xilinx parallel cable ? > > > > Also is it leagal to make my own cable (from the schemetic provided by > > Xilinx) and sell it. > > > > Thanks > > Sumit >Article: 64466
Henning Bahr <Henning.Bahr@ncl.ac.uk> wrote: : Hi folks, : I've purchased an FPGA prototyping board with a p160 expansion slot. : What sort of connector fits into this slot? Where to get it from? The prototyping board manual should tell you that the connector is a HIROSE FX2 connector. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 64467
In article <u65fqln2u.fsf@trw.com>, Martin Thompson <martin.j.thompson@trw.com> wrote: >Not quite - Win2K treats the "extra" processor as a whole extra (real) >processor for scheduling purposes. Apparantly the XP scheduler >understands the difference, and schedules things differently - I don't >know what the differences are though. The big difference is in the cache behavior. In an SMP (Symmetric Multiprocessing) two different processors working on the same task will cause coherancy cache misses, as each takes write access from the other for the common working set. In an SMT, two different processes working on different memory will case incoherancy misses, as each process is fighting for its share of a common cache. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 64468
valentin tihomirov wrote:
> I have compiled a design with XSE 6.1i. It produced post-synthesis/fitting
> VHDL model. ActiveHDL 6.1 simulator fails compilation with *Unknown
> identifier "X_ROC"* error.
Consider writing your own vhdl code and
siming it before synthesis.
-- Mike Treseler
Article: 64469C A L L F O R P A P E R S THE TWELFTH ANNUAL IEEE SYMPOSIUM ON FIELD PROGRAMMABLE CUSTOM COMPUTING MACHINES Napa Valley, California April 20 - April 23, 2004 http://www.fccm.org PURPOSE: To bring together researchers to present recent work in the use of reconfigurable logic as computing elements. This symposium will focus primarily on the current opportunities and problems in this new and evolving technology for computing. Contributions are solicited on all aspects of custom computing, including but not limited to: Architecture of reconfigurable computing devices and systems, including coprocessors, attached processors, reconfigurable systems-on-chip and hybrids; Languages, compilation techniques, tools, and environments for programming and run time support; Applications of reconfigurable computing, including the use of reprogrammable logic in mobile communications, network infrastructure and other embedded systems; Implications of nanotechnology and reconfigurable computing on one another, possible forms, system implications, use of reconfiguration to support fault avoidance; Novel use of reconfigurability, including evolvable hardware; Prototyping for system modeling and architecture emulation. SUBMISSIONS: FCCM has a tradition of presenting both full length papers and high quality posters. Authors are invited to send submissions for either full length papers (10 page maximum) or extended abstracts (2 page maximum) for posters by January 19, 2004, to Jeffrey Arnold. Please indicate whether you seek consideration as a full paper or as a poster. Notification of acceptance will be sent by the beginning of March. Final papers and poster abstracts will be due on the first day of the Symposium. The proceedings will be published following the Symposium. Authors are encouraged to submit PDF or Postscript manuscripts by FTP. Format and submission instructions are available on the FCCM web page (www.fccm.org), or authors can contact Jeffrey Arnold (jmarnold@ieee.org). Authors are also encouraged to bring demonstrations of their work. Space will be made available during the demo event to be held Wednesday, April 21. Details will be available on the web page. SPONSORSHIP: The IEEE Computer Society and the Technical Committee on Computer Architecture. CO-CHAIRS: Kenneth L. Pocek Intel Mail Stop RN6-18 2200 Mission College Boulevard Santa Clara, California 95052 Voice: 408-765-6705 Fax: 408-765-5165 kenneth.pocek@intel.com Jeffrey M. Arnold Stretch, Inc. 10686 Mira Lago Terrace San Diego, CA 92131 Voice: 858-547-9257 Fax: 858-547-9010 jmarnold@ieee.org PROGRAM COMMITTEE: Peter Athanas, Virginia Tech. Donald Bouldin, University of Tennessee, Knoxville Duncan Buell, University of South Carolina Michael Butts, Everychip Steve Casselman, Virtual Computer Corp. Katherine Compton, University of Wisconsin Andre DeHon, California Institute of Technology Apostolos Dollas, Technical Univ. of Crete Philip Friedin, Fliptronics Scott Hauck, University of Washington Brad Hutchings, Brigham Young Univ. Tom Kean, Algotronix, Ltd. Phil Kuekes, HP Labs. Philip Leong, Chinese University of Hong Kong Wayne Luk, Imperial College John McHenry, NSA Robert Parker, Institute for Information Sciences Viktor Prasanna, University of Southern California Herman Schmit, Everychip Mark Shand, HP Labs Satnam Singh, Xilinx Stephen Smith, Lochran Roger Woods, The Queen's University of BelfastArticle: 64470
Hi, Were you able to implement the test design that is provided with the core? That design is a good design flow test. Eric owner wrote: > > Hi, > > I am using Xilinx PCI_64_66_CORE Build 106 (04-04-2003) with ISE > 4.2i/FPGA Express/VHDL design flow. When I try to translate, a.k.a. > NGDBUILD, the design, I encounter the following errors: > > ERROR:NgdBuild:393 - Could not find INST(S) > 'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD' > in design 'gefsc_top'. INST entry is 'INST > "PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD" IOB = TRUE ;' > > ERROR:NgdBuild:393 - Could not find INST(S) > 'PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD' > in design 'gefsc_top'. INST entry is 'INST > "PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD" IOB = TRUE ;' > > ERROR:NgdBuild:393 - Could not find INST(S) > 'PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD' > in design 'gefsc_top'. INST entry is 'INST > "PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD" IOB = TRUE ;' > > The error continues for the whole bus width, and for other signals as > well. > I think the ucf file specifies the constraints using "/" to reference > the instance, but the core instantiates in a different way. There is a > file by the name of "pci_lc_i.vhd" which I found the instance > PCI_AD64_IO31_OFD instantiated as: > > PCI_AD64_IO31_OFD : X_FF > port map( > ..... > > Does this mean I have to change the ucf file's constraint statements? > Can anyone in the group who has used xilinx logicore pci64 advice me > on this? > > Any help is greatly appreciated. > > Regards, > LCArticle: 64471
> Consider writing your own vhdl code and > siming it before synthesis. Excuse me, what does this mean? BTW, I have resolved the problem by downloading last version (6.2) of SW from Aldec.Article: 64472
Henning Bahr wrote: > Hi folks, > I've purchased an FPGA prototyping board with a p160 expansion slot. > What sort of connector fits into this slot? Where to get it from? > > Thanks in advance, > Henning The board we have here (Insight-Memec's V2MB1000) also has a p160 expansion slot, we have a communication expansion module that has an ethernet PHY, USB (slave conector), PS2 port, SRAM/Flash memory, and a connector for an LCD display or something. They also have other expansion modules, so you might want to look them up, just Google "Insight-Memec", it should be the first link. -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --Article: 64473
It sounds like either:
a) You have changed one or more instance names within the design hierarchy so
that the paths 'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD' etc. are not valid, or
b) You have allowed the synthesis tool to change the design hierarchy by
flattening or grouping modules.
In my design I used the keep_hierachy XST synthesis attribute to tell XST to
leave the PCI core hierarchy alone when flattening my logic. I also did a
search/replace on the UCF file to change some instance names in the path so that
they match the instance names I wanted to use in my design.
Mark
owner wrote:
> Hi,
>
> I am using Xilinx PCI_64_66_CORE Build 106 (04-04-2003) with ISE
> 4.2i/FPGA Express/VHDL design flow. When I try to translate, a.k.a.
> NGDBUILD, the design, I encounter the following errors:
>
> ERROR:NgdBuild:393 - Could not find INST(S)
> 'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD'
> in design 'gefsc_top'. INST entry is 'INST
> "PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD" IOB = TRUE ;'
>
> ERROR:NgdBuild:393 - Could not find INST(S)
> 'PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD'
> in design 'gefsc_top'. INST entry is 'INST
> "PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD" IOB = TRUE ;'
>
> ERROR:NgdBuild:393 - Could not find INST(S)
> 'PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD'
> in design 'gefsc_top'. INST entry is 'INST
> "PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD" IOB = TRUE ;'
>
> The error continues for the whole bus width, and for other signals as
> well.
> I think the ucf file specifies the constraints using "/" to reference
> the instance, but the core instantiates in a different way. There is a
> file by the name of "pci_lc_i.vhd" which I found the instance
> PCI_AD64_IO31_OFD instantiated as:
>
> PCI_AD64_IO31_OFD : X_FF
> port map(
> .....
>
> Does this mean I have to change the ucf file's constraint statements?
> Can anyone in the group who has used xilinx logicore pci64 advice me
> on this?
>
> Any help is greatly appreciated.
>
> Regards,
> LC
Article: 64474maxlim79@hotmail.com (Maxlim) wrote in message news:<a6140565.0401042045.3d8123f@posting.google.com>... > Hello... > Can anybody tell me that why Nios SDK cant display floating point > datatype if I include excalibur.h as the header file? The C code that > process simple floating point works correctly only if I exclude the > excalibur.h file. The problem occur when I need the software > subroutine for the standand peripherals but I cant display the > processing time if the calculation formula involved floating point. Hi Maxlim, The reason for this is the printf() routine compiled into your library, defined when you include 'excalibur.h' in your C code is a 'small' printf() that does not support floating point numbers to save on space (useful for systems running out of on-chip memory). This is an SDK option that can be switched for printf() that supports floating point. You can disable this small printf routine and use the full-sized one (and still use excalibur.h in your source code) by opening SOPC Builder, editing the Nios CPU settings for your processor, and under "Software" tab, un-checking the "Use small printf" checkbox. After this, re-generate the SDK and re-compile your code; you should now be able to print floating point numbers correctly while including excalibur.h. I just tried a simple test to verify this, so if you have any questions please email me and I'll send you the example. Regards, Jesse Kempa Altera Corp. jkempa at altera dot com
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