Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Thanks to everyone who replied. I think John's comments cover everyone else's ideas, so I will answer here.. "John Retta" <jretta@rtc-inc.com> wrote in message news:2YOTb.11256$uM2.4279@newsread1.news.pas.earthlink.net... > Here are a couple of things to try - > [1] Take a look at the the -u report ... keep adding contraints until > unconstrained paths drop to zero. I will try this. > [2] Take gate level netlist into simulator, and see if there are problems > with simulation. I can't see anything wrong in the simulator... > [3] Make an effort to ensure that all I/O connecting to core are > registered. They are. > Observations - > [1] Trace does a terrific job with synchronous paths, and (answering > your original question), part problems are typically more design problems > (but it sounds like you already accept this .... just looking for some > ideas). Correct. > [2] On the marginal boards, hit with shot of cold spray to see if chips > start to opperate at 50 Mhz. This is problematic as the thing doesn't fail completely when it fails, it rather generates erroneous data once in a while... > [3] The symptom that one board works, but two don't is a little of a > puzzler. That indicates problem may not be in time domain crossings > but rather in synchronous paths which do not meet timing, where > device specific process variations take have an effect. Or it could > also mean there is something marginal at the PWB level .... GND > scheme, decoupling, marginal voltages that push two units under > threshold. (Check VCC levels ...sorry to state obvious) Electrical problems are not likely. I have designed quite a few FPGA boards, many in produciton. This one is not much different from what I did before and it is well decoupled, etc. The voltages are all fine... > [4] Key might be to isolate block that is really failing. Is it really > core? Something like a "signature" analysis on outputs of a block > for periods that result in identical processing are helpful. ie... > Do outputs of block 1 across an identical data set differ among > the "good chip" vs the "bad" devices. I think it is the core, however I can't say that for sure. The board is a decoder of some sort. It acts as PCI bus master and takes data from the host memory and puts into an onboard buffer. Then the core takes it from that memory, decodes and puts into the output buffer memory. Finally, data from the output buffer is DMA'ed into the host memory. What I see is that sometimes data in the board output buffer is slightly corrupted (usually in the LSB of one of a 1000 words). If I simply read my buffer in a loop, the data is always the same, it fails only when run through the decoder. It doesn't fail every time, it can go fine for over 100 cycles sometimes... > [5] If you can over constrain your clock frequency for the entire > design, or just the core, then try place-and-route with modular > aproach, that might give you margin on your synchronous paths. Well, I have several versions, one of them constrained to below 18 ns and still failing. It must be some other unconstrained path or perhaps a different kind of error, but then why it works at 45 MHz?... /Mikhail -- To reply directly: matusov at square peg ca (join the domain name in one word and add a dot before "ca")Article: 65626
I have to make changes to an old legacy product containing an XC4005
part.
I was able to find a set of old XACT tools but the problem is that the
newer
synplify versions infer the primitives IDFX and ODFX. These to
primitives
are NOT included in the XC4000 libriaries and I have not been been
able
to get past the xnfmerge step. I looked at the xnf file and the ODFX
and
IDFX primitives are D-Flip-flops with enable. But when I look at the
logic
there is no enable needed. Syplicity ties the enable to VCC. For
example,
the following proccess,
PROCESS(clk27m)
BEGIN
IF RISING_EDGE(clk27m) THEN
d1data <= d1data_in;
END IF ;
END PROCESS;
gets mapped to the following in the xnf file,
SYM, d1data_in_inff<1>, IFDX, LIBVER=2.0.0
PIN, Q, O, d1_in/d1data<1>
PIN, D, I, d1data_in<1>
PIN, C, I, clk27m_c
PIN, CE, I, VCC
Is there a way to get synplify to infer the IFD primitive (D-flop w/o
enable) instead of the IFDX without making the source vender specific
or hacking the xnf file?? Does
anyone know where I can get older versions of Syplicity synplify (pre
6.0)? Thanks for any info.
Ted
Article: 65627I have no problem in the simulation, her it works as I expected. I have also checked that all source blocks are set to the actual samplings frequency. I seem to be a problem with clocking data in and/or out of the integrator. All other blocks in the model works fine. When I implement the model as symbol file and include it in my quartuss project. /Jacob >>>>> "Hong" == Hong Shan Neoh <hsneoh@netscape.net> writes: Hong> The integrator is based on the equation q=q+d. If it is a Hong> simulation problem in Simulink, make sure your simulation Hong> parameters (i.e. Solver Options, Single tasking mode etc.) and Hong> sampling rate for your source block are set correctly. Hong> There is an design example of a CIC filter which shows you how Hong> the integrator block can be incorporated into your design. The Hong> design is located in the following directory: Hong> <installation_path>\DSPBuilder\designexamples Hong> -HS hneoh@altera.com Hong> Jacob@jacob-s.net (Jacob Sørensen) wrote in message Hong> news:<2n4fzdvoi36.fsf@jacob-s.net>... >> Hi >> >> Just wanted to here if anyone has an idea to what I am doing wrong. >> >> I can not get the integrator and delay components to work in the >> DSP builder. >> >> All the Arithmetic and gates blocks I use, works well, and the FIFO >> storage element workd well too. >> >> Any suggestions are most welcome. >> >> /Jacob -- >> >> Msg. From Jacob Soerensen jacob@jacob-s.net http://jacob-s.net >> >> Nothing in nature is random ... A thing appears random only >> through the incompleteness of our knowledge. Spinoza, Ethics I -- Msg. From Jacob Soerensen jacob@jacob-s.net http://jacob-s.net Nothing in nature is random ... A thing appears random only through the incompleteness of our knowledge. Spinoza, Ethics IArticle: 65628
nmm1@cus.cam.ac.uk (Nick Maclaren) wrote in message news:<bvod25$ke5$1@pegasus.csx.cam.ac.uk>... > In article <17f33635.0402030650.2c88316@posting.google.com>, > digkpk@yahoo.gr (eric) writes: > |> Can anyone help me design a 4 bit divisor using flip flops. I want to > |> design a circuit that devides two BCD numbers (for example 8 / 3 = 2 > |> and 2 for rest). > |> Can anyone helps ? > > This is a FAQ. Collect together a large number of flip-flops in > various colours. Create a pile of (say) pink ones the side of > your divisor, and a pile of (say) blue ones the size of your > dividend. Keep a pile of (say) yellow ones to hand. > > Match up each pink one with a blue one, discard the blue ones, > and put one yellow one in another pile. Then repeat. When there > aren't enough pink ones to match the blue ones, the number of > yellow ones you have collected in the target pile is the quotient > and the number of blue ones left is the remainder. > > Simple, isn't it? > > > Regards, > Nick Maclaren. Are you sure about that? SOunds too simple perhaps you left out a step ot two.Article: 65629
> >> Match up each pink one with a blue one, discard the blue ones, > >> and put one yellow one in another pile. Then repeat. When there > >> aren't enough pink ones to match the blue ones, the number of > >> yellow ones you have collected in the target pile is the quotient > >> and the number of blue ones left is the remainder. > >> > >> Simple, isn't it? > >> > >> > >> Regards, > >> Nick Maclaren. > > > > I'm afraid I must disagree. Mixing pink, blue and yellow would just > > lead to metastability issues. I would go for green, red, and purple. > > And don't forget to clock yourself, it's always a good idea to have a > > fully synchronous design. > > I don't *Think* so. Synchronous clocking of green flip-flops will almost > certainly lead to ground bounce. > > Bob If you really go into the division operation, then it becomes obvious that you may have additions, substractions and shifts. Research has shown that the "grren flip-flop ground bounce problem" typically only occurs during when a "borrow" occurs in a substraction. An elegant solution to the problem has then been suggested: You make sure that you borrow a "pink" flip flop for the duration of that particular substraction. While not proven in theory, no ground bounce have been discovered so far in such a circuit. -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This is a personal view which may or may not be share by my Employer Atmel Nordic ABArticle: 65630
Hi, I am looking at developing high speed (200MHz+) DDR interfaces for Xilinx or Altera devices. I am wondering if people have thoughts on the best tool flows for achieving such designs. More specifically: I think I have a reasonable understanding as to how to do fast pipelined designs as far as core logic goes. My concern is how good are the tools at letting you do low-level I/O design? In order to obtain 200MHz DDR rates (400Mb/s data) the designer needs to pay a lot of attention to actual routing paths. Do the current Altera/Xilinx tools provide this level of flexibility/control? Would I be advised to use 3rd party tools (Mentor, Synplicity, Synopsys etc)? Are these tools good enough for the required static timing analysis, or do I really need to go to Primetime or some other STA tool? Thanks GregArticle: 65631
Valentin, You need to be more specific in terms of what speeds you want to achieve, whether the rate has to be sustained, what kind of compression/encryption, etc... ? /Mikhail -- To reply directly: matusov at square peg ca (join the domain name in one word and add a dot before "ca") "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in message news:bvnv15$uhbvk$1@ID-212430.news.uni-berlin.de... > I would like to accelerate a data conversion task. We just send a stream > of data to converter that produses a response stream. Actually, this > converter is an emulator of a system we are going to simulate efficiently > accelerating simulation task. As the goal is a number of simulations per > time unit, the high performance channels are needed to communicate between > application running on PC and emulator running on FPGA. The data conversion > (encription, compression) should be a known and well-understood toipc; thus, > I would like to see any good reference designs. > As, I do not have any experiance in high-speed I/O, I would like to > discover existing and popular high speed interfaces (DRIVERS, tools, > examples, defign flows, methodologies, cores, etc.). Can anybody offer an > Internet resource or an exellent book describing the topic? How many time > would it take to built a simplest prototype in man-hours (100, 1000, > million)? How costly will it be? > > Many thanks. > >Article: 65632
Tobias, "Tobias Möglich" <Tobias.Moeglich@gmx.net> wrote in message news:401FC8AB.B097B5C2@gmx.net... > WRITE_DSP : process(IOSTRB_DSP) -- Daten > schreiben ins RAM (data -> ram) > begin > if rising_edge(IOSTRB_DSP) then > if CS_DSP = '0' and IORW_DSP = '0' then -- > IORW=0: WRITE; CS and EN are active low > dinb <= data_DSP; > else > dinb <= (others=>'Z'); -- synthetisiert Tristate buffer; > end if; > end if; > end process; From this code it is not clear what the timing relationship between the address bus, write enable, clock and your data when they are all applied to the memory. You have to make sure that your address is stable when you do your write. Have you simulated this? Have you looked with a scope or a logic analyzer? Do you have Xilinx Chipscope? I would suggest starting with simulation if you haven't done so yet... /Mikhail -- To reply directly: matusov at square peg ca (join the domain name in one word and add a dot before "ca")Article: 65633
On 3 Feb 2004 12:17:13 -0800, tfrankli_1@yahoo.com (Ted) wrote: >I have to make changes to an old legacy product containing an XC4005 part. >I was able to find a set of old XACT tools but the problem is that the newer >synplify versions infer the primitives IDFX and ODFX. These to primitives >are NOT included in the XC4000 libriaries and I have not been been able >to get past the xnfmerge step. I looked at the xnf file and the ODFX and >IDFX primitives are D-Flip-flops with enable. But when I look at the logic >there is no enable needed. Syplicity ties the enable to VCC. For example, >the following proccess, > > PROCESS(clk27m) > BEGIN > IF RISING_EDGE(clk27m) THEN > d1data <= d1data_in; > END IF ; > END PROCESS; > >gets mapped to the following in the xnf file, > >SYM, d1data_in_inff<1>, IFDX, LIBVER=2.0.0 >PIN, Q, O, d1_in/d1data<1> >PIN, D, I, d1data_in<1> >PIN, C, I, clk27m_c >PIN, CE, I, VCC > > >Is there a way to get synplify to infer the IFD primitive (D-flop w/o >enable) instead of the IFDX without making the source vender specific >or hacking the xnf file?? Does >anyone know where I can get older versions of Syplicity synplify (pre >6.0)? Thanks for any info. > >Ted You can certainly hack the xnf. Here are some code snippets that should help: Input FF SYM, d1data_in_inff<1>, INFF PIN, Q, O, d1_in/d1data<1> PIN, D, I, d1data_in<1> PIN, C, I, clk27m_c END Output flipflop SYM, MODULE_TOP/SIGNAME1, OUTFF, INIT=R PIN, C, I, CLK_NET PIN, D, I, MODULE_TOP/INT_MSEL0_21 PIN, O, O, MSEL0_21 END Output flipflop with tristate SYM, MODULE_TOP/SIGNAME2, OUTFFT, INIT=S PIN, C, I, CLK_NET PIN, D, I, MODULE_TOP/INT_MSEL0_31 PIN, O, O, MSEL0_31 PIN, T, I, MODULE_TOP/MSEL0_OUT_REG/OE END Philip Freidin FliptronicsArticle: 65634
Sounds like you need to narrow the problem a bit more. Apparently, writing into
the buffer is OK if you can read back data all day without errors. What happens
if you DMA a known test pattern into the host memory? Do you get errors there?
How about if you bypass the 3rd party core, does data trasfer OK then?
If the buffer memory is external to the FPGA, I'd look really closely at the
signal integrity and timing at the RAM interface. Also verify with FPGA editor
that the I/O, particularly all of the I/O to the RAM are in fact registered in
the IOB. Check that you have the appropriate pin slew rates, delays, drive
strength etc on all the pins connecting to the RAM as well as your host. You
need to somehow verify that the problem is occuring in the FPGA and not in the
DMA transfer. I'd suggest putting a test pattern generator or read from
internal memory and checking the DMA'd data to make sure it isn't getting
garbled in the process due to either bus timing or bus collisions.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 65635Austin Lesea wrote: > Jim, > > * > > *.......I have been admonished for commenting on competitors in this > forum. That will have to be left up to others like yourself. > > A careful review of all of the features of St2 will have to be left to > others. > > Perhaps Ray Andraka can comment on their new ALM architecture? > Advantages, disadvantages? One thing that was not obvious in a quick trawl thru their info, was the relative NIOS sizes (Stratix / Stratix II). You'd think that would make a good benchmark, but maybe it's still a 'work in progress' as they tune the SW. Anyone seen actual numbers or NIOS or NIOS II ? -jgArticle: 65636
MM wrote: > Thanks to everyone who replied. I think John's comments cover everyone > else's ideas, so I will answer here.. >> [2] On the marginal boards, hit with shot of cold spray to see if chips >> start to opperate at 50 Mhz. > > > This is problematic as the thing doesn't fail completely when it fails, it > rather generates erroneous data once in a while... Sounds a good idea, you just need to keep the device cold. eg ICE in a aluminium cup, or a peltier cooler, or whole shibang in the freezer.... ( tho local cooling is better, as it focuses on the device ) You can also heat it, and check the error rate degrades further ? -jgArticle: 65637
Andrew Greensted wrote: > Just for anyone who searches in the future. > It seems that TDI and TMS are usually pulled high within target devices, > however externally pulling them high (4.7k) is probably a good idea. TCK > and TDO can be left floating. > > This may help: > http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=11433 > > Andrew Greensted wrote: > >> Hi All, >> I'm building a JTAG chain demultiplexer so I can control 30 identical >> JTAG chains from a single point. >> Can anyone confirm the quiescent (not doing anything) states of the >> JTAG pins; so I know what to hold the pin levels at when a chain is >> not being used. >> I see that TMS, TCK & TDI have internal pull-ups, so would I place a >> logical 1 on these when they're not in use? TDO is easy enough to sort >> out as it just goes high Z. >> >> Many Thanks >> Andy >> > > Making sure TMS stays high is a good idea, because them any glitches on TCK will just keep (or get) the TAP controller in reset state -LasseArticle: 65638
Sorry, I haven't looked much at NIOS since it was first introduced (and even
then it wasn't a down and dirty look).
Jim Granville wrote:
> Austin Lesea wrote:
> > Jim,
> >
> > *
> >
> > *.......I have been admonished for commenting on competitors in this
> > forum. That will have to be left up to others like yourself.
> >
> > A careful review of all of the features of St2 will have to be left to
> > others.
> >
> > Perhaps Ray Andraka can comment on their new ALM architecture?
> > Advantages, disadvantages?
>
> One thing that was not obvious in a quick trawl thru their info,
> was the relative NIOS sizes (Stratix / Stratix II).
> You'd think that would make a good benchmark, but maybe it's still a
> 'work in progress' as they tune the SW.
>
> Anyone seen actual numbers or NIOS or NIOS II ?
>
> -jg
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 65639On 3 Feb 2004 14:36:13 -0800, gcaw99@hotmail.com (gcaw) wrote: >Hi, > >I am looking at developing high speed (200MHz+) DDR interfaces for >Xilinx or Altera devices. I am wondering if people have thoughts on >the best tool flows for achieving such designs. > >More specifically: I think I have a reasonable understanding as to how >to do fast pipelined designs as far as core logic goes. My concern is >how good are the tools at letting you do low-level I/O design? In >order to obtain 200MHz DDR rates (400Mb/s data) the designer needs to >pay a lot of attention to actual routing paths. Do the current >Altera/Xilinx tools provide this level of flexibility/control? Would I >be advised to use 3rd party tools (Mentor, Synplicity, Synopsys etc)? > >Are these tools good enough for the required static timing analysis, >or do I really need to go to Primetime or some other STA tool? I'm doing a lot (40Gb/s total) of 622Mbps I/O in my current Xilinx FPGA design, using XST and STA. The source code is a mix of RTL and instantiated primitives. Each I/O pin is connected to a RPM, and each RPM is LOC'ed in a UCF to a fixed place on the die. (I would have done it all with RPMs in the source code, but I'm using Verilog.) I was getting occasional "bad builds" until I did some hand routing, although there isn't much of that. The hand routes were done in FPGA editor, and copied into a UCF. Regards, Allan.Article: 65640
ligenzhu@vip.sina.com (Li GenZhu) wrote in message news:<639bf299.0402021754.668add44@posting.google.com>... thank all kind friends. Now it is ok, as you say, D is output, so it ought to be D.oe = !CSN. thanks a lot.Article: 65641
hi i would like to know that how can i obtain a vendor id in brief read the value at the base of config space.. I know that we had to write to CONFIG_ADDRESS register and read from CONFIG_DATA register... but how to read that pls help me out and if possible pls mail me small coding to write into config_address and read for config_data and obtain base of config space and and obtain vendor id i would be really greatfull to you thanksArticle: 65642
hmmmmmm that question was something to cheer up , all the guys working late in the night !! was it? seems everyone got amused by the pink , red and yellow flip flops, but personally i prefer the white ones. Bob Stephens <stephensyomamadigital@earthlink.net> wrote in message news:<137ymslajcfhu$.1nbv3o07c57ws$.dlg@40tude.net>... > On Tue, 3 Feb 2004 17:44:18 +0100, Giuseppe³ wrote: > > > "eric" <digkpk@yahoo.gr> ha scritto nel messaggio > > news:17f33635.0402030650.2c88316@posting.google.com... > >> Can anyone help me design a 4 bit divisor using flip flops. I want to > >> design a circuit that devides two BCD numbers (for example 8 / 3 = 2 > >> and 2 for rest). > >> Can anyone helps ? > >> > >> Thanks a lot > >> > > Can you evitate the crosspost ? > > It's not in netiquette and I'm very angry to download the same message a lot > > of time. > > > > Thank you > > Giuseppe > > Eschew obfuscation! > > BobArticle: 65643
On 3 Feb 2004 18:42:59 -0800, the renowned s_sajan_s@yahoo.com (Sajan) wrote: >hmmmmmm >that question was something to cheer up , all the guys working late in >the night !! was it? >seems everyone got amused by the pink , red and yellow flip flops, >but personally i prefer the white ones. Here are some colored flip-flops that can brighten the lab late at night. http://www.deelights.co.uk/flipflops.jpg Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.comArticle: 65644
On Tue, 3 Feb 2004 17:44:18 +0100, "Giuseppe³" <miaooaim.REMOVETHIS@tiscali.it> wrote: > >"eric" <digkpk@yahoo.gr> ha scritto nel messaggio >news:17f33635.0402030650.2c88316@posting.google.com... >> Can anyone help me design a 4 bit divisor using flip flops. I want to >> design a circuit that devides two BCD numbers (for example 8 / 3 = 2 >> and 2 for rest). >> Can anyone helps ? >> >> Thanks a lot >> >Can you evitate the crosspost ? >It's not in netiquette and I'm very angry to download the same message a lot >of time. > >Thank you >Giuseppe > Get a better news reader. A good one d/l's the message only once, keeping tabs on the message id so if you see it in one group it won't show in the others unless you tell it you want to. - YD. -- Remove HAT if replying by mail.Article: 65645
Hi Greg, You can achieve 200 Mhz (400 Mb/s) DDR in Stratix, Stratix GX, and Stratix II devices. Stratix incorporates dedicated routing and registers for DDR interfacing, which takes the guess work out of the routing part of a DDR design. You can successfully develop your own DDR interface with Quartus and any synthesis tool (or integrated synthesis), and you do not require 3rd party STA for this. However, if you choose to go this route (rather than using an IP core), I would carefully read all available documentation on DDR and it probably wouldn't hurt to talk to an Altera FAE. They can provide you with guidance to help you properly analyse your DDR timing using Quartus. We also provide the DDR SDRAM MegaCore, an IP block you can integrate into your design to further simplify the process of interfacing to DDR memories. The MegaCore is available for free evaluation on the Altera web site. There are also links to 3rd party IP cores that provide DDR interfacing capability. Some references for you: DDR I/O Signaling in Stratix & Startix GX Devices: http://www.altera.com/literature/hb/stx/ch_8_vol_2.pdf DDR SDRAM Controller MegaCore http://www.altera.com/products/ip/iup/memory/m-alt-ddr_sdram.html Regards, Paul Leventis Altera Corp. "gcaw" <gcaw99@hotmail.com> wrote in message news:6eb2ad89.0402031436.538c8318@posting.google.com... > Hi, > > I am looking at developing high speed (200MHz+) DDR interfaces for > Xilinx or Altera devices. I am wondering if people have thoughts on > the best tool flows for achieving such designs. > > More specifically: I think I have a reasonable understanding as to how > to do fast pipelined designs as far as core logic goes. My concern is > how good are the tools at letting you do low-level I/O design? In > order to obtain 200MHz DDR rates (400Mb/s data) the designer needs to > pay a lot of attention to actual routing paths. Do the current > Altera/Xilinx tools provide this level of flexibility/control? Would I > be advised to use 3rd party tools (Mentor, Synplicity, Synopsys etc)? > > Are these tools good enough for the required static timing analysis, > or do I really need to go to Primetime or some other STA tool? > > Thanks > > GregArticle: 65646
> i would like to know that how can i obtain a vendor id in brief read > the value at the base of config space.. > > I know that we had to write to CONFIG_ADDRESS register and read from > CONFIG_DATA register... > but how to read that Can you elaborate on what you are trying to do here? Are you using Xilinx PCI LogiCORE? If so, you can use the ping example which is included with core zip file. In the ping example's simulation file "stimulus.v/vhd", there are tasks (Verilog)/procedures (VHDL) for configuration reads/writes. You should be able to use these in testbench to access configuration space. Device ID and Vendor ID are in configuration space at address 0x00. Refer PCI specification or Xilinx PCI User guide. -VikramArticle: 65647
Ray, "Ray Andraka" <ray@andraka.com> wrote in message news:40203839.C3B40A67@andraka.com... > Sounds like you need to narrow the problem a bit more. Apparently, writing into > the buffer is OK if you can read back data all day without errors. What happens > if you DMA a known test pattern into the host memory? Do you get errors there? > How about if you bypass the 3rd party core, does data trasfer OK then? I have done a lot of tests with regards to the memories and I am pretty sure that part works. However not everything I can try easily. Bypassing the core sounds like a good idea, but I can't do it in the exisiting design. Input and output data formats are different and that would require quite a bit of redesign. What I verified was access to the input/output buffers from the host side. DMA is irrelevant because when an error happens the content of the board and host buffers is always the same. It doesn't matter whether the buffer is read with single PCI target reads or if the DMA is used. And, yes, you can read this buffer for all day long with the same result. Everything seems to point towards the block, which actually puts data in the buffer, i.e. the core... > If the buffer memory is external to the FPGA, I'd look really closely at the > signal integrity and timing at the RAM interface. The memories are internal. The only external part is a PCI bridge. /Mikhail -- To reply directly: matusov at square peg ca (join the domain name in one word and add a dot before "ca")Article: 65648
I have had to define a data type to deal with logarithmic values. It's
basically a real number ranging from -10000 to 10000. However, I would like
to use this user-defined data type in the entity of the device, i.e. given
the user-defined type is called llrValue, the architecture port would be
ENTITY sova_decoder IS
PORT (
Approiri : IN llrValue
)
Where do I define the data type such that it would be recognised once it
appears in the entity? Or is there some other way to do this?
cheers
--
- Kwaj
http://alpha400.ee.unsw.edu.au/~p3015094
Article: 65649<CUT> > > Get a better news reader. A good one d/l's the message only once, > keeping tabs on the message id so if you see it in one group it won't > show in the others unless you tell it you want to. > > - YD. > Which kind of NewsReader do you to suggest or you are using? Thank you Giuseppe
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z