Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:oNQXb.25656$Ga6.6930@newssvr25.news.prodigy.com... > Clark Pope wrote: > > > performance. The ADC clock is 56 MHz. The source clock will be 8MHz so I > > need 7x in the DCM. > > > The DCM won't work with an input frequency of 8MHz. The minimum input is > somewhere around 24MHz. > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > FCS, how many times does someone say this on here? If you use the CLKFX output you can use input frequencies down to 1MHz, as long as the output frequency is over 24MHz. The OP's system will work, but it'll be jittery. Use the jitter calculator on the Xilinx website to find out how jittery. cheers, Symsx.>Article: 66301
HI,
I am seeing a design left from my colleague and I see he set
conflicting timing constraints like this,
1) On a 100MHz data path, he used a DCM and set the parameters so
that CLKFX runs at 56MHz.\
2) In UCF, he defined the constraint for CLKFX like this,
NET "clk_fx" PERIOD = 27.8 ns HIGH 50 %;
These 2 things conflict with each other, does UCF always takes
precedence? That's my guess, but I also see some other conflicting
constraints like this, it seems not always this way.
In another words is there any good reason to do design like this?
Generate a clock and in UCF override it?
Thanks.
Article: 66302On Mon, 16 Feb 2004 16:22:27 -0000, "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote: >"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message >> On Mon, 16 Feb 2004 10:16:17 -0000, "Jonathan Bromley" wrote: >> >hi PLD gurus - especially those with grey hair :-) Check, I got the grey hair (so does Bob and Peter) >> If for some reason Philip Freidin doesn't see your post, send him an >> e-mail. No need, here I am >OK, I give in. Is there some kind of ex-AMD conspiracy >going on here? I already know that Peter Alfke was with >AMD for a while; Bob, unless I'm much mistaken, I attended >your presentation on proposals for the 29050 CPU at an AMD >FAE meeting; now you tell me about Philip Freidin... Will >all those who are *not* AMD alumni please stand up? :-) Yes, there is a conspiracy. Live with it. >He was the father of the 29PL141. As it turns out, I was the step father of the 29PL141, which I inherited from Arthur Khu (also now at Xilinx), when AMD had one of its quarterly company wide reorganizations. The 29PL141 was born in the PAL group, and I believe Arthur and Om Agrawal were the real parents. I was the product planning manager for microcoded products (29xx (bit slice) and 293xx (word slice)) and the powers that be felt that it belonged with the other microcoded products. There were several other family members: 29PL142, 29CPL151, 29CPL142, 29CPL153, 29PL144, 29CPL154, 29BCPL164. I was father or co-father of these. >For a fun project, and also on behalf of someone who >asked me about it, I was hoping to mimic the functionality >of the AMD 29PL141 programmable state machine (vintage ~1988) >in an FPGA of some kind. But my old copy of the '141 data sheet >has gone missing, probably lost in one of my rare and often >disastrous domestic-rubbish purges. > >Does anyone have a copy, somewhere in their archives, that they >could let me see by some means or other? There doesn't seem >to be a copy of it anywhere on the web, which is not surprising >because it wasn't very long-lived and it was POPped (*) long >before the days of web-published data sheets. I have a spare copy of the Am29PL100 handbook that contains detailed info on the architecture, and applications examples. It has pretty much everything ever published about the products, except the data sheet. I'll gladly send it to you if you pay the postage. Separately, I have emailed you a copy of the assembler and simulator, and the text files that go with them. Maybe that is sufficient for your project. Philip Philip Freidin FliptronicsArticle: 66303
>I believe Arthur and Om Agrawal were the real parents. I was the product >planning manager for microcoded products (29xx (bit slice) and 293xx Interesting timing. Due to another thread, I pulled out an old board to check the date code on a XC3020. It says 8833 That board has a 29C116 - a nice chip for I/O controllers that need some smarts to follow control blocks and such. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 66304
> FCS, how many times does someone say this on here? If you use the CLKFX > output you can use input frequencies down to 1MHz, as long as the output > frequency is over 24MHz. The OP's system will work, but it'll be jittery. > Use the jitter calculator on the Xilinx website to find out how jittery. > cheers, Symsx.> Right you are. I assumed a couple of things here. One, that he needed this 8MHz input clock for the rest of the logic. Of course, you could use more than one DCM. No problems there. Jitter for a CLKFX-only implementation is about 0.9ns from 8MHz to 56MHz. This would affect the SNR performance (due to aperture uncertainty) attainable by an otherwise good ADC. I assumed that this would not be acceptable and, therefore, the CLKFX option would not be available. I would choose to go with a high quality 56MHz clock and divide it down for internal FPGA logic, if required. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 66305
Hi Tushit,
In Quartus II 4.0 try setting the following Logic Options:
a) Auto Packed Registers : to either Minimize Area or Minimize Area with
chains. This is set in the Assignment Settings->Fitter Settings->More
Settings Dialog:.
b) Optimization Technique is set to Area. This is set in the Assignment
Settings->Analysis and Synthesis settings.
- Subroto Datta
Altera Corp.
"tushit" <tushitjain@yahoo.com> wrote in message
news:ec6aab0.0402152209.5f58efb6@posting.google.com...
> Hi,
> I have a design which does not fit on my Altera Stratix device. I need
> to split it onto 2 Stratix devices. Is it possible to manually do
> this? I can't afford a partitioning software. The clock frequency for
> the design after fitting will be around 30MHz and I can run the design
> at a speed slower than that achieved after fitting.
> So can I safely operate the design at say 20Mhz if Quartus was to
> ensure a speed of 30Mhz on a single larger FPGA? Slowing the FPGA by
> 10 MHz would mean I have an extra 100ns delay which will be used up by
> the interconnect delay between the 2 FPGAs(due to rise time/fall time
> of IO pins). Assuming this approach works, approx. how much extra
> delay should I leave for the interconnect delays? Are there any other
> issues I should be aware of?
> Thanks
> Tushit
Article: 66306On Mon, 16 Feb 2004 16:23:28 -0700, QiDaNei <qidanei__2@hotmail.com> wrote: >HI, > I am seeing a design left from my colleague and I see he set >conflicting timing constraints like this, > 1) On a 100MHz data path, he used a DCM and set the parameters so >that CLKFX runs at 56MHz.\ > 2) In UCF, he defined the constraint for CLKFX like this, > NET "clk_fx" PERIOD = 27.8 ns HIGH 50 %; The period for a 56MHz clock is 17.85 ns . If he really wrote 27.8, then it is plain wrong. Or maybe you mistyped the value. > These 2 things conflict with each other, does UCF always takes >precedence? That's my guess, but I also see some other conflicting >constraints like this, it seems not always this way. Actually, they do not conflict. Period is the reciprocal of frequency, the time from one rising edge to the next rising edge (or falling to falling). The HIGH 50% just says that the CLKFX is symmetrical, 50% high time, 50% low time. Usually not an issue unless you are using both edges of a clock. > In another words is there any good reason to do design like this? >Generate a clock and in UCF override it? The UCF (and also your design files VHDL/Verilog/Schematic) can all contain both parameters and constraints. Although they look the similar, they behave differently. As you wrote above (1) there are parameters that set the DCM CLKFX to be 56MHz. unless there are errors in the parameter value, or the input is not really 100MHz, the CLKFX output will be 56MHz. Parameters specify the operating mode of various functions on the FPGA, as well as the initial conditions of other parts of the FPGA (such as initial value for a flip flop, or ROM contents, or initial RAM contents). As you wrote above (2) there are timing constraints. These constraints (and there are many variants) are goals being set for the place and route software to meet. They do not affect the logic being built, but do affect how the logic is placed and routed. (There is a special case of signal replication for reducing net loading, but the functional result is the same logic). In this case, the PERIOD constraint is wrongly telling the router that it can have path delays of up to 27.8ns between synchronous elements that are both clocked by the clk_fx net. The router will stop trying to make these paths any faster, once these paths are less than or equal to 27.8 ns. The design will almost certainly fail. Constraints that occur in the UCF override constraints that occur in the design files. >Thanks. Philip Philip Freidin FliptronicsArticle: 66307
> Right you are. I assumed a couple of things here. One, that he needed this > 8MHz input clock for the rest of the logic. Of course, you could use more > than one DCM. No problems there. > > Jitter for a CLKFX-only implementation is about 0.9ns from 8MHz to 56MHz. > This would affect the SNR performance (due to aperture uncertainty) > attainable by an otherwise good ADC. I assumed that this would not be > acceptable and, therefore, the CLKFX option would not be available. I would > choose to go with a high quality 56MHz clock and divide it down for internal > FPGA logic, if required. > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian Martin, Good points, your suggestion of using a good 56MHz source and a divided down enable for the 8 MHz functionality is the way I'd go too. Cheers, Syms.Article: 66308
> So what do I need to do to get 'rst' connected to the GSR > net? > > I've spent a fair bit of time searching the Xilinx site/docs > and googling this group with no results. It seems to be one > of those things that I should probably know, but just can't > find anywhere. > > Thanks for any pointers, > > Nial. > Hi Nial, Can you instantiate the STARTBUF_SPARTAN3 design element? Listed under STARTBUF_architecture in the Design Elements section of the Libraries guide. Cheers mate, Syms. p.s. I see Mr.Easton's expecting again! There should be a law against it!Article: 66309
>I wonder about this because I'm looking into moving data across device >boundaries for a project. The approach I am favoring at the moment is to >have a source-synchronous bus + control + clock leave device A and enter >device B. The output clock would be generated via DDR method within the >IOB. It would seem to me that --assuming careful PCB layout-- this method >might be preferable to having an external clock generator feed devices A and >B. >Am I missing something? I can see that with proper DCM configuration it >truly doesn't matter which way you go (or it shouldn't)? I think one important idea is to use an approach that you are comfortable with. What is "best" probably depends upon details that haven't been specified yet. What are you going to use for the main clock on device B? Can you run the whole chip off the source-synchronous clock, or does it need to run off a normal clock, in sync with device A. If the latter, then you need a FIFO or such to get across the clock boundary. How fast are you running? Can you afford pipeline delays? Will it work if you put a pipeline stage at the output IOBs and another at the input IOBs? If things are slow enough so that works, it avoids the clock re-sync tangle. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 66310
On Mon, 16 Feb 2004 11:50:38 -0500, "MM" <mbmsv@yahoo.com> wrote: >"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in >message news:c0qnad$1ac2h2$1@ID-212430.news.uni-berlin.de... >> The planned architecture: >> telephone line -> ADCs (8k samples pre second)-> FPGA (samples into >> ram) -> AXIS controller (with Ethernet) > >I've never designed telephone stuff, but considering the speeds and speech >quality requirements I think you can get away with a single A/D and an >analog mux at the input. There are some A/D chips with the mux onboard. I'm not sure whether "telephone line" means "globally compliant POTS line" or "something that will connect to a phone across the office". If it is the former meaning, it is a requirement to support a number of different complex termination impedances. This may be done by changing analog components in the line hybrid, or it may be synthesised digitally (by feeding a filtered version of the ADC signal back to the DAC) with different filter taps for each market. The latency of the ADC & DAC matters a lot! This may rule out a multiplexed approach, and will almost certainly rule out standard "PC" type codecs (which have large latency). Note that some customers may expect to be able to connect V.90 type modems to what is nominally an audio line. IIRC, this requires at least 14 bits of accuracy prior to mu/A law companding. There's a large market for phone line connection devices, so it's not all that hard to find codecs designed for the task, e.g. AD73322L Regards, Allan.Article: 66311
I forgot to mention: All INITbar outputs are connected together, with a 1 kilohm pull-up resistor, and hold the SPROM reset while that common pin is Low. This guarantees that all chips wait for the slowest device to come out of power-on reset (POR) Peter Alfke. Peter Alfke wrote: > > One of the V2P7 chips is the master and drives CCLK to the SPROM and to > the other V2P7s, the other seven V2P7s must be in slave serial mode and > receive CCLK. Al Din pins are tied together and thus receive the same > bitstream from the SPROM.. > > Peter Alfke > > Adarsh Kumar Jain wrote: > > > > Hi, > > I am trying to configure 8 Virtex 2 Pros (V2P7) (with the same bitstream) on > > a single board. > > I will use the the Master Serial programming mode. > > Are there known issues which i need to worry about ? > > Any documentation available ? Prior Experience ? > > Thanks in advance, > > AdarshArticle: 66312
"Yttrium" <Yttrium@pandora.be> wrote in message news:<sSNXb.2451$hs5.60476@phobos.telenet-ops.be>... > wo when i have 0.002100205514 as a coefficient i enter it in the COE > file as 2100205514 with the radix=10 and the width as i want it to be > (with changing the coefficient to the size that it can fit the width!)? > > greetings, > > Yttrium > > > <ccon> wrote in message news:ee82680.2@WebX.sUN8CHnE... > scale your numbers to integer, the coef width depends on the > resolution(decimal points)you wish. > -- yup, it's something like that, and it also depends on max/min range of your coefficients. For the number in your example you will need 32 bit coe, and if your coef is signed you will need 1 more bit. In practical you may reduce your resolution to fit in smaller device. Generally speaking, you may ask yourself what kind of device you can afford? what is your data width? howmany taps? and what kind of FIR?...Article: 66313
On Mon, 16 Feb 2004 11:59:02 -0700, "Davka" <mygarbagepail@hotmail.com> wrote: >I just read the online RTX2010 manual. Does the RTX2000 also >have the multiply-and-accumulate logic? No. >Do people buy these chips nowadays for DSP? The main use of the RTX2xxx was in rad-hard satellite applications. The key feature of the family is interrupt response. Stephen -- Stephen Pelc, stephenXXX@INVALID.mpeltd.demon.co.uk MicroProcessor Engineering Ltd - More Real, Less Time 133 Hill Lane, Southampton SO15 5AF, England tel: +44 (0)23 8063 1441, fax: +44 (0)23 8033 9691 web: http://www.mpeltd.demon.co.uk - free VFX Forth downloadsArticle: 66314
Tobias Möglich wrote: > Hello, > > I use Xilinx Chipscope for ISE 6.1. > My question. What's the sample rate. I couldn't find any documentation > about it. The ILA-core has a clock input. The data is then sampled on the rising or falling edge (depending on how you set it up) of that clock. Usually you just pick the fastest clock signal in your design for that. > If I use a fast clock signal in my design, I do have to use a big sample > rate, isn't it ? > Otherwise I won' get the exact result. Right? Basically yes. In ChipScope this is - at least most of the time - nothing you have to worry about, since the clocks to update the signals and to sample them are the same. The only thing you should take care of is that the sample clock is synchronous to the signals you want to analyze. -- Sean Durkin Fraunhofer Institute for Integrated Circuits (IIS) Am Wolfsmantel 33, 91058 Erlangen, Germany http://www.iis.fraunhofer.de mailto:23@iis.42.de ([23 , 42] <=> [durkinsn , fraunhofer])Article: 66315
Following link may help: http://www.tinyboot.com/cd16 A synthesizable 16-bit CPU with development tools, FORTH compiler and CPU for FPGA with best regards, Peter Seng ############################# SENG digitale Systeme GmbH Im Bruckwasen 35 D 73037 Göppingen Germany tel +7161-75245 fax +7161-72965 eMail p.seng@seng.de net http://www.seng.de ############################# "Davka" <mygarbagepail@hotmail.com> schrieb im Newsbeitrag news:T%XXb.70$pM3.121810@news.uswest.net... > I want to bring my knowledge about Forth processors up to date, so I'm > posting some questions. > > Who is currently selling Forth processors? > > What happened to forthchip.com? > > Is there a community that is actively involved in discussing and/or > developing FPGA-based Forth chips, or more generally, stack > machines? > > Has anyone done any substantial DSP work in Forth? Are there libraries > of code available? > > How about hardware Forth implementations that include dedicated DSP > hardware? > > Thanks in advance! > > -- > > Davka > >Article: 66316
"Davka" <mygarbagepail@hotmail.com> wrote in message news:<Yp8Yb.46$sG5.38559@news.uswest.net>... > I just read the online RTX2010 manual. Does the RTX2000 also > have the multiply-and-accumulate logic? > > Do people buy these chips nowadays for DSP? The 2000 and 2001 were the same except for lower price and power on the 2000 the single cycle multiply on the 2001. (I hope I didn't reverse the 2000/2001 models) and the 2010 was popular for aero-space applications because of the rad-hard model despite the very high price tag. Harris switched production from 2000/2001 to 80C286 because the CMOS 286 was popular for laptops at the time and had a larger market. That gives you an idea how long ago Harris moved on from the RTX-2000/2001 production. They continued to produce 2010 for a long time in limited quantity but it is no longer in production either. RTX was done in standard cell technology but it was so long ago that the original patents have expired so one can make knock offs today. Best WishesArticle: 66317
Hi ken, Could you please tell me whether the phase problem that you had mentioned between sdram clock and cpu clock will be reflected in timing simulation? I had done the timing simulation with micron SDRAM instantiated in the testbench. Read and write operations are proper. But the same is not working in virtex2 FPGA board.could you please give some suggestions to improve testing? kamsArticle: 66318
Nice to see someone trying to use an ETRAX. I had a look at your (employers?) web site and the project looks interesting. Nice move to use the ETRAX MCM. Should make for a small footprint. For you others reading this it might be somewhat interesting to have a look at http://developer.axis.com to see the ETRAX. And no, I do not work for Axis. (anymore:) /Ulf Andersson "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in message news:c0qnad$1ac2h2$1@ID-212430.news.uni-berlin.de... > The planned architecture: > telephone line -> ADCs (8k samples pre second)-> FPGA (samples into > ram) -> AXIS controller (with Ethernet) > > The goal is to tap several (about 8) telephone channels and convert them > into TCP/IP stream. TCP server will run on Axis controller. I consider to > use FPGA for polling ADCs and storing samples into Block RAM. When FPGA > buffers are say 50% full, the FPGA would interrupt the controller. AXIS runs > at 100MHz. The interrupted controller would address FPGA by address bus and > reads all samples from FPGA memory. I think 1 kbyte sample buffer would be > enaught for an audio channel. > > I'm new to this filed and want to ask whether the architecture choosen is > feasible? Which FPGA families suit better for the task? > > AXIS is a risk processor; I'm thinking to implement addressing scheme where > there is an address for each audio channel. That is, any two sequential > reads from the same address would read two sequential samples from FPGA. It > it normal solution? > > Thanks, any references are highly appretiated! > >Article: 66319
Telephone line is that one where you connect your phone at home and office. FPGAs require an EEPROM; may be CPLD + dual-port RAM buffer is better for the 100MHz interface than one FPGA?Article: 66320
Hi ken, Could you please tell me whether the phase problem that you had mentioned between sdram clock and cpu clock will be reflected in timing simulation? I had done the timing simulation with micron SDRAM . Read and write operations are proper. But the same is not working in virtex2 FPGA board.could you please give some suggestions to improve testing? jenniArticle: 66321
> There's a large market for phone line connection devices, so it's not > all that hard to find codecs designed for the task, e.g. AD73322L What is analog front-end? The datasheet gives idea, this is ADC/DAC device with capability of mixing input and output audio. Datasheet states it can be used in telephony applications indeed. Does it mean the chip can be used as hybrid function (DAA) directly connecting to telephone line Tip and Ring wires? Do we still need PLD to tranfer data to a powerful system for storing or TCP/IP conversion? Thanks.Article: 66322
"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:c0q5c8$8ar$1$8302bc10@news.demon.co.uk... > hi PLD gurus - especially those with grey hair :-) Thanks to everyone for the entertaining and helpful responses. Much appreciated. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 66323
IOBs can be used as general resource and the tools can make use of these resources. Try the switch "USE BONDED I/OS" in the P&R properties to see if that makes your issue go away. John Adair Enterpoint Ltd. This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Tobias Möglich" <Tobias.Moeglich@gmx.net> wrote in message news:4030F01F.92CDA398@gmx.net... > Hello > > I use Xilinx ISE 6.1 for synthesis. > I discovered in the floorplanner that there are used very much IOB's. > Even more than used IO pads. > Why that ?? Is it for the reason of timing constraints (for example > delays)?? > As far as I know, I haven't made any timing constraint in my design. > Is it possible not to use so many IOB's. > How can I tell ISE to do so ? > > > Greatings Tobi. >Article: 66324
"Symon" <symon_brewer@hotmail.com> wrote in message news:c0rrgi$1b7t8e$1@ID-212844.news.uni-berlin.de... > > > So what do I need to do to get 'rst' connected to the GSR > > net? > > > > I've spent a fair bit of time searching the Xilinx site/docs > > and googling this group with no results. It seems to be one > > of those things that I should probably know, but just can't > > find anywhere. > > > > Thanks for any pointers, > > > > Nial. > > > Hi Nial, > Can you instantiate the STARTBUF_SPARTAN3 design element? Listed under > STARTBUF_architecture in the Design Elements section of the Libraries guide. > Cheers mate, Syms. Symon, that doesn't do it. The STARTUP_SPARTAN3 module allows you to drive the GSR net from an user defined source but this reset mechanism isn't visible to HDL so simulations won't work. The STARTBUF_SPARTAN3 module does the same thing, but with an output you can connect to your HDL reset lines which mirrors the GSR net. Thus simulations should match real life. This doesn't help me tie my top level 'rst' net to the GSR. I've checked through my design and _all_ my asynch reset declarations use this net with the correct polarity. Any more ideas? Nial.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z