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>I suspect that the difficulty for just about any home grown processor is going to be the tools to compile the >code for it, although folks who are more saavy than I on the software side might argue that the high speed >hardware design is the hard part. How much code are you writing? Would you be willing/happy to do it in asembler? Assemblers can be pretty simple, especially if the target is raw binary running at loaded at 0 rather than something needing linkers and libraries. Also helps if the target is RISC and doesn't have messy addressing modes. How much would a reasonably clean sample assembler help? There should be a good example from the academic world. Just type in the new opcode table. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 66601
The low complexity is why I chose the architecture I did. Unfortunately, I did that design in schematics, before
I started using VHDL, so resurrecting it at this point involves more time than can devote to it.
john jakson wrote:
> The HW part is more fun though. The 1802 takes me back, not bad in a
> twisted sort of way, it certainly used very little logic, I had it
> under a scope at Inmos.
>
> Regards
>
> johnjakson_usa_com
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 66602ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0402222358.3471f206@posting.google.com>... > Hi, > > I tried to compile the code presented some days ago in this newsgroup. > I use Altera QuartusII v3.0 SP2 > > and got the following warning: > > Warning: VHDL Subtype or Type Declaration warning at > numeric_std.vhd(878): > subtype or type has null range Switching left and right bound of > range. > > Was does that mean? > > > Apart from that I get the Info > "No valid register-to-register paths exist for clock Clk" > > What does go wrong with timing calculation? > > Rgds > > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > entity barrelshifter is > port( Quantity : in unsigned(31 downto 0); > Amount : in unsigned(4 downto 0); > Reset : in std_logic; > Clk : in std_logic; > Output : out std_logic_vector(31 downto 0) > ); > end barrelshifter; > > architecture ro_lft of barrelshifter is > signal rotated : std_logic_vector(31 downto 0); > signal rotate_by : unsigned(4 downto 0); > > begin > rotate_by <= Amount; > > process (Clk) > begin > if Reset='1' then > rotated <= (others => '0'); > elsif clk = '1' and clk'event then > rotated <= std_logic_vector(shift_right(quantity,to_integer(unsigned(rotate_by)))); > end if; > end process; > > Output <= rotated; > > end ro_lft; Hi, The first message should just say Warning: VHDL Subtype or Type Declaration warning at numeric_std.vhd(878): subtype or type has null range The remainder of the message is incorrect. The reason that the message occurs is that numeric_std deliberately declares a constant with a null range to return as an error condition from some of its functions. There appears to be only one set of registers in the design, so there are no register-to-register paths, only clock-to-input and clock-to-output (Tsu and Tco) paths. - Subroto Datta Altera Corp.Article: 66603
"Hal Murray wrote: >>I suspect that the difficulty for just about any home grown processor is going to be the tools to compile the >>code for it, although folks who are more saavy than I on the software side might argue that the high speed >>hardware design is the hard part. > > > How much code are you writing? Would you be willing/happy to do it in asembler? > > Assemblers can be pretty simple, especially if the target is raw binary running > at loaded at 0 rather than something needing linkers and libraries. Also helps > if the target is RISC and doesn't have messy addressing modes. > > How much would a reasonably clean sample assembler help? There should be > a good example from the academic world. Just type in the new opcode table. "AS" from Alfred Arnold is a good wide-cores assembler, with a choice of Pascal or C sources : http://john.ccac.rwth-aachen.de:8000/as/download.html And HLA (High Level Assembler) is currently x86 only, but the front end, and approach is much closer to higher level languages (but minus the bloat). V2 will allow different back ends, for opcode outputs. Worth watching. http://webster.cs.ucr.edu/AsmTools/HLA/index.html This is able to support quite large code efforts, and remain close to the iron.. A benefit of working from the 'best assembler' end, is the ease of support multiple/tiny core instances - which is one of the advantages of such soft cores. -jgArticle: 66604
Hi,
Which version of EDK are you using? The basic floating point support has
been existing for quite some time. I checked with EDK 6.1 SP2 and the
addition mentioned in this email does work.
Sid
King wrote:
> Dear all,
>
> I am trying to do floating point addition, subtraction, multiplication
> and division in Microblaze.
>
> According to the specification, it is possible to do so as EDK
> included the required library automatically
>
> But after verifying that the library libc.a, libm.a and libxil.a are
> included and math.h is also included in the source C program, I still
> cannot perform the calculation.
>
> float a=6.4;
> float b=7.2;
> float c=3.4;
>
> printf("%f, %f, %f", a,b,c);
> c=a+b;
> printf("%f, %f, %f", a,b,c);
>
> i can print out the result correctly the first time, but in the second
> time, the value of c becomes 0? 00000000...
>
> Is there any more stuff I need to do to solve the problem.
>
> Thanks
Article: 66605
Dear all
My research is about FPGA delay fault testing. I want to verify my
methodology and have to manually configure FPGA as I wish. I want to
experiment on Xilinx Spartan Series FPGA(XCS10). Is there any program
or design flow to help me?
Thank you~!
Jeremy
Article: 66606Torsten, what do you mean by "Free" ? on the link there is notice "if interested please contact using a form" - there is no reference to any form or download location or conditions. so what it is all about? also the website says the ref design uses Spartan III not IIE ? antti www.openchip.org "Torsten Lauter" <tlau@infotech.tu-chemnitz.de> wrote in message news:c1d6q4$blt$1@anderson.hrz.tu-chemnitz.de... > Free PCI-bridge in VHDL for Spartan-IIE > > Somebody knows the implementation of > http://www.infotech.tu-chemnitz.de/~tlau/pci_bridge > > Regards. > __________________________________________________________________ Torsten > Lauter ICQ#: 14492119 Current ICQ status: + More ways to contact me > __________________________________________________________________ > >Article: 66607
Hi, everybody: I am using ISE6/XST flow. Now in gate-level simulation I faced setuphold timing error...My clocks are odd because they are gated then fed into a global clock buffer... Is there any constraints which set the maximum clock uncertainty to all the registers in this clock domain? I need to make P&R to insert buffer or anything to fix the timing check error... Thanks in advance. Best Regards, KelvinArticle: 66608
I did some tests on a Virtex chip and found HSTL_I good up to 250MHz unloaded with III and IV slightly slower. However, the data sheets seem to imply that the on-chip clock nets can exceed 330MHz(Tch, Tcl = 1.5ns). Is 250MHz the limit for bringing a signal on/off-chip, or was my test poorly executed?Article: 66609
> What's annoying about bottom posting? I have to scroll down to find out if you said anything interesting, and then, half the time it's just a "me too" type comment. If I jump to the end and discover that you didn't just say "me too", then I have to go back to the top and search forward to find out if you inserted something interesting rather than dumping everything at the end. Top vs bottom posting is a perpetural source of flames on usenet. In my opinion, the key is to trim the stuff that isn't directly relevant to what you are responding to. After that, the top/bottom part is lost in the noise and you will probably insert your text in a reasonable place. Top "posting" may be good in an office context where new people get cc-ed and need the previous context. It gets pretty silly in the usenet context when the discussion gets about 6 layers deep and everybody has seen the first N-1 layers several times already. (But then, it might help the poor sucker on a brain-damaged news server that drops 50% of the articles. But he's probably got other troubles.) On usenet, where I do have the context, I find it very annoying. The anti-top posters have many good sig lines. A few examples: A. Top posters. Q. What is the most annoying thing on Usenet? A. Because it destroys the natural flow of conversation. Q. What's wrong with top posting ? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 66610
John_H, "100 ohm load" does not make difference here because both the tables for LVPECL_25 in V-II data sheet and the table for LVPECL_33 in V-II ds have this condition. From the tables, both common mode ranges *and* diff swings are different each other, as least as I read. I am talking about Differential *and* Input only. I copied and pasted the tables as following: LVPECL DC Specifications (LVPECL_25) VCCO = 2.5V VIH 0.8V(min) 2.0V(max) VIL 0.5V(min) 1.7V(max) Differential Input Voltage 0.100V(min) -(max) LVPECL DC Specifications (LVPECL_33) VCCO = 3.3V VIH 1.49(min) 2.72V(max) VIL 0.86(min) 2.125V(max) Differential Input Voltage 0.3V (min) -(max) Can you teach how to read their comon mode ranges and diff swings are same so they are identical? Thanks. -qlyus "John_H" <johnhandwork@mail.com> wrote in message news:<a3u_b.1$tc4.9837@news-west.eli.net>... > qlyus, > > The Virtex-II DC & Switching Characteristics data sheet mentions that "These > values are valid when driving a 100 ? differential load only" suggesting > that the LVPECL standard is supported for DIFFERENTIAL SIGNALS not the > single ended you appear to be going toward. For a differential signal to > work, both inputs have to be within the receiver's common mode range *and* > have a differential swing at least as high as the receiver's minimum. > > If you checked into the Virtex-II user's guide as the Virtex-II data sheet > suggested, the write-up on Using LVPECL I/O in chapter 3 you'll see the > implementation is entirely differential. > > If you want to use single-ended LVPECL, you may need to do things a bit > differently and derive your own numbers. Two approaches that *may* work for > a pseudo-LVPECL would be to tie a center-crossing reference to *each* > differential input pair or define the inputs as a reference-based single > input standard with a slighlty different (but very close) center threshold > reference. > > > > "qlyus" <qlyus@yahoo.com> wrote in message > news:da71446f.0402231202.2f8e93ad@posting.google.com... > > Xilinx keeps saying LVPECL_2.5 and _3.3V inputs are identical. > > Obviously they are NOT. Virtex-II Pro lists only LVPECL_2.5. > > LVPECL_3.3 can be found in Virtex-II. Xilinx are saying THEY ARE > > IDENTICAL all the time, including in a reply when I asked > > specifically. I had to copy/paste the numbers in the data sheets and > > pointed out Vih=1.49-2.72 in LVPECL_3.3 is NOT identical to > > Vih=0.8-1.2 in LVPECL_2.5, Vil .... When admitted those numbers were > > not identical, Xilinx simply just said "go ahead do simulation" and > > closed the case. > > > > Now there are two answer records talking about "...because the input > > specifications for LVDS_25/33 and LVPECL_25/33 are identical." > > > > Here is the quote from Answer Record # 18095: > > > > "LVDS and LVPECL specifications are available in the "DC and Switching > > Characteristics" section of the Spartan-3 data sheet: > > http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf" > > > > But Spartan-3 data sheet does not have LVPECL listed in > > characteristics section at all. > > > > Can somebody here help to understand all of these things? I am really > > confused. > > > > -qlyus > > > > Answer Record # 18095 Spartan-3 - Can I interface a 3.3 volt LVDS or > > LVPECL device to a Spartan-3? > > Spartan-3 supports only LVDS_25 and LVPECL_25. Can I interface a 3.3 > > volt LVDS or LVPECL device to a Spartan-3?... > > (18130 bytes) > > > > Answer Record # 16830 Virtex-II Pro - Can I put LVDS or LVPECL I/O in > > the 3.3V bank? > > Virtex-II offers two options for powering LVDS drivers: 2.5V and 3.3V > > (both have identical electrical characteristics). Is this possible > > with Virtex-II Pro? Can I put LVPECL I/O in the 3.3V bank?... > > (25146 bytes)Article: 66611
Hi,
Mine isn't going to be free, but . . . I am considering releasing a PCI
IP core I have been working on for quite some time, and I am trying to
gauge the demand out there for a commercial-grade PCI IP core for
personal users.
However, the PCI IP core itself probably won't be available for another
three months at the earliest (I still need to fix some minor problems,
and setup the infrastructure before the release.).
The price I am thinking of charging for my PCI IP core is only $100
(USD) as long as the licensee meets the following conditions.
* The licensee resides within the United States (Don't have to be a US
citizen.).
* The licensee Will agree that the PCI IP core will be used only for
non-commercial, non-profit, non-academic research, and personal
purposes.
* The licensee is will agree, sign, and mail back to a license agreement
form I will provide.
* The licensee will pay for the PCI IP core license through an online
payment source like PayPal.
This is what my PCI IP core looks like:
* PCI Local Bus Revision 2.2 compliant.
* Burst initiator/target access support.
* 6 Base Address Register (BAR) and Expansion ROM BAR support.
* Meets 33MHz PCI timings with Spartan-II-5 (Currently, no 66MHz PCI
support with any device due to setup time issues . . .).
* General purpose PCI testbench comes with a PCI arbiter, PCI host
bridge emulator, and PCI target device to allow the user to quickly
debug their design.
* The PCI IP core supplied in NGO netlist format (Xilinx's proprietary
netlist format.).
* Nominally supports Xilinx Virtex, Spartan-II, or newer FPGAs.
* Constraint file supplied for Spartan-II PQ208 and FG456 package,
Virtex-E XCV300E BG432 package, Insight Electronics Spartan-II 150 PCI
card, and Spartan-II 200 PCI card.
* Comes with three reference designs (Two similar target only designs
and one target/initiator design.).
* Fully supports Verilog (Reference designs and the PCI testbench are
written in Verilog.).
* Limited VHDL support (No reference designs and PCI testbench. Might do
VHDL porting of reference designs and PCI testbench someday, but I won't
guarantee that.).
* Supports ISE WebPACK 3.2 or later (The use of ISE WebPACK 5.1 or later
is strongly recommended.).
* Should work with paid version (non-WebPACK) ISE software, but hasn't
been tested.
* Free Xilinx ISE WebPACK and ModelSim XE-Starter can be used to
simulate, synthesize, place & route, and generate a bitstream file.
* Should work with non-XST synthesis tools, but hasn't been tested.
The PCI IP core will also be available for commercial licensees
in NGO netlist format or as Verilog RTL code, but they will cost
considerably more than $100 (Especially the Verilog RTL license.).
The motivation behind this $100 license is to allow hobbyists to build
their own PCI device for about $500 ($275 for Insight Electronics
Spartan-II 200 PCI card with a parallel port JTAG cable, $100 for the
PCI IP core license, $100 for a printed copy of PCI specification from
PCI-SIG, and other miscellaneous costs like shipping cost and sales
tax.) without having them to spend too much time designing their own PCI
interface.
My guess is that there are probably a few hundred people in the United
States who will rather license a PCI IP core with testbench for $100
than to do their own or use Opencores.org PCI IP core.
I believe this PCI IP core is a great learning vehicle for those who
want to learn programmable logic or Verilog, or for use in a student
project (The student can concentrate on backend logic rather than the
PCI bus.).
Let me know if anyone is interesting in this product.
Kevin Brace
Antti Lukats wrote:
>
> Torsten,
>
> what do you mean by "Free" ?
> on the link there is notice
>
> "if interested please contact using a form" - there is no reference to any
> form or download location or conditions.
> so what it is all about?
>
> also the website says the ref design uses Spartan III not IIE ?
>
> antti
> www.openchip.org
>
> "Torsten Lauter" <tlau@infotech.tu-chemnitz.de> wrote in message
> news:c1d6q4$blt$1@anderson.hrz.tu-chemnitz.de...
> > Free PCI-bridge in VHDL for Spartan-IIE
> >
> > Somebody knows the implementation of
> > http://www.infotech.tu-chemnitz.de/~tlau/pci_bridge
> >
> > Regards.
> > __________________________________________________________________ Torsten
> > Lauter ICQ#: 14492119 Current ICQ status: + More ways to contact me
> > __________________________________________________________________
> >
> >
Article: 66612
Hi,
Mine isn't going to be free, but . . . I am considering releasing a PCI
IP core I have been working on for quite some time, and I am trying to
gauge the demand out there for a commercial-grade PCI IP core for
personal users.
However, the PCI IP core itself probably won't be available for another
three months at the earliest (I still need to fix some minor problems,
and setup the infrastructure before the release.).
The price I am thinking of charging for my PCI IP core is only $100
(USD) as long as the licensee meets the following conditions.
* The licensee resides within the United States (Don't have to be a US
citizen.).
* The licensee Will agree that the PCI IP core will be used only for
non-commercial, non-profit, non-academic research, and personal
purposes.
* The licensee is will agree, sign, and mail back to a license agreement
form I will provide.
* The licensee will pay for the PCI IP core license through an online
payment source like PayPal.
This is what my PCI IP core looks like:
* PCI Local Bus Revision 2.2 compliant.
* Burst initiator/target access support.
* 6 Base Address Register (BAR) and Expansion ROM BAR support.
* Meets 33MHz PCI timings with Spartan-II-5 (Currently, no 66MHz PCI
support with any device due to setup time issues . . .).
* General purpose PCI testbench comes with a PCI arbiter, PCI host
bridge emulator, and PCI target device to allow the user to quickly
debug their design.
* The PCI IP core supplied in NGO netlist format (Xilinx's proprietary
netlist format.).
* Nominally supports Xilinx Virtex, Spartan-II, or newer FPGAs.
* Constraint file supplied for Spartan-II PQ208 and FG456 package,
Virtex-E XCV300E BG432 package, Insight Electronics Spartan-II 150 PCI
card, and Spartan-II 200 PCI card.
* Comes with three reference designs (Two similar target only designs
and one target/initiator design.).
* Fully supports Verilog (Reference designs and the PCI testbench are
written in Verilog.).
* Limited VHDL support (No reference designs and PCI testbench. Might do
VHDL porting of reference designs and PCI testbench someday, but I won't
guarantee that.).
* Supports ISE WebPACK 3.2 or later (The use of ISE WebPACK 5.1 or later
is strongly recommended.).
* Should work with paid version (non-WebPACK) ISE software, but hasn't
been tested.
* Free Xilinx ISE WebPACK and ModelSim XE-Starter can be used to
simulate, synthesize, place & route, and generate a bitstream file.
* Should work with non-XST synthesis tools, but hasn't been tested.
The PCI IP core will also be available for commercial licensees
in NGO netlist format or as Verilog RTL code, but they will cost
considerably more than $100 (Especially the Verilog RTL license.).
The motivation behind this $100 license is to allow hobbyists to build
their own PCI device for about $500 ($275 for Insight Electronics
Spartan-II 200 PCI card with a parallel port JTAG cable, $100 for the
PCI IP core license, $100 for a printed copy of PCI specification from
PCI-SIG, and other miscellaneous costs like shipping cost and sales
tax.) without having them to spend too much time designing their own PCI
interface.
My guess is that there are probably a few hundred people in the United
States who will rather license a PCI IP core with testbench for $100
than to do their own or use Opencores.org PCI IP core.
I believe this PCI IP core is a great learning vehicle for those who
want to learn programmable logic or Verilog, or for use in a student
project (The student can concentrate on backend logic rather than the
PCI bus.).
Let me know if anyone is interesting in this product.
Kevin Brace
Torsten Lauter wrote:
>
> Free PCI-bridge in VHDL for Spartan-IIE
>
> Somebody knows the implementation of
> http://www.infotech.tu-chemnitz.de/~tlau/pci_bridge
>
> Regards.
> __________________________________________________________________ Torsten
> Lauter ICQ#: 14492119 Current ICQ status: + More ways to contact me
> __________________________________________________________________
Article: 66613"Kevin Brace" <kev0inb1rac2e@m3ail.c4om> wrote in message news:c1f3ac$lrc$1@newsreader.mailgate.org... > > * The licensee resides within the United States (Don't have to be a US > citizen.). How can you possibly justify this restriction? You get a chance to explain yourself before the rants arrive, but it'd better be *very* good. David Brown Norway.Article: 66614
> Cache architecture is > currently 1 way set associative, but more Blockrams would allow more > ways. Do you not think that the number of ways has to be as least as great as the number of threads? I would expect a significant amount of conflict misses (particularly in the I-Cache) if this is not the case. Hit-under-miss is a must. Otherwise all those impressive Mega-Hurtz will just be thown away stalling for cache refills. Cheers, JonBArticle: 66615
Hi everyone I'm trying to simulate a design using a testbench tool called HDL bencher which is integrated with Xilinx ISE. The problem i have is that when i set the value of the INOUT signal in my design, the testbench does not appear to assert it as desired and the port stays at value zero. Has anyone else had any similar problems with HDL bencher and ISE? Or does anyone have any recommendations / tips for working with INOUT signals in designs? Thanks in advance Mike NicklasArticle: 66616
Dear newsgroup, I am quite new to FPGAs but experienced enough in digital ASIC design (VHDL, Verilog & stuff). Recently, we encountered some problems with the selection of the best FPGA for a design we are attempting. The design in question is a custom CardBus module, for which we are considering a Cyclone FPGA from Altera. The functionality of the module is not too complex. Beside the bus-related requirements themselves (CIS, ConfigSpace), we also need a FIFO. The bigger the FIFO, the better. Is Cyclone an appropriate choice for this application, or are there better solutions out there? Another issue is the time necessary for the FPGA to load its configuration, which can be as high as a couple of seconds. As far as I read in an earlier discussion on the newsgroup, this might be a big problem since the system software will power down the socket after seeing that the card does not respond within a short interval after insertion (less than 1 sec). Is there any reliable solution to this problem? If not, I am afraid the only choice is to try with the flash-based FPGAs from Actel, which does not come in too handy. I don't like the idea of paying for the Actel software, which is not even that good like ISE or Quartus. And the Actel parts seem to be much too expensive and difficult to program. Looking forward to any suggestion, MichaelArticle: 66617
Consider the grid shown below.
There are 4 electrical "switch pairs" which need to be connected to
make the overall connection work.
---------------------------------------------------------
| | | | | | | | | | | | | | |
---------------------------------------------------------
| | | | | | | | | | | | | | c`|
---------------------------------------------------------
| | | | | | | | | | | | | | |
---------------------------------------------------------
| | | | b | | | | | | | | | | |
---------------------------------------------------------
| | | | | | | | | | | | | d'| |
---------------------------------------------------------
| | | | | | | | | | | | | | |
---------------------------------------------------------
| | | | | | | | | | | | | | |
---------------------------------------------------------
| | | | | | a | | | | | a`| | | |
---------------------------------------------------------
| | | | | | | | | | | | | | |
---------------------------------------------------------
| | | | | | | | | | | | | | |
---------------------------------------------------------
| | | | | | | | | | | b`| | | |
---------------------------------------------------------
| | | | | | | d | | | | | | | |
---------------------------------------------------------
| | | | | | | | | | | | | | |
---------------------------------------------------------
| | c | | | | | | | | | | | | |
---------------------------------------------------------
The paths are
a --- a' (path A)
b --- b' (path B)
c --- c' (path C)
d --- d' (path D)
There would be two possible routes to connect these paths. The
connection can follow either 1) horizontal then vertical direction,
or 2) vertical then horizontal direction. There ie no other way that
the path between the electrical switches could be made. Thus every
possible path here would make a bounded rectangle encompassing the
pair of switches.
The following rule is to be followed for making up these paths:
If a switch p belonging to one path lies in the bounded rectangle
formed by the switches belonging to another path, then path p must be
connected first.
SO - What would be the order of connectivity of this set of paths?
AND - Develop a generalized procedure to implement this strategy!
Thanks,
Chris
Article: 66618I have a board that has a XCF02S and Spartan 3 400 (ES) connected in a JTAG chain (the XCF02S is first in the chain). Attempting to initialise the chain in Impact fails because the IDCODE coming out of the FPGA is invalid (I have verified this on a scope - It is reproducibly incorrect, and always the same value). Looking at the TDO pin of the XCF02S / TDI pin of the FPGA, I can see that the IDCODE coming out of the XCF02S is correct. If I take the XCF02S out of the chain, then the IDCODE from the FPGA is correct and Impact is able to program the device. Should the value on the TDI pin of the FPGA effect the output of the IDCODE? Is it possible that any of the other FPGA configuration pins that the XCF02S is driving effect JTAG operation? I'm pretty sure the devices are connected as detailed in the XCF02S data sheet. Cheers, JonBArticle: 66619
"Chris Jones" <chjones@dacafe.com> wrote in message news:8090cd3b.0402240322.107d76ce@posting.google.com... > Consider the grid shown below. > > There are 4 electrical "switch pairs" which need to be connected to > make the overall connection work. > > --------------------------------------------------------- > | | | | | | | | | | | | | | | > --------------------------------------------------------- > | | | | | | | | | | | | | | c`| > --------------------------------------------------------- > | | | | | | | | | | | | | | | > --------------------------------------------------------- > | | | | b | | | | | | | | | | | > --------------------------------------------------------- > | | | | | | | | | | | | | d'| | > --------------------------------------------------------- > | | | | | | | | | | | | | | | > --------------------------------------------------------- > | | | | | | | | | | | | | | | > --------------------------------------------------------- > | | | | | | a | | | | | a`| | | | > --------------------------------------------------------- > | | | | | | | | | | | | | | | > --------------------------------------------------------- > | | | | | | | | | | | | | | | > --------------------------------------------------------- > | | | | | | | | | | | b`| | | | > --------------------------------------------------------- > | | | | | | | d | | | | | | | | > --------------------------------------------------------- > | | | | | | | | | | | | | | | > --------------------------------------------------------- > | | c | | | | | | | | | | | | | > --------------------------------------------------------- > > The paths are > > a --- a' (path A) > b --- b' (path B) > c --- c' (path C) > d --- d' (path D) > > There would be two possible routes to connect these paths. The > connection can follow either 1) horizontal then vertical direction, > or 2) vertical then horizontal direction. There ie no other way that > the path between the electrical switches could be made. Thus every > possible path here would make a bounded rectangle encompassing the > pair of switches. > > The following rule is to be followed for making up these paths: > > If a switch p belonging to one path lies in the bounded rectangle > formed by the switches belonging to another path, then path p must be > connected first. > > SO - What would be the order of connectivity of this set of paths? > > AND - Develop a generalized procedure to implement this strategy! > > Thanks, > Chris The strategy will not work in general. Consider the network: a b - - a' b' It's easy to see a connection solution, but b is in the boundary of a-a', and a' is in the boundary of b-b', so your strategy will not work here. Also, you need to consider how to deal with unsolvable networks.Article: 66620
"Michael" <no.mail@no.spam> wrote in message news:c1fbmr$3o4$1@news.tu-darmstadt.de... > Dear newsgroup, > > I am quite new to FPGAs but experienced enough in digital ASIC design (VHDL, > Verilog & stuff). Recently, we encountered some problems with the selection of > the best FPGA for a design we are attempting. > The design in question is a custom CardBus module, for which we are considering > a Cyclone FPGA from Altera. The functionality of the module is not too complex. > Beside the bus-related requirements themselves (CIS, ConfigSpace), we also need > a FIFO. The bigger the FIFO, the better. Is Cyclone an appropriate choice for > this application, or are there better solutions out there? It depends entirely on the requirements of the FIFO, such as size, speed, latency, cost, component size, etc. > Another issue is the time necessary for the FPGA to load its configuration, > which can be as high as a couple of seconds. As far as I read in an earlier > discussion on the newsgroup, this might be a big problem since the system > software will power down the socket after seeing that the card does not respond > within a short interval after insertion (less than 1 sec). Is there any reliable > solution to this problem? Smaller FPGAs normally load their configuration faster, although I don't have figures for any particular FPGAs. You might also consider using a PLD in the mixture, holding critical functions alive until the FPGA comes on line. > If not, I am afraid the only choice is to try with the flash-based FPGAs from > Actel, which does not come in too handy. I don't like the idea of paying for the > Actel software, which is not even that good like ISE or Quartus. And the Actel > parts seem to be much too expensive and difficult to program. > > Looking forward to any suggestion, > > Michael > >Article: 66621
I have some questions regarding Xilinx design flow. What NGD and NGC files are? Is edif file created by the 2edif tools synthesizable? According to http://toolbox.xilinx.com/docsan/xilinx4/data/docs/dev/ngdbuild2.html, NGDBuild converts netlist (Edif, Ngc, Xnf) into logical design (ngd - logic elements like AND gates, decoders, FFs, RAMs). This is called translation. But what is a role of synthezier, isn't it XST that should generate netlist of logic gates from RTL description? ActiveHDL IDE allows for functional, post-synthess and timing (post-implementation) simulations. Sinthesis is done using Sinplify; it includes two stages: compilation and mapping. After syntesis, Xilinx implementation tools are used to get timing information. Implementation consists of translation, mapping (again?) and P&R. Why mapping is done twice? Why two different libraries (Unisim and SimPrim) are used for syntesis and implementation? Wouldn't it be more effective to use only one? Can I write a structural edif file based on elements of those libraries (which one?) and synthetize it effectively creating design from scratch bypassing synthesis? Thanks.Article: 66622
"Tony" <nospam@email.com> wrote in message news:sfsk30h5664f1u5bvkh37fjk0nud8qvtim@4ax.com... > Hello, > > I am following the new (Jan 12 '04) ML300 EDK user guide to build, > simulate, and run a reference design from the EDK > (http://www.xilinx.com/products/boards/ml300/docs/ml300_ref_des_ug.pdf). > > I have no problem building and running the reference design > (system_hello_uart) on the ML300, but simulation will not work. I > have tried ModelSim SE 5.7 and 5.8, and both generate the same fault > on the same problem. > # ** Error: (vsim-3170) Could not find 'work.glbl'. > # Error loading design > # Error: Error loading design > # Pausing macro execution > # MACRO ./../../data/testbench.do PAUSED at line 92 glbl is small silly stupid simulation primitive that simulates the Global Set Reset lines in FPGA. I think it is somewhere in simulation libs. just need to include it also. $xilinx\verilog\src\glbl.v Antti www.openchip.orgArticle: 66623
Hello You must go on the website and must fill out the form. You get the data per email then. I have gotten the data per email and nothing pays. Regards Torsten Lauter "Antti Lukats" <antti@case2000.com> schrieb im Newsbeitrag news:c1di1m$vqs$00$1@news.t-online.com... > Torsten, > > what do you mean by "Free" ? > on the link there is notice > > "if interested please contact using a form" - there is no reference to any > form or download location or conditions. > so what it is all about? > > also the website says the ref design uses Spartan III not IIE ? > > antti > www.openchip.org > > > "Torsten Lauter" <tlau@infotech.tu-chemnitz.de> wrote in message > news:c1d6q4$blt$1@anderson.hrz.tu-chemnitz.de... > > Free PCI-bridge in VHDL for Spartan-IIE > > > > Somebody knows the implementation of > > http://www.infotech.tu-chemnitz.de/~tlau/pci_bridge > > > > Regards. > > __________________________________________________________________ Torsten > > Lauter ICQ#: 14492119 Current ICQ status: + More ways to contact me > > __________________________________________________________________ > > > > > >Article: 66624
hmurray@suespammers.org (Hal Murray) writes: >> What's annoying about bottom posting? > > I have to scroll down to find out if you said anything interesting, > and then, half the time it's just a "me too" type comment. If I jump to > the end and discover that you didn't just say "me too", then I > have to go back to the top and search forward to find out if you > inserted something interesting rather than dumping everything at the end. > > > Top vs bottom posting is a perpetural source of flames on usenet. > > In my opinion, the key is to trim the stuff that isn't directly > relevant to what you are responding to. After that, the top/bottom > part is lost in the noise and you will probably insert your text > in a reasonable place. > > > Top "posting" may be good in an office context where new people > get cc-ed and need the previous context. It gets pretty silly > in the usenet context when the discussion gets about 6 layers deep > and everybody has seen the first N-1 layers several times already. > (But then, it might help the poor sucker on a brain-damaged > news server that drops 50% of the articles. But he's probably > got other troubles.) On usenet, where I do have the context, > I find it very annoying. > > > The anti-top posters have many good sig lines. A few > examples: > > A. Top posters. > Q. What is the most annoying thing on Usenet? > > A. Because it destroys the natural flow of conversation. > Q. What's wrong with top posting ? Perhaps the problem isn't top- or bottom-posting per se, but that the quoting method used is inconsistent. If folks are careful to ensure the "Tom says:" lines are properly maintained and use the same quote character and indentation style, either posting style is fairly easily- parsed, in my opinion. -- % Randy Yates % "Remember the good old 1980's, when %% Fuquay-Varina, NC % things were so uncomplicated?" %%% 919-577-9882 % 'Ticket To The Moon' %%%% <yates@ieee.org> % *Time*, Electric Light Orchestra http://home.earthlink.net/~yatescr
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