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We have a board with 15 Altera FPGAs and 12 Configuration circuits (9xEPC2 and 3xEPC8). In the JTAG chain one FPGA (1K100484) sometimes falsifies the data stream. It pushes the data stream by one bit - but always for a length of appr. 8 bits, thenafter the stream recovers. Thus it is hard to program the Configuration chips. It is still possible for the EPC2s, sometimes two or three approaches are needed. Practically impossible for the EPC8s due to their longer programming process. The error even shows when we read out ID. The stream looks like: 20 10 00 DD 01 00 20 DD 10 08 00 6E 81 00 20 DD 01 00 A0 DD When we bridge over the JTAG data lines of this single FPGA the error disappears. The FPGA has no longer or different JTAG I/O lines than the other FPGAs in the board. Is this a frequent error? Janos Ero CERN Div. EPArticle: 65651
Hi, can anybody tell me how to send/receive a multi-bit (Eg.160-bit or
512-bit)data between Altera Nios FPGA board with Visual Basic Program
running on PC? Do i need any handshakind signal between the C source
code which will downloaded into the embedded system with the VB
program?
And, can anyone recommen me any website to gain information
regarding serial port communication interface and C source code of it?
Thank you very much.
Article: 65652Hi Jim Jim Granville <no.spam@designtools.co.nz> wrote in message news:<14XTb.20607$ws.2742532@news02.tsnz.net>... > snip. > Anyone seen actual numbers or NIOS or NIOS II ? > > -jg I did a quick compile in Quartus2_ver4 with Stratix2 and Stratix same Nios design only changed parts. Results in ALUT's compared to LE's is 3202 ALUT (S2) and 4522LE's (S). Push button compile of design no tweaking no logiclock. Cheers FredrikArticle: 65653
<dougs@dougs.com> wrote in message news:bvpvpp$slu$1@tomahawk.unsw.edu.au... > I have had to define a data type to deal with logarithmic values. It's > basically a real number ranging from -10000 to 10000. However, I would like > to use this user-defined data type in the entity of the device, i.e. given > the user-defined type is called llrValue, the architecture port would be > > ENTITY sova_decoder IS > PORT ( > Approiri : IN llrValue > ) > > Where do I define the data type such that it would be recognised once it > appears in the entity? Or is there some other way to do this? You need to use a package, e.g. package types is subtype llrvalue is real range -10000.0 to 10000.0; end; Then if you compile it into the same library you are using for your entity, it will appear in the current working library, so you can say use WORK.types.all; entity sova_decoder is ... regards Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 65654
Hi all ! Currently I'm working on a design to be implemented by using a daughterboard, that is set on top of a TI C671x DSK. On this daughterboards, one Spartan II FPGA ( XC2S200) with Speedgrade -5 and package PQFP208 is soldered. This one connects directly to the DSP expansion ports. As we would like to have efficient data transmissions between DSP and FPGA there was the idea to implement a 100MHz SBSRAM tnterface for transmissions between DSP and Spartan II Block Ram. After some simulations I guess that the dout timings of the BR are the most critical part and a propper solution could be just found by manual floorplanning and using a FPGA with speedgrade -6. Since the board already is soldered, this might be a little problem :-( Well, as here are some really experienced guys, I would be happy to get some suggestions that might help me to get this design working. Thank you very much !!!!Article: 65655
A part number search for XC3S400 on http://www.em.avnet.com/ showed a status change to "on stock" for the XC3S400-4FT256CES. A call to the germany distributors (explicilty asking also for engineering samples) however gave either no parts listed or "expect about 12 weeks of delivery delay". What holds? Are there samples available, and how to get them? B.t.w.: Xilinx explicitly denies Us distributors to deliver to Germany, so ordering directly with AVNET US is not an option. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 65656
Any advice please. I am creating a parallel uP interface to my fpga and i have separate 'processes' for the read and write functions. My question is : Will quartus synthesise separate address decoders - one for the read and one for the write, or is it 'clever' enough to munge the two together in the same decoder when synthesising ? (not sure of the tech term but is this resource sharing ?) Any help will be much appreciatedArticle: 65657
abhishektara@hotmail.com (abhishek tara) wrote in message news:<4e406ad0.0402031749.1c68fd24@posting.google.com>... > hi > i would like to know that how can i obtain a vendor id in brief read > the > value at the base of config space.. Under linux use lspci (read the man page) or look at the contents of /proc/bus/pci/ Under DOS and its successors use pcispy.exe Also very useful under windows is the memaccess library from zealsoft. Kolja SulimmaArticle: 65658
On Wed, 4 Feb 2004 16:29:48 +1100, <dougs@dougs.com> wrote:
>I have had to define a data type to deal with logarithmic values. It's
>basically a real number ranging from -10000 to 10000. However, I would like
>to use this user-defined data type in the entity of the device, i.e. given
>the user-defined type is called llrValue, the architecture port would be
>
>ENTITY sova_decoder IS
>PORT (
> Approiri : IN llrValue
>)
>
>Where do I define the data type such that it would be recognised once it
>appears in the entity? Or is there some other way to do this?
Define the type in a package, then "use" the package before the entity
declaration.
lib mylib;
use mylib.mypkg.all;
entity sova_decoder is
port (
Approiri : IN llrValue
Regards,
Allan.
Article: 65659Uwe Bonnes wrote: > A part number search for XC3S400 on http://www.em.avnet.com/ showed a status > change to "on stock" for the XC3S400-4FT256CES. I don't get that, when I checked just now all the XCS3* parts are "No Stock" or"Not available for on-line ordering". Leon -- Leon Heller, G1HSM Email: aqzf13@dsl.pipex.com My low-cost Philips LPC210x ARM development system: http://www.geocities.com/leon_heller/lpc2104.htmlArticle: 65660
hi all,
any body have the idea on adaptive viterbi decoder design. now
in that i am facing problem in ACS unit control. in that if the path
metric is less that threshold, next time the ACS corresponda to that
state must off. how to control that.
and another main problem is in a ACS two states will be there. if one
state is off, then how we can get that metric only. if any body
interested to know this prblem, i will give in another mail.
thanks
Article: 65661Uwe Bonnes wrote: > A part number search for XC3S400 on http://www.em.avnet.com/ showed a status > change to "on stock" for the XC3S400-4FT256CES. Sorry, they *are* available (allegedly), I didn't check all the pages. Leon -- Leon Heller, G1HSM Email: aqzf13@dsl.pipex.com My low-cost Philips LPC210x ARM development system: http://www.geocities.com/leon_heller/lpc2104.htmlArticle: 65662
I'm trying to be very specific telling that the target application is simulations accelerator. The higher speed the better. As converter will be running on FPGA, this limits number of vectors per second that can be simulated to about 200MHz. Hence, the desired bandwidth is number_of_vectors_per_second * vector_width gives about 100Mbps..10Gbps (for both channels). Channels should not be symmetric (input can be faster than output or vice versa). I just want to discover existing PC-interfacing solutions, make a broader view in the field. Rather than doing conversion task in SW it is often more desirable to use a task specific HW. All kinds of FPGA-based accelerators are becoming more and more popular. I've even seen about universal FPGA-accelerators. Data converter is a simplest accelerator; its communication scheme includes only one input and one output stream. The simulator I would like to implement belogns to data conversion class as well. I have mentioned compression/encription asking for typical reference design of data converter. Thanks.Article: 65663
cheers "Alan Fitch" <alan.fitch@doulos.com> wrote in message news:bvqcon$aqa$1$8300dec7@news.demon.co.uk... > > <dougs@dougs.com> wrote in message > news:bvpvpp$slu$1@tomahawk.unsw.edu.au... > > I have had to define a data type to deal with logarithmic values. > It's > > basically a real number ranging from -10000 to 10000. However, I > would like > > to use this user-defined data type in the entity of the device, i.e. > given > > the user-defined type is called llrValue, the architecture port > would be > > > > ENTITY sova_decoder IS > > PORT ( > > Approiri : IN llrValue > > ) > > > > Where do I define the data type such that it would be recognised > once it > > appears in the entity? Or is there some other way to do this? > > You need to use a package, e.g. > > package types is > > subtype llrvalue is real range -10000.0 to 10000.0; > > end; > > Then if you compile it into the same library you are using for your > entity, it will appear in the current working library, so you can > say > > use WORK.types.all; > entity sova_decoder is ... > > > regards > > Alan > > -- > Alan Fitch > Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project > Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 > 1AW, UK > Tel: +44 (0)1425 471223 mail: > alan.fitch@doulos.com > Fax: +44 (0)1425 471573 Web: > http://www.doulos.com > > The contents of this message may contain personal views which are not > the > views of Doulos Ltd., unless specifically stated. >Article: 65664
Hi Raghavendra, You can access Xilinx's Spreadsheet Power Tools and Web Power Tool (WPT) here : http://www.xilinx.com/ise/power_tools/. That web-site also provides information on our desktop power estimation application XPower - which is part of ISE. Regards, Brendan Raghavendra wrote: > Hi All, > How to manually estimate dynamic power consumption of the design in the FPGA? > Thanks in advance, > Raghavendra.SArticle: 65665
Leon Heller <aqzf13@dsl.pipex.com> wrote: : Sorry, they *are* available (allegedly), I didn't check all the pages. Listing 60 or even more then 100 Spartan (nuhorizons) Device/Package/Speed Options have having only 3/nill on stock looks strange admitingly... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 65666
In article <bvq8h1$uoao1$1@ID-61213.news.uni-berlin.de>, miaooaim.REMOVETHIS@tiscali.it says... > <CUT> > > > > Get a better news reader. A good one d/l's the message only once, > > keeping tabs on the message id so if you see it in one group it won't > > show in the others unless you tell it you want to. > > > > - YD. > > > > Which kind of NewsReader do you to suggest or you are using? He's using "Forte Agent 1.8/32.548" (the X=Newsreader: tag is in the article headers). I'm using Gravity, which is free. Any decent newsreader understands cross-threading. If your newsreader doesn't, it's time to change. -- KeithArticle: 65667
Your problem reminds me of a problem I had a while ago. The FPGA locked up just your CPLD was doing. By digging a bit, I found that ISE had implemented my state machines as one-hot so I thought that somehow the FSM had gone into an illegal state. Forcing the FSM to binary encoding reinforced my belief. To shorten the story, it turned out the FPGA wasn't really going into an illegal state: the problem was that there was poor signal integrity on the clock signal, which occasionally would have a double edge, causing the bit in the one-hot encoding to be lost. You might want to check out the clock after looking at the Vcc.Article: 65669
Hi, Is it possible to reconfigure an FPGA from 'within' the FPGA at runtime, without any need for an external system to do this? I would like to make a design that can create/remove 'components' at runtime. Do all/any of the mainstream chips support this (Xilinx, Altera)? Does anyone have any experience of doing this? What is the performance like? What impact does it have on the overall system? I was thinking that a core would remain constant, and pre-defined areas would be dynamically changed as required. Also, is there any available software that will support/simulate this functionality? Preferably something that I could afford (personal hobby project) would be good! I'm sorry if this is a bit of a newbie question. I have had a good dig around for answers, but not found anything other than hints that this can be done. Maybe. I'm looking at doing some GP work with FPGA's, as I only discovered they even existed a few days ago, and they seem suited to GP work. Any help would be appreciated. Thanks in advance, - Jelly. "Beware of the Leopard!"Article: 65670
Look at the LATTICE range of XPGA products. www.lattice.co.ukArticle: 65671
If you want your emulator to be pluggable into a standard PC, then the most obvious choice for the interface is PCI. With standard 32 bit 33 MHz PCI you can theoretically achieve 132 MByte/s. In practice I have achieved over 100 MByte/s. If this is not enough you can go to 64 bit / 66 MHz PCI, which is pretty common nowadays too. To achieve high speeds on PCI bus your emulator would have to be a bus master for both reads and writes. The next step in performance is PCI-X, but I don't think it is wide spread among PC motherboards... Another way is to make your card look like a memory module. I think this approach was discussed here in the past. This seems like an interesting idea, but personally I prefer staying with standard interfaces. Then there are all kinds of fast serial buses, but if I were you I wouldn't go there for this application. /Mikhail -- To reply directly: matusov at square peg ca (join the domain name in one word and add a dot before "ca") "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in message news:bvqnq5$vmk1b$1@ID-212430.news.uni-berlin.de... > I'm trying to be very specific telling that the target application is > simulations accelerator. The higher speed the better. As converter will be > running on FPGA, this limits number of vectors per second that can be > simulated to about 200MHz. Hence, the desired bandwidth is > number_of_vectors_per_second * vector_width gives about 100Mbps..10Gbps (for > both channels). Channels should not be symmetric (input can be faster than > output or vice versa). I just want to discover existing PC-interfacing > solutions, make a broader view in the field. > > Rather than doing conversion task in SW it is often more desirable to use a > task specific HW. All kinds of FPGA-based accelerators are becoming more and > more popular. I've even seen about universal FPGA-accelerators. Data > converter is a simplest accelerator; its communication scheme includes only > one input and one output stream. The simulator I would like to implement > belogns to data conversion class as well. I have mentioned > compression/encription asking for typical reference design of data > converter. Thanks. > >Article: 65672
Il 3 Feb 2004 04:49:32 -0800, ytregubov@yahoo.com (Yuri Tregubov) ha scritto: >Dear colleagues, > >The ByteBlaster works fine with MaxPlus 9.4 / Windows 95 but fails >with MaxPlus 10.2 / Windows 98. > >"Unrecognized device or socket is empty" > >Any clue ? my home made byteblaster and byteblasterMV work fine, with MaxPlus 10.2 / Windows 98 on an old Dell laptop. SB --------------------------------------------------- togli i caratteri accentati per rispondere via mailArticle: 65673
I wasn't able to attend SOPC World. (really wanted to) Can anyone share info from Altera's roadmap for these products? I'm working on a commercial product with the Cyclone and Nios and look forward to even more of this amazing technology. Also, a question about the pricing of Stratix I vs. II. Is the 40% lower price a marketing number or a real number? I mean are they playing games with equivalent LE's vs. ALUT's or will the roughly equivalent chips really be 60% of the current price?(what's $200 now will be $120) I ask because a 40% discount would bring the SII into the price range for our products, and I'd love to have the DSP features. Or will the Cyclone II get some of this? TIA, KenArticle: 65674
In comp.arch.fpga valentin tihomirov <valentin_NOSPAM_NOWORMS@abelectron.com> wrote: : I would like to accelerate a data conversion task. We just send a stream : of data to converter that produses a response stream. Actually, this : converter is an emulator of a system we are going to simulate efficiently : accelerating simulation task. As the goal is a number of simulations per : time unit, the high performance channels are needed to communicate between : application running on PC and emulator running on FPGA. The data conversion : (encription, compression) should be a known and well-understood toipc; thus, : I would like to see any good reference designs. : As, I do not have any experiance in high-speed I/O, I would like to : discover existing and popular high speed interfaces (DRIVERS, tools, : examples, defign flows, methodologies, cores, etc.). Can anybody offer an : Internet resource or an exellent book describing the topic? How many time : would it take to built a simplest prototype in man-hours (100, 1000, : million)? How costly will it be? If you only need to send data between some peripheral and the PC and latency isn't an issue, think about using a USB2 link, like the usrp Software radio peripheral (http://comsec.com/wiki?UsrpProtoIntro) does. About 32 MByte/sec were reached with unidirectional flow, 16 MByte in each direction bidirectional and a complete chain is provided. That way, you don't need to design an PCI adapter and can easily plug into any modern PC without opening it. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z