Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Vaughn Betz wrote: > One last suggestion Rene -- if your design is already complete, you > can use the power calculation abilities of the Quartus simulator. > Since the simulator will compute the activity (switching rate) of each > node in your design, it will generally be more accurate than the > spreadsheet on the web, where you have to enter your guessed > activities. The actitivies calculated by the simulator are still only > as good as your test vectors -- if you have little idea of the typical > input vector usage patterns of your design, simulation may still help > some, but the accuracy will be less than ideal. > > Of course, the simulator also knows the details of how many logic > cells, IOs, which standards, etc. are in your design. So you get the > right numbers there too. > > But to use this you need a completed design with test vectors, and > simulation is also slower than doing what-if scenarios in a > spreadsheet. > > To use the simulation-based power calculator from the GUI, go to > Assignments->Settings->Simulator, click on the Power Estimation > button, and check the "Estimate Power Consumption" box. > Then simulate your design. The design report file will now include a > power report section. Thanks Vaughn, I saw the power calculator in Quartus. The project is nowhere yet. I may have to do the Quartus design first then. Before the board. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 64951
Peter, out of curiosity, how many of these DLLs are in there ? 1, 10, one per pin ? Rene Peter Alfke wrote: > The DLL in Virtex-II or Spartan3 (we call it DCM=digital clock manager) > is the way to go. > You feed it a continuously-running clock, and you generate outputs that > are delayed by a fraction of the clock period ( defined as integer > multiple of clock period divided by 256). Works very nicely! > Peter Alfke, Xilinx > > chuk wrote: > >>Generating clock delays >> >>I am relatively new to VHDL so pleas excuse me if this is too easy a >>question. I need to be able to generate a time shifted version of the >>clk signal for control purposes in an Xilinx based project. There are >>several options that I have come across: >> >>-Using the after ??n, but this dose not seem to generate any >>difference >>-using the wait until statement though this is not supported by Xilinx >>for some reason >>-using the dll (is this the most efficient manor?) >> >>I would like someone to tell me which is the best and most >>controllable manor of generating a clock delay. ThanksArticle: 64952
I have an Avnet board. It comes with evaluation versions of EDK and ISE. It comes with a compact flash card containing several demo .bit files. By default it boots into Linux but you can make it boot any one of several sample designs. It had everything I need and ran out of the box in about 10 minutes. The one bad thing is that all of the documentation comes on CDs. I ended up printing about 500 pages of material so I could leaf to info easily. Also, it would be nice if they posted the documents to the web. "AJ" <AirJosh69@hotmail.com> wrote in message news:af0645be.0401160818.150fc01a@posting.google.com... > Hello FPGA users, > > I am thinking about purchasing the Avnet Virtex-II ProT Development > Kit and would like to find out if anyone is using it or has used it > recently. I want to make sure I am not missing anything. It seems like > it comes with all the tools, but I find it difficult to get a > straight/consistant answer sometimes from Avnet. My confusion lies in > the PowerPC tools and startup. I want to make sure that the board and > tools (ISE 6.1 Foundation and EDK) are sufficient to get going. I > don't need an RTOS for my project so I just want to be able to run my > code on the PowerPC either from external RAM or internal BRAM. > > Confusion is about the BOOT up process and wether I will have to write > alot of system level code. Can someone help me out or point me to a > document that might clear up my concerns. > > I would love to talk with someone that is currently using this > product. Please e-mail me. > > Thanks in advance, > AJArticle: 64953
Rene, The Cyclone FPGA can be configured by JTAG 1149.1. This can be done through the various download cables, or from a microprocessor. The microprocessor can do this via Jam (also used for programming CPLDs) or JRunner (a simpler FPGA-only tool). For more details, please consult Chapter 13 of the Cyclone Handbook: Configuring Cyclone FPGAs. http://www.altera.com/literature/hb/cyc/cyc_c51013.pdf The EPCS Serial Configuration Devices are programmed through a serial interface. While the device itself does not include JTAG, we have developed a method of programming it by JTAG by routing the data through the Cyclone device. In short: 1. The Cyclone FPGA is configured through JTAG. 2. The EPCS programming data is sent from the PC to the JTAG port of the Cyclone FPGA. This is done by Jam, so it can come from a PC, or from a Jam player running on an embedded microprocessor. 3. The logic in the FPGA captures data from the JTAG port of the Cyclone FPGA, reformats it to conform to the EPCS interface, and drives it to the EPCS device. This capability (as a reference design with documentation) is available in beta form today, and will be included in a future version of Quartus II software. To get access to the beta version, please contact your FAE or Regional Support Center. So, while the EPCS device is not directly connected to the JTAG chain, the device can be programmed by a JTAG controller by passing the data through the FPGA. One final note - Altera also provides a tool called SRunner, which enables you to program the EPCS device directly from an embedded microprocessor. This is another solution to the question of how to program the EPCS device. Greg Steinke gregs@altera.com Neil Glenn Jacobson <neil.jacobson@xilinx.com> wrote in message news:<400702DB.5060104@xilinx.com>... > The Cyclone device is programmable using only the proprietary mechanism. > It does not support 1149.1 or 1532 based programming. > > Rene Tschaggelar wrote: > > > The Altera Cyclone Programming device EPCS1 are shown > > to be programmed in the AS mode requiring an own connector. > > Since the JTAG was never officially declared outdated, > > I'd expect a way to program the cyclone plus the EPCS1 in JTAG > > mode. I wasn't able to find it yet though. > > > > ReneArticle: 64954
Between 4 and 12 DCMs in Virtex-II (depending on the chip size). It's on page 2 of the data sheet. We are not shy in bragging about these things. :-) Peter Alfke ============================= Rene Tschaggelar wrote: > > Peter, > out of curiosity, how many of these DLLs are in there ? > 1, 10, one per pin ? > > Rene > > Peter Alfke wrote: > > The DLL in Virtex-II or Spartan3 (we call it DCM=digital clock manager) > > is the way to go. > > You feed it a continuously-running clock, and you generate outputs that > > are delayed by a fraction of the clock period ( defined as integer > > multiple of clock period divided by 256). Works very nicely! > > Peter Alfke, Xilinx > > > > chuk wrote: > > > >>Generating clock delays > >> > >>I am relatively new to VHDL so pleas excuse me if this is too easy a > >>question. I need to be able to generate a time shifted version of the > >>clk signal for control purposes in an Xilinx based project. There are > >>several options that I have come across: > >> > >>-Using the after ??n, but this dose not seem to generate any > >>difference > >>-using the wait until statement though this is not supported by Xilinx > >>for some reason > >>-using the dll (is this the most efficient manor?) > >> > >>I would like someone to tell me which is the best and most > >>controllable manor of generating a clock delay. ThanksArticle: 64955
All, There was a related thread on this topic, and I replied to it. I am cross posting the response to this thread as well: The EPCS Serial Configuration Devices are programmed through a serial interface. While the device itself does not include JTAG, we have developed a method of programming it by JTAG by routing the data through the Cyclone device. In short: 1. The Cyclone FPGA is configured through JTAG. 2. The EPCS programming data is sent from the PC to the JTAG port of the Cyclone FPGA. This is done by Jam, so it can come from a PC, or from a Jam player running on an embedded microprocessor. 3. The logic in the FPGA captures data from the JTAG port of the Cyclone FPGA, reformats it to conform to the EPCS interface, and drives it to the EPCS device. This capability (as a reference design with documentation) is available in beta form today, and will be included in a future version of Quartus II software. To get access to the beta version, please contact your FAE or Regional Support Center. So, while the EPCS device is not directly connected to the JTAG chain, the device can be programmed by a JTAG controller by passing the data through the FPGA. One final note - Altera also provides a tool called SRunner, which enables you to program the EPCS device directly from an embedded microprocessor. This is another solution to the question of how to program the EPCS device. Greg Steinke gregs@altera.com "Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:<4002b0a7$0$227$fa0fcedb@lovejoy.zen.co.uk>... > Ben Popoola <b.popoola@ntlworld.com> wrote in message > news:qmkMb.4126$OA3.1018845@newsfep2-win.server.ntli.net... > > > I think that you can also program the EPCS1 via the Cyclone chip itself > > but I do not know how off head. > > > > This might work: > > > > (1) Configure the FPGA through the JTAG port. > > (2) If you have an I/O connection between your logic in the Cyclone and > > a PC, download your configuration bitstream into the EPCS1 via your > > logic in the Cyclone. > > (3) Turn the power off then on. The Cyclone should boot from the EPCS1. > > > I don't think it's as easy as this. > > There's an IP block AMSI which a NIOS processor can use to > acesss/reconfigure an AS device, but this can't easily be > accessed without the NIOS. > > Details of how it's driven aren't published so it's probably > not impossible to use, but not easy. > > This seems a daft move by Altera as easy access to the AS > device allowing in system up-dates would be a good marketing > point. > > > Nial Stewart > > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > Cyclone based 'Easy PCI' eval board > www.nialstewartdevelopments.co.ukArticle: 64956
guille wrote: > jim granville <no.spam@designtools.co.nz> wrote in message news:<ijtNb.17319$ws.2066401@news02.tsnz.net>... > >>guille wrote: >> >> >>>Hello all, >>> >>>I have a FSM with 6 states: IDLE, and S0-S5. Transitions are >>>synchronized with the system clock, but next state might be determined >>>by signals which are asynchronous to that clock. >> >>Sounds like thin ice. >>Can you not sync these to the opposite clock edge ? > > > Actually the signals are being double clocked (to the same clock > edge) to synchronize them and avoid metastables. So the actual > implementation would look more or less like this: > > clk > -----------+-----------+ > | | > +-----+ +-----+ > sig | | | | sig1 > --------|D Q|-----|D Q|-------- > +-----+ +-----+ > > And sig1 is the signal that the FSM looks at to determine which > state to go next. Is it a problem if the signal is sycnrhonized > to the same clock edge? No - the resaon I suggested the 'other edge', is sometimes the latency matters, and other edge is one way to make that 'half-clock'. What you have here is fully sync signals. > > >>>The FSM is normally at state IDLE. If certain signals are active, it >>>will go from IDLE to S0, then go through some intermediate states, and >>>finally back to IDLE. Here's a list of possible transitions: >>> >>>Current state Possible next states >>>------------- -------------------- >>>IDLE IDLE, S0 >>>S0 S1 >>>S1 S2, IDLE >>>S2 S3, IDLE >>>S3 S4, IDLE >>>S4 S4, S5, IDLE >>>S5 IDLE >>> >>>I would like to use Gray encoding for this FSM but I'm not sure how it >>>should be done. Using Gray encoding is straightforward for things like >>>counters and such where there's only one possible next state for each >>>current state. However, is it possible in a case like this? >> >>A formal Gray code may be impossible, but you may be able to find a >>'single bit change' pattern using pencil and paper. >>It can also help, if you allow IDLEa, IDLEb,(etc) for example - these >>are extra states added purely to ensure single-bit state jumps >>can be met. > > > I assume that this is still needed even after adding the double > clocking described above, right? No - once you have sync'd any signals that may have violated Tsu, you can generate any state pattern you like, including one where multiple bits change. Provided all downstream decisions are made by FF's ( not async decoded) you do not need actually Gray code. The real danger of async signals -> Two bit changes is aperture skew, where the precise capture time of two FFs is not exactly the same. Then only one bit may toggle, taking you into unwanted state territory. -jgArticle: 64957
x86asm wrote: > Hi, I would like to experiment with VHDL code, I was wondering if there > is any good free tools (dont care about limits) that I could use? Consider sonata for linux or windows. The free version will do what you need and the gui is very easy to use for a beginner. http://www.symphonyeda.com/proddownloads.htm -- Mike TreselerArticle: 64958
ram wrote: > Hi > I am using System ACE module from Insight with Virtex 2 pro board. > Of all the things i am facing a very trivial but more complicated > situation. > In order to make the files stored in flash card readable by system ace > module, it need to be formattted by win 98 not by win 2000 or XP( as > xilinx said formatting done by dos on win 2000 and xp has problems > ). > Any help on guiding me to find the formatting utility would be > appreciated. > Thanx for your effort and time. > Thank you > Regards > Ram nathan I've "formatted" CompactFlash disks that satisfy SystemACE using mkfs.msdos under Linux. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 64959
Kelvin @ SG wrote: > Hi, there: > > I am using ise WebPack for learning purpose. I am learning modular design > while > I can't live without the FPGA Editor...even if a viewer is okie... > > I used ISE w6.1.03, but there is no editor on it. > > May I know which version has this functionality on it? No versions of WebPack have FPGA Editor. You need a for-money version to get it. (My other gripe: No versions of WebPack support Linux native. Grumble.) -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 64960
I've been successful using the format command through the Windows2000 command prompt: format D: /FS:FAT /A:1024 This, and other solutions are detailed on the Xilinx support website. See answer record 14456.Article: 64961
Hi Jean, For Altera's FPGAs, the timing produced by Quartus will take into any internal voltage drops. So provided that your external Vdd does not drop below the minimum value spec'ed in the data sheet (for example, 1.425 V for Stratix/GX/Cyclone vs. 1.5V nominal), your timing report will be valid. Regards, Paul Leventis Altera Corp. "jean-francois hasson" <jfhasson@club-internet.fr> wrote in message news:40082283$0$6968$7a628cd7@news.club-internet.fr... > Hi, > > I have read the article about slack and margins written by Austin Lesea and > I am anxious to have more information concerning "any ripple or noise > detracts directly from the speed of the part. 200 mV peak-to-peak of noise > and ripple on the internal core power supply of a 1.5 volt part results in a > significant slowdown". How big is the impact of the ripple on the timings. I > believe the converters on the board I have can provide 50mV peak-to-peak of > ripple/noise. Will my timing margins degrade ? Any type of information will > be welcome. > > Thanks, > > JF > >Article: 64962
Hi Brannon, This type of optimization (and many others) could be done up-front by synthesis tools -- and I think some of them will do this. The netlists that 3rd party synthesis tools produce are composed of technology-mapped logic elements (LUT + some other stuff) and flip-flops, plus other gunk (RAMs, IOs, ...). However, synthesis is limited since it must guess what your critical path is. Not only must you make sure you inform your tools via timing constraints, but they must guess what the down-stream P&R tool will do. Irrespective of what synthesis tool you use, Quartus can perform netlist optimizations (aka localized resynthesis, or physical synthesis) in various stages of the placement and routing flow. The optimizations are performed based on the slack of various connections in your design, and thus the decisions will be timing-driven. The P&R tool has the advantage of knowing what the true critical path(s) of your design are, since it knows the placement and then routing used, and thus is in a good position to make these tweaks. By using Netlist Optimizations, Quartus can take a good synthesis result and make it even better! This option is NOT enabled by default in Quartus. The reason is that these optimizations can result in node name changes between your P&R netlist and your synthesis netlist, which can complicate the entry of constraints or running your design through formal verification. And you only need Netlist Optimizations when you are not meeting timing. To enable Netlist Optimizations, go to the Settings dialog box in the Assignments menu and select the Netlist Optimizations page. See AN297 (http://www.altera.com/literature/an/an297.pdf) and AN198 (http://www.altera.com/literature/an/an198.pdf).for more information on these and other methods for improving your design performance in Quartus. Or try out the "Design Space Explorer" tool. DSE will try a whole bunch of Quartus settings for you to find those that yield the best results for your design. Netlist Optimizations are just one of the things it tries. For more information on DSE and other ways to close timing in your design see AN198. Regards, Paul Leventis Altera Corp. "Brannon King" <bking@starbridgesystems.com> wrote in message news:bu6s3c$4s2@dispatch.concentric.net... > VHDL/Verilog compilers perform an optimization that I think should be done > in the mapper. I think it is part of the "slice packing." Maybe someone can > explain why this is done in this fashion. What I want is to use my 3rd-party > structural EDIF, and currently I'm having to perform this optimization > manually. The optimization is this: Suppose I have three OR gates where they > are cascaded such that the output of the first goes into the second and the > output of the second goes into a third. The other inputs for the three gates > all come from the same top layer. It is possible to reorder those gates such > that the first two OR gates are in the same layer and the third has inputs > coming from the first two gates. The Map/Par seems to have a much easier > time with the Timespec when I start out with the binary (latter) ordered > gates, yet I would think it would be an easy optimization for the mapper to > perform. Thoughts? > >Article: 64963
at Fri, 16 Jan 2004 14:53:36 GMT in <4007EF4F.16A1C673@yahoo.com>, cbfalconer@worldnet.att.net (CBFalconer) wrote : >Hans-Bernhard Broeker wrote: >> >> In comp.arch.embedded Alex Rast <ad.rast.7@nwnotlink.nospam.com> >> wrote: >> >> [...] >> >> > Because of the design of the board, I need >> > to use a synchronous, hardware-based protocol and interface to >> > transfer the data. >> >> "A ... protocol" meaning exactly _what_? I'm quite sure you don't >> just need some random protocol. You need a piece of hardware and >> software that generates and read _exactly_ that protocol your device >> under test uses. Actually, we can pretty much indeed use any protocol, as long as it's synchronous (i.e. uses a continuous clock signal to time transactions) That's the nice thing about an FPGA - it's reconfigurable. I designed an internal test port that on the one side has the interface to our bus inside the FPGA, and on the other side has an interface to whatever test fixture we decided to use. The external interface is interchangeable, so we can devise it to suit a wide variety of possible protocols. >Moral: Don't design hardware without first thinking about testing >it. Or at least enough of it :-) We did think very long and hard about testing, and had several meetings where we really examined the design carefully, with a view to testability. But there's also the side of that your board needs to do what it needs to do. There's not much good designing a highly testable board that doesn't perform the task you're designing it for. It does seem to me that the available testing options for high-speed, synchronous interfaces are very few and far between. The option that people have been recommending, of putting another identical board in our system to use as a test interface, is one I thought about and I think, with the consensus being that this is the best way to go, is what I'll do. Is this, then, the typical way people test high-speed cards and interfaces? I'm quite surprised that there aren't more testing/prototype systems available for these kinds of hardware, which must surely be extremely common. -- Alex Rast ad.rast.7@nwnotlink.NOSPAM.com (remove d., .7, not, and .NOSPAM to reply)Article: 64964
On the Stratix FPGA, -5 (fastest) speed grade, flip-chip package, the clock input can handle up to 400 MHz for 1.5 or 1.8 V HSTL. The fastest output clock is 225-250 MHz depending on whether this is HSTL Class I or II. So this alone precludes a 400 MHz RLDRAM II interface. Furthermore, there's more to the interface than toggle rate - for example, skew between the pins will impact timing. There is another comment in this thread about SPI-4.2 and HyperTransport running at 400 MHz DDR (800 Mbps per pin) on FPGAs. This is true, but keep in mind that that these are low-swing differential IO standards which can generally toggle faster than single-ended standards like HSTL. This is how FPGAs have had 840 Mbps LVDS since APEX 20KE was released some time ago. Also, some FPGAs (like Stratix) have a built in serial/parallel converter (and vice versa) so that the programmable logic never sees the high speed signal. For example, with an 800 Mbps SPI-4.2, you may have an 4:1 converter so that the logic in the device runs at 200 MHz. There's no such converter for HSTL other than the double-data rate IO buffers. Regards, Greg Steinke gregs@altera.com "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<dRDNb.11195$gD6.6510@newssvr25.news.prodigy.com>... > It's a single data path. > > It looks like none of the current FPGA's will support this in non-trivial > application. > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > > > > "Robert Sefton" <rsefton@abc.net> wrote in message > news:bu53b6$dpfal$1@ID-212988.news.uni-berlin.de... > > "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message > > news:r2nNb.1094$746.125@newssvr29.news.prodigy.com... > > > RLDRAM II can (will) hit 400MHz (2.5ns cycle) actual clock rate. Of > course, > > > still DDR, so 800Mb/s/pin peak. > > > > > > > Martin - > > > > Virtex-II (and Pro) should be able to handle that. Xilinx's SPI-4.2 and > > HyperTransport cores run up to 400MHz DDR (800Mbps per pin). I assume > > RLDRAM has separate (uni-directional) read and write paths? I can't > > imagine anything running bi-directional at those rates. > > > > Robert > > > >Article: 64965
Rene Tschaggelar <none@none.none> wrote in message news:<5677e0dea670f1a44d48a9926c42d73c@news.teranews.com>... > The Altera Cyclone Programming device EPCS1 are shown > to be programmed in the AS mode requiring an own connector. > Since the JTAG was never officially declared outdated, > I'd expect a way to program the cyclone plus the EPCS1 in JTAG > mode. I wasn't able to find it yet though. > > Rene Cyclone FPGAs are programmed using JTAG, or by Altera configuration prom devices, or by serial interface from a microprocessor or download cable. The EPCS1 configuration prom device is programmed using AS protocol, and does not support JTAG. - Subroto Datta Altera Corp.Article: 64966
Hello all, I am working on FFT and instead of using Xilinx Block RAM, I write the = memory block using VHDL codes. However, after compiling and = synthesizing, it seems like they are occupying the Xilinx FPGA slices. = Thus, it occupies a lot of CLB/gates. Is there any such away that the memory is written in our own vhdl code = but it occupies the memory allocation (Block RAM) in FPGA ? Thanks. Buzz=20Article: 64967
Probably in a related vein, Xilinx has removed the TimingChecksOn generic
from the clocked elements in the unisim library. Not a problem if you
never touched it, however the default value had been true, which created
some delta clock delay problems with mixed instantiated/inferred designs
a while back. As a result, my library, and I'm sure others has elements
with these primitives with the TimingChecksOn generic set to false. Now
with the new unisim library, it is completely gone, so any old code has
to be revised to be able to compile. Would have been much cleaner to
just leave the generic there as a dummy, even if it has no references in
the component.
lecroy wrote:
> If I look at your latest unisim_vital.vhd and the previous version of
> the file, there have been some major changes that effected my
> simulation. Interesting, once again the headers did not change. They
> still show the file not being updated after 1996, ending with change
> 86.
>
> I brought this up with the models in the past.
>
> Is there a reason that you don't want to take the time to document
> your work?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 64968
I've had some success dealing with customer's simulators that don't support
mixed languages by using the mapped output from synplicity in the target
language for simulation. It is not as fast, and I have occasionally had
problems with INIT= attributes passing through if other than the default, but
otherwise it works.
fabbl wrote:
> Mixed designs are supported by certain vendor tools. Modelsim SE has an
> integrated kernel. See http://www.model.com/products/pdf/datasheets/se.pdf
> page 2 for details.
>
> "ALuPin" <ALuPin@web.de> wrote in message
> news:b8a9a7b0.0401150750.76d8893a@posting.google.com...
> > Dear Sir or Madam,
> >
> > I have the following problem:
> >
> > I have a simulation component which is written in Verilog (not a trivial
> one
> > which could be translated to VHDL).
> > My toplevel design and all other components are written in VHDL.
> >
> > My question:
> >
> > Is it possible to include this Verilog component in my VHDL top level ?
> >
> > What about the types std_logic / std_logic_vector ?
> > Can I connect the inputs and outputs of the Verilog component to signals
> of
> > these types ?
> > How do I define it in the VHDL top level ?
> >
> > I do not know if such thing is possible but I would be very
> > thankful for any information about that.
> >
> >
> > Kind regards
> > Andrés Vázquez
> > G&D System Development
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 64969
Hi,I am currently doing research on the Elliptic Curve Cryptosystem
(ECC) on Smart Card Prototype.
I will build a ECC Smart card prototype and download the
entire design into Altera FPGA APEX Device which is EP20K200EFC484-2x.
This prototype does not have an embedded OS. To test and verify my
design, I will build a testbench for Elliptic Curve Digital Signature
and ECC-based Mutual Authentication.
Currently, the Operating System on my PC is Windows2000 with
NTFS File System. My Altera Nios Development Board communicates with
the PC through UART. To build the testbench, i need to write a
software which will be built and run on the Nios SDK shell and able to
do the following functions:
1. Open a new file or read a existing file (plain-text) in the
Operating System Windows2000 environemnt in my PC.
2. The file will be sent from my PC to my Smart Card prototype
through UART.
3. The file (plaintext) will be processed in my Smart Card
prototype to create a Digital Signature.
4. Both of the original file (plaintext) and the digital
signature will then sent back to PC from smart card prototype through
UART.
My question is: Does the Nios-gnupro support the file access
system such as fopen, fprintf, fclose? I have written a simple program
which is able to run on Visual Studio but can't execute while in
nios-build process. I wonder does the Nios-gnupro support the file
access system. Thanks for your reply. Wish you all have a nice day.
Article: 64970
>I could still manage something with the reset condition but that's not
>exactly what the datasheet says ("If <input signal> is strapped Low at
>power-up...")
What do you think "at power-up" means?
Most chips I've worked with have a separate reset signal that
must be held active until the power is stable. "at power-up"
really means when reset goes away. It's the designer's
job to make sure that doesn't happen before power is stable.
Usually the signals you are looking at are not "strapped"
(or the problem would be simple) but there is a weak pullup/down
that is strong enough as long as no real driver is driving
that signal but doesn't add much load to mess up the normal
use of that pin. So the other half of the designer's job
is to make sure that nothing else drives those signals
until the chip has come out of reset.
Sometimes that last paragraph is wrong. If you are loading
the FPGA from a uProc, the uProc might have control of those
signals so the software has to get it right rather than using
pullups/downs.
--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
Article: 64971>I am working on a project and I need to run different designs on a >variety of FPGAs. More specifically, I would like to have 4 to 9 FPGAs >running at once. I noticed that XILINX will not run in multiple >instances. What does that mean? How does a chip know wheather it is running alone or is part of a clump? > Is there any way that I can (1) simulate such a system? (2) >download the design for each FPGA to that particular FPGA? [I'm not a simulation wizard. No comments there.] Each chip has a set of pins that you use to load it. If you connect those pins up to the right source of bits you get the right design loaded into your chip. I suggest reading the data sheet. There is a big section on configuration. It's all there, but may take several passes to understand it. It's common to share many of the configuration pins by connecting several chips in a daisy chain. For two chips, you need to feed them twice as many bits - roughly one set of bits for each chip. You can load the same program into several chips if that's what you want to do. In that case, you only need one copy of the bits, but you have to wire up the chips differently than the daisy chain - parallel rather than series. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 64972
hi, you can do a number of things. use one of the synthesis templates provided with ISE from the EDIT menu. That code is behavioral in nature so should be similar to what you write. Also, you can set the option from the Synthesis - Process Properties under the HDL options tab, Where you can choose the RAM style as BLOCK (from the menu)... this should prevent XST from using slices to implement RAM. Hope this helps. Good luck ! Btw, which synthesizer are you using ? Cheers, Adarsh ----- Original Message ----- From: "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> Newsgroups: comp.arch.fpga Sent: Friday, January 16, 2004 9:25 PM Subject: Block RAM Hello all, I am working on FFT and instead of using Xilinx Block RAM, I write the memory block using VHDL codes. However, after compiling and synthesizing, it seems like they are occupying the Xilinx FPGA slices. Thus, it occupies a lot of CLB/gates. Is there any such away that the memory is written in our own vhdl code but it occupies the memory allocation (Block RAM) in FPGA ? Thanks. BuzzArticle: 64973
>We did think very long and hard about testing, and had several meetings >where we really examined the design carefully, with a view to testability. >But there's also the side of that your board needs to do what it needs to >do. There's not much good designing a highly testable board that doesn't >perform the task you're designing it for. It does seem to me that the >available testing options for high-speed, synchronous interfaces are very >few and far between. The option that people have been recommending, of >putting another identical board in our system to use as a test interface, >is one I thought about and I think, with the consensus being that this is >the best way to go, is what I'll do. Is this, then, the typical way people >test high-speed cards and interfaces? I'm quite surprised that there aren't >more testing/prototype systems available for these kinds of hardware, which >must surely be extremely common. I don't know if "typical" is the right word, but it seems like one of the obvious advantages of using an FPGA. (aka you can reprogram it to do something else) One important consideration for using your own board: You are already familiar with the tools and all the details of the hardware. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 64974
Hi there, I want to perform a timing simulation with ModelSim SE5.7e from the output generated by Quartus II 3.0. So, I add "mydesign.vho" to my modelsim project and it compiles without any errors or warnings. However, when I try to load the design for simulation (without *.sdo for now) the following is printed out: # Compile of mydesign.vho was successful. vsim work.mydesign(structure) # vsim work.mydesign(structure) # Loading C:/Modeltech_5.7e/win32/../std.standard # Loading C:/Modeltech_5.7e/win32/../ieee.std_logic_1164(body) # Loading C:/Modeltech_5.7e/win32/../std.textio(body) # Loading C:/Modeltech_5.7e/win32/../ieee.vital_timing(body) # Loading C:/Modeltech_5.7e/win32/../ieee.vital_primitives(body) # Loading work.atom_pack(body) # Loading work.apex20ke_components # Loading C:/Modeltech_5.7e/win32/../ieee.std_logic_arith(body) # Loading C:/Modeltech_5.7e/win32/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_5.7e/win32/../ieee.std_logic_textio(body) # Loading work.mydesign(structure) # Loading work.apex20ke_dpram(vital_dpram_atom) # Loading work.output_delay(v1) # ** Error: (vsim-7) Failed to open VHDL file "A()" in rb mode. # No such file or directory. (errno = ENOENT) # Time: 0 ns Iteration: 0 Instance: /mydesign/inst6_alpm_instance_adp0_adpram # ** Fatal: (vsim-7) Failed to open VHDL file "A()" in rb mode. # No such file or directory. (errno = ENOENT) # Time: 0 ns Iteration: 0 Process: /mydesign/inst6_alpm_instance_adp0_adpram/clock File: C:/quartus/eda/sim_lib/apex20ke_atoms.vhd # FATAL ERROR while loading design # Error loading design Anybody can help? Regards, Cornel Arnet
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z