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chuk wrote: > Generating clock delays > > I am relatively new to VHDL so pleas excuse me if this is too easy a > question. I need to be able to generate a time shifted version of the > clk signal for control purposes in an Xilinx based project. There are > several options that I have come across: > > -Using the after ??n, but this dose not seem to generate any > difference Yes, synthesis ignores after statements generally. > -using the wait until statement though this is not supported by Xilinx > for some reason That's basically the same problem as with "after". > -using the dll (is this the most efficient manor?) That's the way to go - provided that your FPGA implements such a circuitry. DLLs are there for exactly such purposes. > I would like someone to tell me which is the best and most > controllable manor of generating a clock delay. Thanks Another alternative is to feed the clock through some normal circuitry. But you can't describe this in VHDL. Instead, you need to create a hard-macro that does nothing more than propagating the signal from input to output. Depending on the timing information you receive in the data sheets, you can calculate how often the signal needs to be feed through some LUTs or other parts. Although this method is not the very best one, it is working fine in many cases. Regards, MarioArticle: 64851
ramntn@yahoo.com (ram) wrote in message news:<61c2cc9d.0401142200.61fb3d7@posting.google.com>... > Hi Edward. > ModelSIm XE supports only 500 lines of code, so you need to get > ModelSim SE/PE to run MicroBlaze simulation. > bye > Ram Hi Ed, Possibly a cheaper and more effective option to buying Modelsim SE/PE is to get yourself a QuartusII and a NIOS dev kit. Not only will you have a much better,flexible and mature embedded micro core, you'll be able to simulate to your hearts content with the Modelsim OEM. -- Rich.Article: 64852
In article <W9rNb.1068$vK3.331@fe02.usenetserver.com>, ching_wang@REMOVE.THE.OBVIOUS.alltel.net says... > This is a question related to input pin on 1.8V Spartan IIE. Datasheets said > it is "5V tolerant with external resistor." What should the value of this > external resistor be? What value in the datasheet are you based on to > calculate the necessary voltage drop on this resistor? I am mainly a > firmware person, just start looking into FPGAs... > Thanks! > 100 Ohms... -- Greg Deuerling Fermi National Accelerator Laboratory P.O.Box 500 MS368 Batavia, IL 60510 (630)840-4629 FAX (630)840-5406 Electronic Systems Engineering Group Work: egads_AT_fnal.gov, remove '_AT_'Article: 64853
Peter Alfke wrote: > Rene Tschaggelar wrote: > >>>Thanks Peter, >> >>the first sensible answer. What is wrong with a simple formula ? >>Eg Imax = Io + 4mA/Mhz + I/O_load. >> >>It'd help specifying the power supply as well as the heatsink. >> > > Rene, unfortunately it is not that simple. > • Io is just the static leakage current, which tends to be > junction-temperature dependent, and unfortunately has increased > dramatically with 130 and 90 nm technology. Like a hundred times :-( > • mA per MHz depends on the frequency of each node, times the > capacitance of that node, and all this accumulated over the whole chip. > Some people (notably our friendly A competitor) make the tacit > assumption that everything behaves like a 16-bit counter, But that can > lead to very optimistic results, compared to a real DSP-like circuit > where everything is clocked at 300 MHz, and half the flip-flops and > interconnects change each clock period. > • I/O load is usually not static, but rather a load driving board- and > input capacitances. So you again need the capacitance and average > frequency of each pin. > > This is why power calculation is such a chore. > On top of this, a 50% tolerance guess is no good. You don't want to > guardband your supply by a factor 2, and you definitely cannot be wrong > by a factor 2 when you calculate the junction over-temperature. > Theoretically, you have only between 50 (?) degrees max inside the box, > and 85 degrees at the junction. There is not much room to make a > mistake and accept an error or even a widetolerance. > > That's why I have recommended for years to "try it out". With FPGAs (but > not with ASICs) that is relatively easy, and you can be within a few > percentage points. You will see hardly any variation between speed > grades in this respect... > > This is not a pretty story, but it might help when you understand > the difficulties. Thanks Peter, I recognize that a lot of factors, some beyond control, influence the current consumption. I'm in the low quantity market, where the design is a major cost factor and the hardware cost is secondary. A must is flexibility. Meaning that long after the prototype, when the stuff is in production, the customer may have an additional wish which could be fulfilled with the remaining 10 to 60% of the cells. Whatever it is, it shouldn't be restricted by the power supply. I'd even be prepared to have a four times stronger switcher already on the board. This still comes cheaper than a new design. When the external power supply needs to be stronger too, that shouldn't be a problem as the customer provides for it. I'm in the process of designing a new generic digital board that should be useable for few years without yet having an idea about the applications. Therefore I take a medium sized FPGA with 100k gates, the fastest version. There is a lot more stuff on the board, but the FPGA may make up for the most power consumption. I'm having the impression that supplying chips which draw a lot of current is considered loosing the face amongst the competitors. Nevertheless if no one wants to burn the fingers, there could be competitions on who can burn the most (or least current) in a specific chip while hinting on the kind of applications at what clock rate. I'm also aware that by fine tuning the design, one can trade speed against size. So it is not only the chip that burns current, but also to a however large degree the design. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 64854
chuk wrote: > Generating clock delays > > I am relatively new to VHDL so pleas excuse me if this is too easy a > question. I need to be able to generate a time shifted version of the > clk signal for control purposes in an Xilinx based project. There are > several options that I have come across: > > -Using the after ??n, but this dose not seem to generate any > difference > -using the wait until statement though this is not supported by Xilinx > for some reason > -using the dll (is this the most efficient manor?) > > I would like someone to tell me which is the best and most > controllable manor of generating a clock delay. Thanks The usual approach for such a problem is to have a PLL. There are chips, such as the Cypress CY7B9911 clock skew buffer, or the Cypress CY7B9930 multi frequency PLL clock buffer. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 64855
Hi, there: I am using ise WebPack for learning purpose. I am learning modular design while I can't live without the FPGA Editor...even if a viewer is okie... I used ISE w6.1.03, but there is no editor on it. May I know which version has this functionality on it? Best Regards, KelvinArticle: 64856
Dear Sir or Madam, I have the following problem: I have a simulation component which is written in Verilog (not a trivial one which could be translated to VHDL). My toplevel design and all other components are written in VHDL. My question: Is it possible to include this Verilog component in my VHDL top level ? What about the types std_logic / std_logic_vector ? Can I connect the inputs and outputs of the Verilog component to signals of these types ? How do I define it in the VHDL top level ? I do not know if such thing is possible but I would be very thankful for any information about that. Kind regards Andrés Vázquez G&D System DevelopmentArticle: 64857
inaganti_suni@yahoo.com (sunil) wrote in message news:<9f28d282.0401080128.3a9ab0b@posting.google.com>... > i am designing viterbi decoder. i have one problem. i am doing 3bit > quantiser for quantizing the received symbols(noise addedsymbols). but > my problem is from which number to which number i have to take as > quantization level. either from 0 to 7 or -3 to 4. depending on those > the branch metric is varying. which will give minimum metric as best > metric. i am planning to calculate hamming distance. > if any body have the idea on this please mail me. > thank u. > bye Hi, I am designing the same as you. If you plane to use Hamming distance then definitely use [0:7]. I have tested it and compared with Matlab's Viterbi. Good luckArticle: 64858
Mixed designs are supported by certain vendor tools. Modelsim SE has an integrated kernel. See http://www.model.com/products/pdf/datasheets/se.pdf page 2 for details. "ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0401150750.76d8893a@posting.google.com... > Dear Sir or Madam, > > I have the following problem: > > I have a simulation component which is written in Verilog (not a trivial one > which could be translated to VHDL). > My toplevel design and all other components are written in VHDL. > > My question: > > Is it possible to include this Verilog component in my VHDL top level ? > > What about the types std_logic / std_logic_vector ? > Can I connect the inputs and outputs of the Verilog component to signals of > these types ? > How do I define it in the VHDL top level ? > > I do not know if such thing is possible but I would be very > thankful for any information about that. > > > Kind regards > Andrés Vázquez > G&D System DevelopmentArticle: 64859
The DLL in Virtex-II or Spartan3 (we call it DCM=digital clock manager) is the way to go. You feed it a continuously-running clock, and you generate outputs that are delayed by a fraction of the clock period ( defined as integer multiple of clock period divided by 256). Works very nicely! Peter Alfke, Xilinx chuk wrote: > > Generating clock delays > > I am relatively new to VHDL so pleas excuse me if this is too easy a > question. I need to be able to generate a time shifted version of the > clk signal for control purposes in an Xilinx based project. There are > several options that I have come across: > > -Using the after ??n, but this dose not seem to generate any > difference > -using the wait until statement though this is not supported by Xilinx > for some reason > -using the dll (is this the most efficient manor?) > > I would like someone to tell me which is the best and most > controllable manor of generating a clock delay. ThanksArticle: 64860
I need help in creating constants to be used with schematic capture.
In previous versions of Xilinx ISE I used to create schematic symbols
for constants (i.e. 0xA5) by creating a schmetic with 8 buffers. The
inputs were connected to gnd or vcc to create the constant. The
outputs of the buffer were connected to a bus CONST(7:0).
Then I could use this constant anywhere in my schematic by inserting
this part.
I tried this on the latest ISE 6.1 and got the following error when I
compiled.
ERROR:Xst:1539 - C:/Projects/DemoTop.vhf line 122: Formal port in
component <const8_80> must be an identifier.
Here is the DemoTop.vhf output:
XLXI_30 : const8_80
port map (Const(7 downto 0)=>XLXN_12(7 downto 0));
Why doesn't this work anymore? Is there a better way to create a
constant. I know that Altera has a constant macro. Is there any easy
way in Xilinx.
Thanks,
Bob
P.S. Please post the answer in the newsgroup rather than emailing it.
Article: 64861100 Ohms of you are after speed. Any higher value, let's say up to 1 kilohm, if the RC delay (C of the connection and input capacitance) is acceptable. 1 kilohm times 20 pF = 20 ns Peter Alfke, Xilinx ========== Egads wrote: > > In article <W9rNb.1068$vK3.331@fe02.usenetserver.com>, > ching_wang@REMOVE.THE.OBVIOUS.alltel.net says... > > This is a question related to input pin on 1.8V Spartan IIE. Datasheets said > > it is "5V tolerant with external resistor." What should the value of this > > external resistor be? What value in the datasheet are you based on to > > calculate the necessary voltage drop on this resistor? I am mainly a > > firmware person, just start looking into FPGAs... > > Thanks! > > > 100 Ohms... > -- > Greg Deuerling > Fermi National Accelerator Laboratory > P.O.Box 500 MS368 Batavia, IL 60510 > (630)840-4629 FAX (630)840-5406 > Electronic Systems Engineering Group > Work: egads_AT_fnal.gov, remove '_AT_'Article: 64862
Kelvin @ SG <kelvin8157@hotmail.com> wrote: : Hi, there: : I am using ise WebPack for learning purpose. I am learning modular design : while : I can't live without the FPGA Editor...even if a viewer is okie... : I used ISE w6.1.03, but there is no editor on it. : May I know which version has this functionality on it? Webpack comes without FPGA Editor... That's the priceb you have to pay that Webpack comes at no costs... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 64863
What are you talking about? "cruzin" <cruiser144@hotmail.com> wrote in message news:775730eb.0401142320.250e4218@posting.google.com... > Hello, > > I can download a program to memory using "nios-run my_prog.srec" and > it works fine. > > However, when I write the program into the same memory manually (ie. > memory fill command), nios will not wrong the program properly. > > I verified that both methods write exactly the same program bytes into > memory, but nios-run does something with the memory AFTER the program > end. This must be the source of my problems. Why are bytes changed > after the end of the program? > > I verified every byte up until the last byte written as defined by the > S-Record. > > Any ideas on what steps nios-run goes through? > > Help is greatly appreciated.Article: 64864
Hi: I am using Xilinx Webpack and Modelsim XEII starter 5.7c to simulate Verilog. If I put a `timescale directive in my uut, the compiler complains "module 'xxx' has a `timescale directive in effect, but previous modules do not." If I don't put in a `timescale directive, then it makes the same message about the 'glbl' module. Right now it gives peculiar results with the `timescale 10ns/1ns in my source, but simulates correctly without the directive. Trouble is, it has units of 1ps for each timestep without the directive. How can I properly use the `timescale directive? This is only for functional simulation to learn Verilog. I know that things will get more complicated for synthesis for real devices. Thanks for comments. Good day! -- ____________________________________ Christopher R. Carlen Principal Laser/Optical Technologist Sandia National Laboratories CA USA crcarle@sandia.govArticle: 64865
Not true :) You can only select NIC ID's already on file. I've complained to no avail about this. Just call Altera and get your license. The licensing people are very nice, they just don't have the ability to change how the web form works. (or doesn't work IMO) Hint: If your machine moves around and may not be on a lan then request that they tie it to your hard drive ID. Ken "Petter Gustad" <newsmailcomp5@gustad.com> wrote in message news:m3n08pk45h.fsf@scimul.dolphinics.no... > dreamguy007@hotmail.com (Jack) writes: > > > altera.com/licensing website, it needs NIC ID that was used to buy the > > kit. i won the kit, didn't buy it. any clue? > > It's the NIC ID of your license server host, or the host where you > will run the software if you don't have a dedicated license server. > > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail?Article: 64866
Hi,
I am using a Virtex 2 Pro (V2P7) device to perform some deserialization and
8b/10b decoding.
I use ISE 6.1SP3 and Active HDL 6.1 SP2.
Its a very simple design and right now all I am trying to do is to get
something out of the tranceiver.
The code is given below :
The DCM parts simulate ok but I am not sure about how to drive the RXP and
RXN inputs to the Transceiver.
I try to feed opposite polarity clocks into them in the hope that at least
Recoverd Clock i should get to see.
But i see nothing...
Any help will be apprecaiated,
Thanks in advance
//Top Level
module GT_TOP
(DinP,DinN,ClkP,ClkN,Dout,DCMLocked,RefClk80,UsrClk,RXRECCLK,RXRESET);
input DinP;
input DinN;
input ClkP,ClkN;
input RXRESET;
output [15:0] Dout;
output DCMLocked;
output RefClk80;
output UsrClk;
output RXRECCLK;
// ********************************************************************
// ******************** CLOCK SECTION *****************
// *********************************************
// XST is stupid at handling clocks and clock buffer, so we instantiate
// all the buffers and inihbit XST from changing them with the attribute.
wire RefClk80;
wire DCMLocked;
wire UsrClk,DCMClkFBOut,DCMUsrClk,DCMClkFBIn;
// Instantiate the Differential Global Input Buffer
IBUFGDS DIFCLKBUF (.I(ClkP), .IB(ClkN), .O(RefClk80) );
//synthesis attribute clock_buffer of ClkP is "none"
//synthesis attribute clock_buffer of ClkN is "none"
BUFG USRCLKBUF (.I(DCMUsrClk), .O(UsrClk)); // Use this output as
User clock to GTs
//synthesis attribute clock_buffer of DCMUsrClk is "none"
BUFG FBCLKBUF (.I(DCMClkFBOut), .O(DCMClkFBIn)); // clock for feedback
//synthesis attribute clock_buffer of DCMClkFBOut is "none"
// synthesis translate_off
defparam DCMGT.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCMGT.FACTORY_JF = 16'hC080;
defparam DCMGT.CLKDV_DIVIDE = 2.0;
defparam DCMGT.CLKFX_DIVIDE = 1;
defparam DCMGT.CLKFX_MULTIPLY = 4;
defparam DCMGT.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCMGT.CLK_FEEDBACK = "1X";
defparam DCMGT.DLL_FREQUENCY_MODE = "LOW";
defparam DCMGT.PHASE_SHIFT = 0;
defparam DCMGT.SIM_CLKIN_CYCLE_JITTER = 300;
defparam DCMGT.SIM_CLKIN_PERIOD_JITTER = 1000;
defparam DCMGT.MAXPERCLKIN = 41668;
defparam DCMGT.MAXPERPSCLK = 1264998735;
//synthesis translate_on
//synthesis attribute CLKDV_DIVIDE of DCMGT is "2.0"
//synthesis attribute DUTY_CYCLE_CORRECTION of DCMGT is "TRUE"
DCM DCMGT
(
.CLK0 (DCMClkFBOut),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLK90 (),
.CLKDV (DCMUsrClk),
.CLKFX (),
.CLKFX180 (),
.LOCKED (DCMLocked),
.PSDONE (),
.STATUS (),
.CLKFB (DCMClkFBIn),
.CLKIN (RefClk80),
.DSSEN (1'b0),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.RST (1'b0)
);
wire RXRESET;
wire [1:0] RXBUFSTATUS;
wire [1:0] RXCHARISCOMMA;
wire [1:0] RXCHARISK;
wire RXCOMMADET;
wire [1:0] RXDISPERR;
wire [1:0] RXLOSSOFSYNC;
wire [1:0] RXNOTINTABLE;
wire RXREALIGN;
wire RXRECCLK;
wire [1:0] RXRUNDISP;
gtmacro1 GT1 (
.CONFIGENABLE(1'b0),
.CONFIGIN(1'b0),
.ENMCOMMAALIGN(1'b0),
.ENPCOMMAALIGN(1'b0),
.POWERDOWN(1'b0),
.REFCLK(RefClk80),
.REFCLK2(RefClk80),
.REFCLKSEL(1'b0),
.RXN(DinN),
.RXP(DinP),
.RXPOLARITY(1'b0),
.RXRESET(RXRESET),
.RXUSRCLK(UsrClk),
.RXUSRCLK2(UsrClk),
.TXUSRCLK(UsrClk),
.TXUSRCLK2(UsrClk),
.CONFIGOUT(),
.RXBUFSTATUS(RXBUFSTATUS),
.RXCHARISCOMMA(RXCHARISCOMMA),
.RXCHARISK(RXCHARISK),
.RXCLKCORCNT(),
.RXCOMMADET(RXCOMMADET),
.RXDATA(Dout),
.RXDISPERR(RXDISPERR),
.RXLOSSOFSYNC(RXLOSSOFSYNC),
.RXNOTINTABLE(RXNOTINTABLE),
.RXREALIGN(RXREALIGN),
.RXRECCLK(RXRECCLK),
.RXRUNDISP(RXRUNDISP)
);
endmodule
// instantiation of the macro
module gtmacro1(
CONFIGENABLE,
CONFIGIN,
ENMCOMMAALIGN,
ENPCOMMAALIGN,
POWERDOWN,
REFCLK,
REFCLK2,
REFCLKSEL,
RXN,
RXP,
RXPOLARITY,
RXRESET,
RXUSRCLK,
RXUSRCLK2,
TXUSRCLK,
TXUSRCLK2,
CONFIGOUT,
RXBUFSTATUS,
RXCHARISCOMMA,
RXCHARISK,
RXCLKCORCNT,
RXCOMMADET,
RXDATA,
RXDISPERR,
RXLOSSOFSYNC,
RXNOTINTABLE,
RXREALIGN,
RXRECCLK,
RXRUNDISP);
input CONFIGENABLE;
input CONFIGIN;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input TXUSRCLK;
input TXUSRCLK2;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [1:0] RXCHARISCOMMA;
output [1:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [15:0] RXDATA;
output [1:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [1:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [1:0] RXRUNDISP;
GT_ETHERNET_2 GT_ETHERNET_INST(
.CONFIGENABLE (CONFIGENABLE),
.CONFIGIN (CONFIGIN),
.ENMCOMMAALIGN (ENMCOMMAALIGN),
.ENPCOMMAALIGN (ENPCOMMAALIGN),
.LOOPBACK (2'b00),
.POWERDOWN (POWERDOWN),
.REFCLK (REFCLK),
.REFCLK2 (REFCLK2),
.REFCLKSEL (REFCLKSEL),
.BREFCLK (1'b0),
.BREFCLK2 (1'b0),
.RXN (RXN),
.RXP (RXP),
.RXPOLARITY (RXPOLARITY),
.RXRESET (RXRESET),
.RXUSRCLK (RXUSRCLK),
.RXUSRCLK2 (RXUSRCLK2),
.TXBYPASS8B10B (2'b00),
.TXCHARDISPMODE (2'b00),
.TXCHARDISPVAL (2'b00),
.TXCHARISK (2'b00),
.TXDATA (16'b0000000000000000),
.TXFORCECRCERR (1'b0),
.TXINHIBIT (1'b0),
.TXPOLARITY (1'b0),
.TXRESET (1'b0),
.TXUSRCLK (TXUSRCLK),
.TXUSRCLK2 (TXUSRCLK2),
.CONFIGOUT (CONFIGOUT),
.RXBUFSTATUS (RXBUFSTATUS[1:0]),
.RXCHARISCOMMA (RXCHARISCOMMA[1:0]),
.RXCHARISK (RXCHARISK[1:0]),
.RXCHECKINGCRC (),
.RXCLKCORCNT (RXCLKCORCNT[2:0]),
.RXCOMMADET (RXCOMMADET),
.RXCRCERR (),
.RXDATA (RXDATA[15:0]),
.RXDISPERR (RXDISPERR[1:0]),
.RXLOSSOFSYNC (RXLOSSOFSYNC[1:0]),
.RXNOTINTABLE (RXNOTINTABLE[1:0]),
.RXREALIGN (RXREALIGN),
.RXRECCLK (RXRECCLK),
.RXRUNDISP (RXRUNDISP[1:0]),
.TXBUFERR (),
.TXKERR (),
.TXN (),
.TXP (),
.TXRUNDISP ());
// synthesis attribute ALIGN_COMMA_MSB of GT_ETHERNET_INST is "FALSE"
// synthesis attribute CHAN_BOND_LIMIT of GT_ETHERNET_INST is 1
// synthesis attribute CHAN_BOND_MODE of GT_ETHERNET_INST is "OFF"
// synthesis attribute CHAN_BOND_OFFSET of GT_ETHERNET_INST is 0
// synthesis attribute CHAN_BOND_ONE_SHOT of GT_ETHERNET_INST is "TRUE"
// synthesis attribute CHAN_BOND_SEQ_2_USE of GT_ETHERNET_INST is "FALSE"
// synthesis attribute CHAN_BOND_SEQ_LEN of GT_ETHERNET_INST is 1
// synthesis attribute CHAN_BOND_WAIT of GT_ETHERNET_INST is 7
// synthesis attribute CLK_CORRECT_USE of GT_ETHERNET_INST is "TRUE"
// synthesis attribute CLK_COR_INSERT_IDLE_FLAG of GT_ETHERNET_INST is
"FALSE"
// synthesis attribute CLK_COR_KEEP_IDLE of GT_ETHERNET_INST is "FALSE"
// synthesis attribute CLK_COR_REPEAT_WAIT of GT_ETHERNET_INST is 1
// synthesis attribute CLK_COR_SEQ_1_1 of GT_ETHERNET_INST is 00110111100
// synthesis attribute CLK_COR_SEQ_1_2 of GT_ETHERNET_INST is 00001010000
// synthesis attribute CLK_COR_SEQ_1_3 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_1_4 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_2_1 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_2_2 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_2_3 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_2_4 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_2_USE of GT_ETHERNET_INST is "FALSE"
// synthesis attribute CLK_COR_SEQ_LEN of GT_ETHERNET_INST is 2
// synthesis attribute COMMA_10B_MASK of GT_ETHERNET_INST is 1111111000
// synthesis attribute CRC_END_OF_PKT of GT_ETHERNET_INST is "K29_7"
// synthesis attribute CRC_FORMAT of GT_ETHERNET_INST is "ETHERNET"
// synthesis attribute CRC_START_OF_PKT of GT_ETHERNET_INST is "K27_7"
// synthesis attribute DEC_MCOMMA_DETECT of GT_ETHERNET_INST is "TRUE"
// synthesis attribute DEC_PCOMMA_DETECT of GT_ETHERNET_INST is "TRUE"
// synthesis attribute DEC_VALID_COMMA_ONLY of GT_ETHERNET_INST is "TRUE"
// synthesis attribute MCOMMA_10B_VALUE of GT_ETHERNET_INST is 1100000000
// synthesis attribute MCOMMA_DETECT of GT_ETHERNET_INST is "TRUE"
// synthesis attribute PCOMMA_10B_VALUE of GT_ETHERNET_INST is 0011111000
// synthesis attribute PCOMMA_DETECT of GT_ETHERNET_INST is "TRUE"
// synthesis attribute RX_BUFFER_USE of GT_ETHERNET_INST is "TRUE"
// synthesis attribute RX_CRC_USE of GT_ETHERNET_INST is "FALSE"
// synthesis attribute RX_DATA_WIDTH of GT_ETHERNET_INST is 2
// synthesis attribute RX_DECODE_USE of GT_ETHERNET_INST is "TRUE"
// synthesis attribute RX_LOSS_OF_SYNC_FSM of GT_ETHERNET_INST is "FALSE"
// synthesis attribute RX_LOS_INVALID_INCR of GT_ETHERNET_INST is 1
// synthesis attribute RX_LOS_THRESHOLD of GT_ETHERNET_INST is 4
// synthesis attribute TERMINATION_IMP of GT_ETHERNET_INST is 50
// synthesis attribute SERDES_10B of GT_ETHERNET_INST is "TRUE"
// synthesis attribute TX_BUFFER_USE of GT_ETHERNET_INST is "TRUE"
// synthesis attribute TX_CRC_FORCE_VALUE of GT_ETHERNET_INST is 11010110
// synthesis attribute TX_CRC_USE of GT_ETHERNET_INST is "FALSE"
// synthesis attribute TX_DATA_WIDTH of GT_ETHERNET_INST is 2
// synthesis attribute TX_DIFF_CTRL of GT_ETHERNET_INST is 500
// synthesis attribute TX_PREEMPHASIS of GT_ETHERNET_INST is 0
// synthesis attribute REF_CLK_V_SEL of GT_ETHERNET_INST is 0
// synthesis translate_off
defparam GT_ETHERNET_INST.CLK_COR_INSERT_IDLE_FLAG="FALSE";
defparam GT_ETHERNET_INST.CLK_COR_KEEP_IDLE="FALSE";
defparam GT_ETHERNET_INST.CLK_COR_REPEAT_WAIT=1;
defparam GT_ETHERNET_INST.RX_CRC_USE="FALSE";
defparam GT_ETHERNET_INST.RX_LOSS_OF_SYNC_FSM="FALSE";
defparam GT_ETHERNET_INST.RX_LOS_INVALID_INCR=1;
defparam GT_ETHERNET_INST.RX_LOS_THRESHOLD=4;
defparam GT_ETHERNET_INST.TERMINATION_IMP=50;
defparam GT_ETHERNET_INST.SERDES_10B="TRUE";
defparam GT_ETHERNET_INST.TX_CRC_FORCE_VALUE=8'b11010110;
defparam GT_ETHERNET_INST.TX_CRC_USE="FALSE";
defparam GT_ETHERNET_INST.TX_DIFF_CTRL=500;
defparam GT_ETHERNET_INST.TX_PREEMPHASIS=0;
defparam GT_ETHERNET_INST.REF_CLK_V_SEL=0;
// synthesis translate_on
endmodule
Article: 64867Allan Herriman wrote: > (including a broken ASIC). This seems to be more of a problem in > testbenches, because designers typically don't introduce delta delays > to clocks in synthesisable code. Yes, and this is one good reason to use a synchronous style in vhdl sim models and testbenches. -- Mike TreselerArticle: 64868
Params: Xilinx's PCIX core for PCI64/PCIX at 66MHz 2v4000-4 running the controller core with 40 Fifos (10 targets, 2 channels, r/w) and a busmaster wrapper Tyan 2721 MB w/Xeon 2.6GHz w/ 4GB RAM Win2k Server sp4 No scatter/gather support in driver Exact same software and hardware for both reads and writes Bus commands 1110 and 1111 Results: Max host write speed: 70MB/s Max host read speed: 230MB/s Development time: six months w/ two engineers for both driver and core wrapper The timer does not include the memory allocations. Any ideas why the write speed is so much slower? Would it be the latency parameters in the core? An OS issue?Article: 64869
Just curious: Do any Altera/Xilinx engineers actually read this forum? And actually post answers? Prefer the forums on your websites? Prefer tech support emails?Article: 64870
Brannon King <bking@starbridgesystems.com> wrote: : Just curious: Do any Altera/Xilinx engineers actually read this forum? And : actually post answers? Prefer the forums on your websites? Prefer tech : support emails? Do _you_ read the forum? Do you use the archive? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 64871
VHDL/Verilog compilers perform an optimization that I think should be done in the mapper. I think it is part of the "slice packing." Maybe someone can explain why this is done in this fashion. What I want is to use my 3rd-party structural EDIF, and currently I'm having to perform this optimization manually. The optimization is this: Suppose I have three OR gates where they are cascaded such that the output of the first goes into the second and the output of the second goes into a third. The other inputs for the three gates all come from the same top layer. It is possible to reorder those gates such that the first two OR gates are in the same layer and the third has inputs coming from the first two gates. The Map/Par seems to have a much easier time with the Timespec when I start out with the binary (latter) ordered gates, yet I would think it would be an easy optimization for the mapper to perform. Thoughts?Article: 64872
Hi! I'm trying to synthecize a pic VHDL core on Altera Quartus II web edition, but when I make changes on the ROM.vhdl(It's using Case-When clauses), the compiler reports: ; Total logic elements ; 0 ; ; Total pins ; 20 ; ; Total memory bits ; 0 ; ; Total PLLs ; 0 if I don't change the rom program, it reports: ; Total logic elements ; 2,137 ; ; Total pins ; 20 ; ; Total memory bits ; 0 ; ; Total PLLs ; 0 ; . Someone can tell me why this it happen? Thank you, Andre, Student of science computer - BrazilArticle: 64873
Brannon, If I start a timer, and see how long it takes to successfully answer a question, Xilinx Hotline wins most of the time over this newsgroup. As it should. The hotline is not well suited to questions like: how do I compare two different FPGAs? But, this newsgroup does offer what other people might think, and what they have knowledge of. Hence it is valuable. Peter, and I read this newsgroup for Xilinx, as well as other Xilinx employees who read it for other reasons than replying. If you are a student and use Xilinx, there is a student forum dedicated to answering questions, and supporting you (see our website for details). Austin Brannon King wrote: > Just curious: Do any Altera/Xilinx engineers actually read this forum? And > actually post answers? Prefer the forums on your websites? Prefer tech > support emails? > >Article: 64874
Interesting question. I am a Xilinx engineer, and I have posted a few thousand times on this newsgroup. I think I am one of the three most prolific writers here. And I almost always include the name Xilinx in my signature... So, what is your real question? Peter Alfke, Xilinx Applications ========================================= Brannon King wrote: > > Just curious: Do any Altera/Xilinx engineers actually read this forum? And > actually post answers? Prefer the forums on your websites? Prefer tech > support emails?
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