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My advisor assigned me a problem which is to monitor the value of active pins of an ARM processor which will run a embedded OS. The ARM processor is on an evaluation board - amtel eb63 and the OS is dos-like. I have wiggler in hand. Boss's idea is using the boundary-scan to get the value while the OS is running. Please tell me if it is possible to do this and what I should do or learn to finish this task. Thanks TCHArticle: 64526
Hi Silvia, Are you trying to readback the current value stored in the register? Currently, iMPACT supports reading back and verifying through BSCAN interface. To capture the current value in the register, you'll have to instantiate the capture block. You can learn more about this in XAPP138. Also, you may want to contact the Xilinx hotline support for detailed current work arounds solutions using iMPACT/XSVF player to capture the desired register values. Regards, Wei Xilinx Applications Turquesa wrote: > I am working with a spartan2e and i wish readback the register, not my > configuration, i read that is posible, i am using iMPACT and it have a > option READBACK, but is always disenable. > Any help is welcome > thanks, SilviaArticle: 64527
chi wrote: > Hello, > > Can anyone help me to get the programming sequence of CoolRunner CPLD > to program through boundary-scan pins? > > Regards, > chi I advice you to use to remote the JTAG from SVF file or a binary file of SVF if you want to remote from an embedded processor. SVF is a nice ASCII file format. Both XILINX and ALTERA pupose this format. AND the format is supported by many ATPG for Boundary Scan (Board TEST). NOTE: the SVF is nice for downloading FPGA and CPLD or for testing PCB, but is to heavy for debugging processor ! If your are doing a commercial product, we have build our own SVF player (actually we can remote JTAG for any XILINX FPGA/CPLD or ALTERA FPGA). Written in native C, we have tested it from a PC over EPP port and from our ARM platform. (fully used by our Chameleon POD Programmer) Contact me for more info. Regards, Laurent Gauch www.amontec.comArticle: 64528
I am working on a design involving 2 4028EX devices along with an external SRAM bank. Is there a way I can simulate both post-synthesis netlists together? I'm trying to find a way where I can model the memory and chip interconnects and then simulate the whole system. The devices are on a PCI card which is one if the reasons just using a larger chip isn't an option. ThanksArticle: 64529
Thank you very much. The paper reads: In addition to the CORDIC vectoring and rotation modes, Tab. 2 also shows how to elegantly implement the MAC and DAC (divide-and-accumulate) operations using CORDIC arithmetic: MAC: yout=yout'+xin*yin, DAC: xout=xout'+xin/yin At first, I have the same doubt. But it states clearly. > > I don't see any relation between MAC/DAC and CORDIC. > Can you quote the relevant section of the paper? > Maybe you misread it. > > - LarryArticle: 64530
Chi, we could not get through to your e-mail address. Here is what I have been asked to forward to you through the newsgroup: "Chi, Peter Alfke forwarded your request for help on CoolRunner programming through JTAG. Can you tell me more about what you are trying to do ( which parts, what software, cables, etc. that you have). I run the CPLD applications group and either someone on my team, the Configurations Solutions team, or the hotline can give you a hand. Tell me more and I can direct the solution. Jesse Jenkins, Xilinx jesse@xilinx.com " chi wrote: > > Hello, > > Can anyone help me to get the programming sequence of CoolRunner CPLD > to program through boundary-scan pins? > > Regards, > chiArticle: 64531
Hello I am trying to use AFX BG560-100 board from xilinx.(http://www.xilinx.com/xlnx/xebiz/board_detail.jsp?key=HW-AFX-BG560-100&category=) I have XCV 1000 fgpa chips to use with the board. I have never used this board before.I was using Dililentinc board till this. 1.Can anyone tell me how to start using this board for simple applications. 2.How to use the prototype area in the board. 3.can i use the same ISE webpack software 5.1i to program this chips with the board or is there any other software. Thanks in advance.It would be of great help. bhadri.Article: 64532
Hello can anyone say me what is the difference between virtex and spartan fgpa chips. It is just the number of gates in them, voltage levels or anything more than that. I have used spartan chips.i configured the chip with different vhdl files again and again on the same chip.But somebody said it is not possible in the xcv1000 virtex chips.(dynamically reconfigurable).Is it true.Then,y are they called FPGA's. Thanks in advance bhadriArticle: 64533
I just used this board for my project a few weeks ago but this is off the top of my head so some things may be wrong. My goal was only a 30-40 cycle test at 15MHz. You should have the protoboard datasheet and the XCV1000 datasheet handy as you will reference them a lot when you constrain your I/O. You will also need a 3.3v and 2.5v power supply in addition to a download cable. I used a MultiLinx in slave-serial mode. There are jumpers on the board to specify which download mode you are using. The Virtex has 'banks' of I/O that can each run on its own supply voltage. This is set by a row of jumpers on the left side of the AFX board. The board I used already had all I/O banks jumpered to the 3.3 supply. The VccINT post powers the chip core. For an XCV1000 this is 2.5v(****check the datasheet to be sure****). You should be aware that your design must specify the I/O type to use(LVTTL, LVDS, etc) In the Virtex datasheet you will find the pinouts for the 560BGA package labeled with two alphanumeric characters(such as AR or B4). These correspond to the prototype area holes around the chip on the AFX board. *Note* that some rows and columns are entirely ground. Since my I/O usage was small(16-20 pins), I simply inserted the headers that come with the board into a row that had a lot of consecutive general I/O pins. I then just attached my logic analyzer cable to these headers. I discovered that they don't make good contact unless slightly pressed against but other than that worked fine. There may or may nor be a clock chip already on your board. The four sockets at each corner of the chip holder are for clock chips. If one is populated make sure you don't attempt to use another external clock on the same pin. Pin AL or AK I think is the lower left clock chip. You won't be able to use Webpack because the XCV1000 is larger than the V300E device, the largest Webpack supports. You will need the real ISE to program. Adam "Bhadri" <bhadrig@yahoo.com> wrote in message news:d574235a.0401061819.73186542@posting.google.com... > Hello > I am trying to use AFX BG560-100 board from > xilinx.(http://www.xilinx.com/xlnx/xebiz/board_detail.jsp?key=HW-AFX-BG560-1 00&category=) > I have XCV 1000 fgpa chips to use with the board. > I have never used this board before.I was using Dililentinc board till > this. > 1.Can anyone tell me how to start using this board for simple > applications. > 2.How to use the prototype area in the board. > 3.can i use the same ISE webpack software 5.1i to program this chips > with the board or is there any other software. > > Thanks in advance.It would be of great help. > bhadri.Article: 64534
Hi, there: I am reading the XPP290.zip for partial reconfiguration. I want to know where does ISE place the top level logic (as shown below) if all the three AREA_GROUPS don't allow boundary crossing? Best Regards, Kelvin -- ----------------------------------------------------------------- -- This will help Modular Design to recognize the clock -- It will also be pushed into IOB for better I/O performance... -- LEDs have negative logic => use an inverter! -- ----------------------------------------------------------------- OutputReg: process (Clock, Reset_pushbutton) begin if (Reset_pushbutton = '1') then LED_A_out <= '1'; -- disable LED (negative logic) LED_B_out <= '1'; LED_C_out <= '1'; LED_D_out <= '1'; elsif (Clock = '1' and Clock'event) then LED_A_out <= not LED_A_signal; -- active LOW => invert the signal! LED_B_out <= not LED_B_signal; LED_C_out <= not LED_C_signal; LED_D_out <= not LED_D_signal; end if; end process; -- ----------------------------------------------------------------- -- -- Some confusion exists when Active and Final Assembly compilations -- build the design. Internal FFs can be extracted from modules and -- pushed into IOB (Output pads specifically...). -- -- To avoid this potential problem, output registers will be created. -- -- ----------------------------------------------------------------- OutputReg2: process (Clock, Reset_lcd_driver) begin if (Reset_lcd_driver = '1') then LCD_DataBus <= (others => '0'); E <= '0'; RW <= '0'; RS <= '0'; elsif (Clock = '1' and Clock'event) then LCD_DataBus <= LCD_DataBus_lcd; E <= E_lcd; RW <= RW_lcd; RS <= RS_lcd; end if; end process;Article: 64535
Hi, there: How do I fix this problem? I am running xilperl guideconv.pl -gm leverage -par calctop.ncd calctop.ngd calctop_61.ncd It seems the xilperl uses some unix format while I am using PC. The app can't find the bm_4b_v2.nmc in my current directory. And I can't find the corresponding path in the guideconv.pl... Thanks in advance. Kelvin Release 6.1.03i - Map G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Using target part "2v40fg256-4". Removing unused or disabled logic... Running cover... Ldm_View: branch /calctop/FRAGCOVERED/calctop/BM_Address_CalcData untyped for FragLib.ltl Ldm_View: branch /calctop/FRAGCOVERED/calctop/BM_PushButton1 untyped for FragLib.ltl Ldm_View: branch /calctop/FRAGCOVERED/calctop/BM_PushButton2 untyped for FragLib.ltl Ldm_View: branch /calctop/FRAGCOVERED/calctop/BM_Sync untyped for FragLib.ltl Ldm_View: branch /calctop/FRAGCOVERED/calctop/BM_Sync_LED_Pushbutton untyped for FragLib.ltl Ldm_View: branch /calctop/FRAGCOVERED/calctop/BM_WriteEnable_LCD_Data untyped for FragLib.ltl Writing file calntop_61.ngm... Constraining slice packing based on guide NCD. Running directed packing... Running delay-based LUT packing... Running related packing... ERROR:Pack:196 - Specified macro file /home/limd/designs/partial_reconfig/Calc_pr10/Top/Assemble/bm_4b_v2.nmc does not exist. ERROR:Pack:196 - Specified macro file /home/limd/designs/partial_reconfig/Calc_pr10/Top/Assemble/bm_4b_v2.nmc does not exist. Design Summary -------------- Number of errors : 1 Number of warnings : 5 Map could not convert the NCD file.Article: 64536
PAR time is related to many factors including the complexity of your design and
aggressiveness of the timing constraints relative to the logic delays in your
design. Good floorplanning can reduce an 8 hour run to a few minutes (I've got
a fairly sparse - 25% utilized 2V6000 I am working with right now) without
placing the BRAMs, I ws getting PAR runs in the 8-10 hour range. By simply
placing the BRAMs and the output pipeline registers using floorplanning, it
reduces the par time to under 20 minutes.
"Kelvin @ SG" wrote:
> Hi, there:
>
> I am performing active-module P&R for partial reconfiguration. My fixed
> logic is 30K (ASIC) gates, and the
> variable logic modules are 0.5 & 2K gates only...Now I am P&R the variable
> modules with a blackbox
> for fixed module, how come it takes over 30 minutes but still ISE 6.1
> couldn't finish this small module.
>
> I want to know whether the P&R time is more related to my chip size OR the
> size of my FPGA(Virtex2, 6000K).
>
> Besides that, how may I derive the output file names in multi-pass P&R, e.g.
> 4_4_1.ncd from my par command
> options?
>
> Best Regards,
> Kelvin
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 64537
I think of guard bits as extra MSBs to prevent overflow. With CORDIC,
worst case you need 2 to accommodate the gain (1.65) plus rotation of the
worst case vector on (45 degree line, full scale I and Q) to a cardinal
axis, which gives a 'gain' of sqrt(2) on one axis. CORDIC also suffers
from some truncation errors at each iteration due to the right shift of
the cross components. If you simply truncate at each iteration, the worst
case error is roughly log2(iterations) bits, which tells you the number of
bits extra you should keep in the LSBs to minimize the trucation error at
the output.
I'm not aware of a multiply-accumulate or divide-accumulate directly,
however the CORDIC can be modified to do multiplication or division and
then it is a simple matter to accumulate the results with an extra adder.
I describe the multiplication and division algorithms for CORDIC in my
CORDIC paper, which I think you have probably seen.
Jeff wrote:
> Hi,
> I have learned about CORDIC from this group, especially from Ray. Now,
> I have several more questions.
> One paper described the implement structure of CORDIC algorithm. It
> uses 16 bits data width and 6 guard bits internally. What is the guard
> bits? I have borrowed several digital design books from library and
> they do not mention that. Even though I can guess guard bits are used
> for overflow prevention, it is far away from understanding the
> utilization of its application in the CORDIC algorithm.
> My another question is how to realize an MAC(multiply-and-accumulate)
> and DAC(divide-and-accumulate) using CORDIC. The paper says they can.
> Although I have read the relevant papers on the website of Ray, I have
> not got the answer. Could you shed some light on this question?
>
> Thans in advance
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 64538
Hi!
My question is long, but bare with me. I am using EDK 3.2 and trying
to get Microblaze XMK working from external memory. I have bootloader
in BRAM, which copies the context of FLASH memory to SRAM memory and
then jumps to SRAM. This context includes Xilkernel.elf and two
processes: Shell.elf (This is from test/arch/microblaze/Shell.c) and
Print.elf, which is simple "Hello World". Here is a snippet of my .MSS
file
BEGIN LIBRARY
PARAMETER LIBRARY_NAME = xilkernel
PARAMETER LIBRARY_VER = 1.00.a
PARAMETER MAX_PROCS = 2
PARAMETER CONFIG_PROCESS = true
PARAMETER CONFIG_PROCESS_EXIT = true
PARAMETER CONFIG_PROCESS_KILL = true
PARAMETER CONFIG_PROCESS_SLEEP = true
PARAMETER CONFIG_PROCESS_YIELD = true
PARAMETER THREAD_STACK_SIZE = 0x400
PARAMETER PROCESS_TABLE = ( (0x80806000, 1), (0x8080A000, 2))
PARAMETER SCHED_TYPE = 2
PARAMETER CONFIG_MUTEX = true
PARAMETER CONFIG_SEMA = true
PARAMETER CONFIG_MSGQ = true
PARAMETER CONFIG_THREAD_SUPPORT = true
PARAMETER MSGQ_TABLE = ( (10, 10), (15, 15) )
END
Bootloader works correctly and I have 3 .ELF files in SRAM memory. My
problem is how to generate the first interrupt to get the first
process scheduled. Like said in xilkernel_v1_00_a/src/src/sys/main.c
file
* @file main.c
*
* The main routine, that starts the kernel.
*
* Enables the Interrupts and starts the timer Interrupt.
* Initialises the system by calling sys_init() and loops. On first
timer
* interrupt the first process gets scheduled.
From MB_XILKERNEL part the code seems to be incomplete so I have tried
to add following lines to main.c file
#ifdef MB_XILKERNEL
/* Enable microblaze interrupts */
microblaze_enable_interrupts();
/* Start the interrupt controller */
XIntc_mMasterEnable(XPAR_MY_OPB_INTC_BASEADDR);
/* Set the number of cycles the timer counts before interrupting
*/
XTmrCtr_mSetLoadReg(XPAR_MY_OPB_TIMER_BASEADDR, 0, 100);
/* Reset the timer and clear interrupts */
XTmrCtr_mSetControlStatusReg(XPAR_MY_OPB_TIMER_BASEADDR, 0,
XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK);
/* Enable timer interrupt in the interrupt controller */
XIntc_mEnableIntr(XPAR_MY_OPB_INTC_BASEADDR,
XPAR_MY_OPB_TIMER_INTERRUPT_MASK);
/* Start the timer */
XTmrCtr_mSetControlStatusReg(XPAR_MY_OPB_TIMER_BASEADDR, 0,
XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK |
XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
#endif
I was hoping to set timer to count and give interrupt so I can get the
first interrupt. But I am stuck in here, end of main.c file, waiting
interrupt to occur.
while(1) { /* Keep looping....*/
print("Hi!\r\n") ;
}
return 0 ;
I have checked every value of these XPAR_... and XTC_... variables and
they are ok. I am guessing that I am missing Interrupt routine, like
timer_int_handler or something like that. In the same folder where
main.c is located there is also timer_intr.S file. If I have
understood correctly this should be Microblaze Xilkernel
timer_intr_handler? Why it is not working? What am I missing? Am I
trying in a wrong way to get an interrupt to occur? Should there be
line
PARAMETER INT_HANDLER = timer_intr_handler, INT_PORT = Interrupt
in my .MSS file?
Thanks,
Jari
Article: 64539I am pleased to announce that Altera has opened up its Quartus II CAD suite to university researchers. The Quartus University Interface Program, or QUIP, toolkit is designed to enable university (or other) researchers to plug new CAD tools and ideas into the Altera Quartus II CAD flow. QUIP describes Altera's devices, interfaces by which data can be sent into the Quartus II software at various points in the CAD flow, and data formats in which data can be dumped out of the Quartus II software. QUIP also includes tutorial and sample programs showing how to use the various APIs and data file formats. This toolkit enables researchers to write point CAD tools that perform one CAD optimization in a new or better way, and integrate their new CAD tool into a complete CAD flow so they can get realistic results on how this new idea improves circuit timing, routability, device utilization, compile time, or other metrics. You can augment or replace virtually any phase of the Quartus II CAD flow (e.g. all of synthesis, or logic optimization, or technology mapping, or placement, etc.) or add new phases (floorplanning, wire-type routing, physical synthesis, etc.). You can then get statistics back from the Quartus II CAD suite showing how much your new tool or algorithm improves circuit timing, routability, device utilization, or other metrics. You can quickly test new CAD ideas in an industrial strength tool flow, and avoid having to write a complete CAD suite to test your ideas. The benefit to academics is the ability to focus more on innovative CAD algorithms and tools, and less on putting together entire CAD flows to test out these new algorithms and tools. In my PhD I spent five years writing a place and route system, including timing analyzer, etc., so this would certainly have helped me graduate faster! The benefit to us at Altera is (we hope!) more FPGA CAD research, and research not just on simplified FPGA architectures and on simple benchmark circuits, but on the full range of problems presented by today's complex FPGA architectures, and the complex hardware designs going into those FPGAs. For more details on QUIP, and to download all the documents, tutorials, APIs, etc, see http://www.altera.com/education/univ/quip/quip-overview.html. Feel free to contact me, or mail quip@altera.com, or post to this newsgroup, if you have any questions. Regards, Vaughn Betz AlteraArticle: 64540
If your synthesis tool creates FFs that power up as zero, by default, then
you could try this:
process(clk)
begin
if rising_edge(clk) then
if reset_n = '0' then
reset_n <= '1';
end if;
end if;
end process;
reset <= not(reset_n);
--
Regards,
Vinh Pham
vinh-pham (a) hawaii rr com
Article: 64541Hello, I have implemented my own SDRAM controller in a Virtex II component in order to use SDRAM modules Sodimm-PC133 (133 MHz frequency). My problem is that this block seems to work very well with MICRON Sdram modules, but it is not fully stable with SMART modules. It seems to be the burst reading which causes some bit errors (not many, we have at worst 25 bit errors on 32Mb files). I think the FPGA block is OK, routing timings are correct, and I think my problem may be on SDRAM timings. I used 180° phase of my DCM to generate control signals and bring back datas, in fact I work on the falling edge of the SDRAM clock. I have tried to work on the rising edge but then results are much uncertain ! So my question is : Do you had some timing problems when controlling a Sdram ? On which edge do you work ? etracArticle: 64542
> I am performing active-module P&R for partial reconfiguration. My fixed > logic is 30K (ASIC) gates, and the > variable logic modules are 0.5 & 2K gates only...Now I am P&R the variable > modules with a blackbox > for fixed module, how come it takes over 30 minutes but still ISE 6.1 > couldn't finish this small module. It sounds like you have very aggressive timing specs. How fast are you clocking your FPGA? There should be a *.par report file that gives you some details about your design. Does it show your design having many levels of logic? I've never done ASIC design, but perhaps you folks don't use flip-flops a lot. FFs are "free" in FPGAs so we tend to stick as many of them into our datapaths as we can. I habitually stick in FFs after only a couple levels of logic, if I can afford the latency. Sometimes I'll throw in one right after a single AND gate because it's "free". > I want to know whether the P&R time is more related to my chip size OR the > size of my FPGA(Virtex2, 6000K). By "chip size" do you mean "design size"? I don't think the capacity of your FPGA makes a difference, unless your design is close to 100% utilization, then the tools have less room to work, on top of more routing congestion. Having too much space might also be a problem if the tools place your logic far apart just because they can. If you see it doing that (by looking with Floorplanner) you might want to set an area constraint to force your logic into a reasonable area.. The speed grade (e.g. -6,-7,...) of your FPGA might be more of an issue than size. Regards, Vinh Pham vinh-pham (a) hawaii rr comArticle: 64543
"Bruce Warkentin" <bruce@nnosspam..rtds.com> wrote: > I'm looking for VHDL floating point code to do 32-bit > adds and multiplies to work with the ppc405 core. > I've found a couple out there ... You can try the FPHDL libraries (http://www.eda.org/fphdl/). What are the floating point libraries you have found?Article: 64544
Bhadri wrote: > Hello > can anyone say me what is the difference between virtex and spartan > fgpa chips. > It is just the number of gates in them, voltage levels or anything > more than that. > I have used spartan chips.i configured the chip with different vhdl > files again and again on the same chip.But somebody said it is not > possible in the xcv1000 virtex chips.(dynamically reconfigurable).Is > it true.Then,y are they called FPGA's. Bhadri, did you have a short look at the data sheet of both series? They should answer your question. As for your last question, I would say you have been told something wrong from somebody. Regards, MarioArticle: 64545
Adam wrote: > I am working on a design involving 2 4028EX devices along with an > external > SRAM bank. Is there a way I can simulate both post-synthesis netlists > together? I'm trying to find a way where I can model the memory and chip > interconnects and then simulate the whole system. The devices are on a > PCI card which is one if the reasons just using a larger chip isn't an > option. Thanks Of course you can do this. Generate post-synthesis (back-annotated) VHDL-Files and put them into a single structural VHDL design that connects them appropriately. In addition, you might need to model other things such as the memories and some PCI stub in your case. You would integrate this either directly into your top-level structural design or (better) create separate modules. Regards, MarioArticle: 64546
Dear Peter, You wrote: > Years ago, I defined a tracking factor: If any parameter is actually > at its max value (it cannot be any longer), then all other timing > parameters are between 70% and 100% of their guaranteed max values. > But if the chip is inherently fast, and is cold, and has high Vcc, > then all delays will be short, but the above relationship still holds: > They all track with a max 30% error between them. And also: > Timing analysis is easy when you just have to add values. The > worst-case max is the sum of the worst-case maxes. > Trouble starts when you must subtract. Then the worst-case total max > must use the min value of the subtracted parameter. > That's where the tracking rules come in. One last question if I may, just to be sure I understood correctly. I have the impression that the timing analyzer from Xilinx does _not_ use this 70% tracking factor. In other words even when it needs to subtract (e.g. for setup and hold times) it will always use the nominal values as specified in the data sheets to derive all timings: For example in order to derive Tsu the equation is: Tsu = Tin + Tlogi + Tsui - Tgck As you say above in the worst case Tsu would need to be calculated using Tgck_min, but since that's not available one would need to either assume 0 ns or use the 70% rule you mentioned. However I believe that the timing report generated by the Xilinx tools ignores this and happily uses the nominal Tgck value. Can you confirm this? Also in the datasheet, the "AC Electrical Characteristics" (aka external timing parameters, derived from the internal parameters using the procedures outlined in white paper 122 from Xilinx) seem to ignore both this 70% rule and the more conservative "0 ns min" approach... Thanks for your time, G.Article: 64547
Hi, Are there any difference between "CORE" and "IP"? (thinking terminology) Thanks for you advice Laurent www.amontec.com ------------ And now a word from our sponsor ------------------ For a quality usenet news server, try DNEWS, easy to install, fast, efficient and reliable. For home servers or carrier class installations with millions of users it will allow you to grow! ---- See http://netwinsite.com/sponsor/sponsor_dnews.htm ----Article: 64548
"etrac" <etraq@yahoo.fr> wrote in message news:c99b95c7.0401070133.38f7e294@posting.google.com... > I have implemented my own SDRAM controller in a Virtex II component in > order to use SDRAM modules Sodimm-PC133 (133 MHz frequency). > > My problem is that this block seems to work very well with MICRON > Sdram modules, but it is not fully stable with SMART modules. It's quite common to find that top-rank manufacturers test and grade their devices more conservatively. > I think the FPGA block is OK, routing timings are correct, and I think > my problem may be on SDRAM timings. Obviously you have the SDRAM data sheet, and you use that timing to determine timing required at the FPGA pins. Are you using worst-case values from the data sheet? > I used 180° phase of my DCM to > generate control signals and bring back datas, in fact I work on the > falling edge of the SDRAM clock. I have tried to work on the rising > edge but then results are much uncertain ! Don't forget that every pin into and out of the FPGA, *including the clock*, suffers pad delays - have you checked all the pad timings? Often they are the slowest part of an FPGA design. Have you correctly accounted for the delay between external clock and internal FPGA clock? That delay doesn't matter when deciding how the FPGA operates internally, but of course it will affect any external timing that's relative to the clock. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 64549
Hi,
I have two clock domains in my Verilog design (Spartan2), 33 MHz and 20 MHz.
My problem: data transport between domains create deadlock.
(When I use the same clock in all domains, this send/receive primitive
works fine, but I need different clocks...)
Can somebody help me? URL, FAQ, RTFM? :)
Thanks,
BB
// send @ 33 MHz
data_reg = 4;
data_ready <= data_ready ^ 1;
// receive @ 20 MHz
case (state)
0: if (data_ready != last_data_ready)
begin
last_data_ready = last_data_ready ^ 1;
state <= 1;
end
1: // READ data_reg
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