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Davide Canina wrote: > Dear all, > I would like to know if it's possible to create an interface from Virtex > II-FPGA's to serial RS485 or RS232,please ? > Do you have some > application notes or technical issues for this problem,please? > Thank > you very much for your help. > Best regards, If you want to attach RS485 or RS232 lines directly to the FPGA I would not do this. And, as Valentin said, you get some voltage level problems. Normally, one uses special RS232 or RS485 transceivers that are driven by standard levels. As for the logical part, you need to implement some standard UART functionality in your FPGA. If you don't know how to do that, have a look at the link Martin gave you, or check out www.opencores.org. Regards, MarioArticle: 63726
Hi all, Is that possible to put the busy signal (when the FPGA is configuring) in a float state. I coupled an ARM7 and a SPARTAN-II, and busy signal of the FPGA is directly connected to a data_line of the ARM. As we are doing FPGA configuration over ethernet, busy line corrupt the ARM when it try to configure the FPGA. There are two solutions: -- change the schemetic -- to be able to put busy line in a float state as an other IO line when FPGA is programming : Are there any option in ISE to do that? Laurent www.amontec.comArticle: 63727
Hi Praveen, Brendan Cullen wrote: > Hi Praveen, > > Are you asking what power, given room temperature operation, would send the junction temperature > to over 85 degrees Celsius ? > > Brendan > > praveen wrote: > > > John Blaine <john.blaine@xilinx.com> wrote in message news:<3F9FA363.7930A312@xilinx.com>... > > > Praveen, > > > > > > It is difficult to estimate how much impact this will have on the power > > > estimate. > > > So let me take you through a few points: > > > > > > Using a post PAR estimate will allow XPower to have an accurate estimate > > > of > > > capacitance load on the internal routes so no problem here. If you are > > > using post MAP > > > where no SDF is generated then this is a large source of inaccuracy and > > > is not > > > recommended. > > > > > > Now lets look at the timing simulations tend to result in glitches. This > > > switching translates > > > into higher activity rates in XPower-> higher power. > > > > > > I would expect these to be fairly low load signals. Also if you have a > > > fully synchronous > > > design this effect will be limited. > > > > > > Your clocks will be set correctly (high power consuming nets). > > > If you have met timing (verifed through timing analyser) then other > > > heavy loaded signals like > > > clock enables, should be set correctly. > > > > > > So in summary, if your design is post PAR, fully synchronous and has met > > > timing, you should > > > be OK an get an accurate power estimate. > > > > > > John > > > > > > praveen wrote: > > > > > > > hi all, > > > > > > > > i am calculating the power consumption using xilinx xpower. For > > > > generating the VCD file i am not loading the SDF(Standard Delay > > > > Format) during VSIM. Will it affect the power calculation. > > > > > > > > thanks in advance. > > > > > > -- > > > > hi john, > > > > as u said our design is fully synchronous and our entire design is > > working on only one clock edge, and more over ther are no latches > > inferred in our design , so chances of glitches are minimal. Having a synchronous design does not mean that a node will change only once per clock cycle. All it means is that all nodes need to be stable before the next clock cycle. In other words, the nodes in between two registers in a fully synchronous data path may change from 1 to 0 and back to 1 again several times within a clock cycle and that is OK as long as it is stable before the next clock cycle arrives. The reason it may oscillate like that is the inputs to the logic functions will arrive at different times depending on the component and routing delays and depending on the logic functions and the input values any node may change several times in between clock cycles. The reason this is important to know is the way to calculate dynamic power depends on how often each node changes value (Dynamic Power = Capacitance * Voltage^2 Frequency the node changes). If you do a non-timing simulation and do not account for delays in the design, these "glitches" for lack of a better word will not be simulated and thus not given to XPower and thus will not get as accurate of an estimation for power since the frequency part of the equation will not be accurate. There is even more to it than that. Within the SDF file are parameters called PATHPULSE which define which glitches get propogated and which ones will get absorbed by the capacitance within the chip. This will get rid of some glitches that will likely not get realized in the silicon simply because they are too short to overcome the node capacitance. Without an SDF file, it is possible that some transitions within the non-timing simulation would not happen and for timing simulation, some of the "glithes" will happen and some will not. This parameter is the one that gates that behavior and thus can effect the number of tranitions at a node and thus the dynamic power at that node. > > so not loading the SDF file will not make much differnce in th power > > estimate i guess. It very likely can. I would highly recommend doing power estimations with SDF only as it is much more likely to accurately predict power than not using one. > > one more thing i wanted to ask u regarding the power consumption, we r > > using XILINX virtex 2p (XC2VP50 -6 FF1517) . what is the power that is > > tolerable without providing heat sinks. As long as the junction temperature is below 85 degrees for comercial devices, then you are OK. The junction temperature is dependent on the amount of power dissipated as well as the ambient temperature, airflow, and heat dissipation of the device (through the package, heatsink, and the board itself). Once it gets above that, you need to cool the device and a heatsink is one way to do that. XPower allows you to enter information like ambient temperature and airflow so that it can calculate the junction temperature based on those parameters as well as the power dissipated. As long as that is below 85 degrees (with some margin) then you should be OK without a heatsink. If not, you need to either look into a heatsink or possibly change other environmental factors to get the device within specification. BrendanArticle: 63728
Delay the control signal for some nano seconds "Vazquez" <andres.vazquez@gmx.de> schrieb im Newsbeitrag news:eee19a7a.0312010549.27b93f6c@posting.google.com... > Dear Sir or Madame, > > I have a question concerning the inputs of a VHDL module when > simulating with the Altera QuartusII Waveform Editor. > The input CONTROL shall be a registered signal from a different > module. > When doing a functional simulation I edit the waveform in that form you > can see so that CONTROL changes its value right with rising edge of > CLK. So I want to reproduce the registered input signal CONTROL. > But when starting the functional simulation I get the error message: > "Found clock-sensitive change during active clock edge ...", of course. > My question: How can I reproduce the clock synchronous input CONTROL without > violating setup-time? (using the Waveform Editor !!!) > > Thank you for your help. > > Andre V. > G&D System Development > > > -------- -------- -------- > | | | | | | > | | | | | | CLK > | |___________| |___________| |___________ > > > ------------------------------------------- > | > | CONTROL > _____________________|Article: 63729
Hello folks, I am getting this intermittent error when running ngdbuild from the command line: // START error Release 5.2.03i - ngdbuild F.31 Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -quiet -dd ./_ngo -uc test_design.ucf -p xc2v3000-fg676-5 test_design.edf test_design.ngd Launcher: Executing edif2ngd -quiet "test_design.edf" "_ngo\test_design.ngo" ERROR:NgdBuild:527 - Failed to launch program edif2ngd: The pipe has been ended. ERROR:NgdBuild:28 - Top-level input design file "test_design.edf" cannot be found or created. Please make sure the source file exists and is of a recognized netlist format (e.g., ngo, ngc, edif, edn, or edf). Writing NGDBUILD log file "test_design.bld"... // END error This happens when using edifs from coregen and synplify pro - the edifs are present. If I rerun it with the same input edif, the error doesn't happen! So, it is some transient condition that is causing this. Xilinx answer 16491 is the only one that talks about error 527 and it only mentions invalid chars/spaces in the edif path as being the problem but this is not the case. It does not mention "the pipe has been ended". Nothing in the archives/web either. Anyone encountered this before or have any suggestions please? Thanks for your time. Ken -- To reply by email, please remove the _MENOWANTSPAM from my email address.Article: 63730
Dear Sir or Madam, when tyring a complex FGPA design on real hardware what possibilities do exist to analyse the design ? Of course one possibility are debug pins but the problem is that their availableness is not always given. Simulation might be a good first step in order to prove first correct functionality but what if there are some components which cannot be reproduced my models so easily? Are their any tools (for Altera Cyclone FPGA) which allow to observe the diffent signals live (not simulation!) without having to route them to output pins (which are of limited number anyway, apart from that the timimg may be changed in an unmeant way) ? Thank you for your information and help. Best regards AndreArticle: 63731
"ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0312020511.4194c798@posting.google.com... > Dear Sir or Madam, > > when tyring a complex FGPA design on real hardware > what possibilities do exist to analyse the design ? > Of course one possibility are debug pins but the problem > is that their availableness is not always given. > > Simulation might be a good first step in order to prove > first correct functionality but what if there are > some components which cannot be reproduced my models so > easily? > Are their any tools (for Altera Cyclone FPGA) which allow > to observe the diffent signals live (not simulation!) without having > to route them to output pins (which are of limited number anyway, > apart from that > the timimg may be changed in an unmeant way) ? > > Thank you for your information and help. > > Best regards > > Andre So, you have an FPGA on a board and you want to know the value of signals within that FPGA, but you don't want to use any external pins? Hmmm. Two sensible choices - SignalTap - Not used it, but at a guess it uses internal RAM to store signals, then communicate them via JTAG back to the host PC. VITAL, or Gate Level simulation. OK, its simulation, but (in theory) it is the Place and Route tool's view of what it has just placed and routed, complete with ps accurate delays. You should do a gate level sim anyway, just in case your design has been broken by one of the tools along the way. -- Ian Poole, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: ian.poole@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 63732
Altera provides the SignalTap II tool to allow monitoring live signals inside the FPGA. This solution uses the internal RAM. Details of how this tool can be used are provided in http://www.altera.com/literature/an/an280.pdf Hope this helps. - Subroto Datta Altera Corp. "ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0312020511.4194c798@posting.google.com... > Dear Sir or Madam, > > when tyring a complex FGPA design on real hardware > what possibilities do exist to analyse the design ? > Of course one possibility are debug pins but the problem > is that their availableness is not always given. > > Simulation might be a good first step in order to prove > first correct functionality but what if there are > some components which cannot be reproduced my models so > easily? > Are their any tools (for Altera Cyclone FPGA) which allow > to observe the diffent signals live (not simulation!) without having > to route them to output pins (which are of limited number anyway, > apart from that > the timimg may be changed in an unmeant way) ? > > Thank you for your information and help. > > Best regards > > AndreArticle: 63733
P L E A S E somebody help. I have a design of mixed .gdf and .vhd
files that
were created in MaxPlusII, which I have imported it into Quartus II
v3.0 SP2.
What I am trying to do is to convert the complete design into VHDL
ONLY
The reason for doing this is so that i can do a functional simulation
of my design prior to synthesising it - synthesis currently takes 4
hours ! !
The problems I am having with Quartus are :-
- currently, the way i am creating a VHDL ONLY representation of
my design
(without synth'ing) is by 'create HDL design file for current
file' on every block diagram i have. with quite a few block
diags this is getting VERY
ANNOYING, slow and highly prone to error. does anybody know how to
do it better ?
- generics dont work properly. declaring a parameter that defines
the
generic works fine...so long as you dont want the generics to be
inhereted
from the hierarchical level above - this is where the problems
arrise. if
i want the generic to be inhereted then i have to leave the
'value' box for
the parameter empty, however this causes the generic clause to be
empty
when i then create a HDL design file of my block diagram.
Article: 63734The NIOS processor runs on a 33.333MHz clock. How can I increase the speed of the clock and what is the maximum speed which can be achieved? Please advice.Article: 63735
Larry, I disagree. Metastability delay is statistically unbounded (although less than 3 ns in all but perverse cases). But you should not throw this in willy-nilly. Whenever you have a truly asynchronous interface, you should be aware of it. If many or most of your timings are prone to metastability, there is something wrong with the design approach... Peter Alfke ==================== Larry Doolittle wrote: > Don't forget metastability slack. In theory it does not apply to the > purely synchronous nets; in practice I don't want to go through the > work of separating them out, and it's a good excuse to add one more > conservative assumption. > > - LarryArticle: 63736
Temperature, Vcc, and process variations are already (and have always been) covered by the worst-case assumptions behind the Xilinx timing analyzer numbers. Peter Alfke ====================== glen herrmannsfeldt wrote: > > > How about temperature or Vcc variation? > > Or process variations in the chips? A newer chip batch, done on a > different process, may be faster than an older one. > > If the timing constraints already include such margins, you don't need > to add additional margins. > > -- glenArticle: 63737
Hi there, Has anyone managed to get Triscend's FastChip software working with visionClick 7.6 under Windows XP? I've used the tools previously under Windows 2000 (a year or so ago) but have been forced to use a new machine with Windows XP installed, and I can't get things to work. I have an A7 Evalution Board, and I'm confident that it works, as setting it up in visionClick I can communicate with the board and the parallel port tester works fine too. I tried FastChip 2.6, but the download manager software there said it couldn't connect to the board. Thus I regressed to 2.1.2, which is what I had working previously and have the CDs for, and the FastChip Download Manager software there doesn't download to the board, just sitting there at 0%. More curious is that it doesn't complain it can't find the board, which is what it is meant to do it things are ill. I've gone through the instructions several times, and I can't see what I'm doing wrong. I dare say it's something daft on my behalf, but I thought I'd see of anyone else has had similar problems. -- Dr Michael Dales -- email: michael@dcs.gla.ac.uk -- tel: +44 141 330 6297 Department of Computing Science, University of Glasgow, Glasgow, G12 8QQ.Article: 63738
In article <bqhbgp$22qvbe$1@ID-212988.news.uni-berlin.de>, Robert Sefton wrote:
> "Larry Doolittle" <ldoolitt@recycle.lbl.gov> wrote in message
>>
>> Don't forget metastability slack. In theory it does not apply to the
>> purely synchronous nets; in practice I don't want to go through the
>> work of separating them out, and it's a good excuse to add one more
>> conservative assumption.
>
> What is metastability slack and how do you apply it? Do you mean you
> over-constrain your clock periods slightly to expand setup margins?
Yes and no. Yes, I over-constrain my clock slightly (Peter Alfke's
nominal number for modern chips and "typical" applications is 3 ns).
The interpretation is to allow time after the clock edge for each
flip-flop (that has an asynchronous input) to "choose" which state
to land in.
In a private e-mail to me, Peter Alfke both complained that this
approach is flawed (because the metastability delay is statistically
unbounded, and of course he's right) and gave me the 3 ns number above
(conservative for "all but perverse cases"). He's right, most nets
don't need this. But if _some_ do (and I have two clock domains in
my designs, that I cross carefully and minimally, but I can't get
away with 'never'), then it's simply easier for me to set a global
conservatism than to (in some error-prone way) root out the clock
domain crossing flip-flops and change the timing spec on their output
nets. Hey, my designs "make timing" and work in the field, so it
can't be all bad.
An alternative approach (I have seen other people do this) is to put
two stages of flip-flops on all clock-domain crossings, and _assume_
there is a ton of slack between them.
- Larry
Article: 63739JohhnyNorthener wrote: > P L E A S E somebody help. I have a design of mixed .gdf and .vhd > files that > were created in MaxPlusII, which I have imported it into Quartus II > v3.0 SP2. > > What I am trying to do is to convert the complete design into VHDL > ONLY > > The reason for doing this is so that i can do a functional simulation > of my design prior to synthesising it - synthesis currently takes 4 > hours ! ! Sounds like a good reason to write some code. The fixed-pc license includes modelsim, which should handle this job for you. > - currently, the way i am creating a VHDL ONLY representation of > my design > (without synth'ing) is by 'create HDL design file for current > file' on every block diagram i have. Consider using the block diagrams only as a guide to write your own vhdl synth code. Do a bit at a time using a modelsim compile to check syntax. Write a simple testbench before attempting synthesis. If rewriting the synth code is too much trouble, consider writing a modelsim testbench only for your existing .vho netlist. -- Mike TreselerArticle: 63740
When you implement double synchronizers, make sure that the two flip-flops are closely spaced ( e.g. in the same slice ) with minimal routing delay between them. Overconstrain this delay between them ( enforce a few ns ) so that you do not squander the time available for metastable resolution. Remember: The software takes your constraint requests literally. Once they are met, the software does nothing to make it any better ( why should it? ), the way a good engineer might naturally be inclined to do it... It's just a computer! Peter Alfke ====================== Larry Doolittle wrote: > An alternative approach (I have seen other people do this) is to put > two stages of flip-flops on all clock-domain crossings, and _assume_ > there is a ton of slack between them. > > - LarryArticle: 63741
Larry Doolittle wrote: (snip) > Yes and no. Yes, I over-constrain my clock slightly (Peter Alfke's > nominal number for modern chips and "typical" applications is 3 ns). > The interpretation is to allow time after the clock edge for each > flip-flop (that has an asynchronous input) to "choose" which state > to land in. The original question didn't ask about metastability at all. It seemed to me that he was trying to exactly predict the timing margins required to make the design work. > In a private e-mail to me, Peter Alfke both complained that this > approach is flawed (because the metastability delay is statistically > unbounded, and of course he's right) and gave me the 3 ns number above > (conservative for "all but perverse cases"). (snip) > An alternative approach (I have seen other people do this) is to put > two stages of flip-flops on all clock-domain crossings, and _assume_ > there is a ton of slack between them. Well, you have a whole clock cycle of slack between them. Because of the exponential, that is usually good enough. If you are close to where it isn't, synchronous parts of the design will have metastability problems, too! If your design will not fail in 1e100 years, is that good enough? OK, today is tuesday, what day of the week will it be in 1e100 days? Only ordinary calculators need to be used in figuring this out. -- glenArticle: 63742
When i try to add signals to the Wave window Modelsim freeks out creating a corrut call stack error. WHY? and any ideas on how to fix that? BTW i'm running Windows XP.. -- Använder M2, Operas banbrytande e-postklient: http://www.opera.com/m2/Article: 63743
In article <slrnbspm40.akj.ldoolitt@recycle.lbl.gov>, ldoolitt@recycle.lbl.gov says... > In article <bqhbgp$22qvbe$1@ID-212988.news.uni-berlin.de>, Robert Sefton wrote: > > "Larry Doolittle" <ldoolitt@recycle.lbl.gov> wrote in message > >> > >> Don't forget metastability slack. In theory it does not apply to the > >> purely synchronous nets; in practice I don't want to go through the > >> work of separating them out, and it's a good excuse to add one more > >> conservative assumption. > > > > What is metastability slack and how do you apply it? Do you mean you > > over-constrain your clock periods slightly to expand setup margins? > > Yes and no. Yes, I over-constrain my clock slightly (Peter Alfke's > nominal number for modern chips and "typical" applications is 3 ns). > The interpretation is to allow time after the clock edge for each > flip-flop (that has an asynchronous input) to "choose" which state > to land in. Larry, your clocks must be pretty slow if you can afford to add 3 ns to every path in the design instead of just the few async boundary paths. I would call that majorly, not slightly, over-constraining the design. -- Rich IachettaArticle: 63744
On Tue, 2 Dec 2003 16:07:51 -0600, Richard Iachetta <no@virus.com> wrote: >In article <slrnbspm40.akj.ldoolitt@recycle.lbl.gov>, ldoolitt@recycle.lbl.gov >says... >> In article <bqhbgp$22qvbe$1@ID-212988.news.uni-berlin.de>, Robert Sefton wrote: >> > "Larry Doolittle" <ldoolitt@recycle.lbl.gov> wrote in message >> >> >> >> Don't forget metastability slack. In theory it does not apply to the >> >> purely synchronous nets; in practice I don't want to go through the >> >> work of separating them out, and it's a good excuse to add one more >> >> conservative assumption. >> > >> > What is metastability slack and how do you apply it? Do you mean you >> > over-constrain your clock periods slightly to expand setup margins? >> >> Yes and no. Yes, I over-constrain my clock slightly (Peter Alfke's >> nominal number for modern chips and "typical" applications is 3 ns). >> The interpretation is to allow time after the clock edge for each >> flip-flop (that has an asynchronous input) to "choose" which state >> to land in. > >Larry, your clocks must be pretty slow if you can afford to add 3 ns to every >path in the design instead of just the few async boundary paths. I would call >that majorly, not slightly, over-constraining the design. Yes. I have some 1.6ns clocks in my current design. It would be a bit hard to make the constraint 3ns tighter. Moral: avoid cookbook solutions. Regards, Allan.Article: 63745
>Remember: The software takes your constraint requests literally. Once >they are met, the software does nothing to make it any better ( why >should it? ), the way a good engineer might naturally be inclined to do it... >It's just a computer! Perhaps the software should have a "metastability" tag for signals between FFs that should be placed right next to each other. Then the timing analysis could tell you the slack which is what you really want to know. There are probably other good things smart software could do with that info. Or maybe that's a wild goose chase. Maybe you don't want them right next to eachother and the clock is slow enough so it doesn't matter... -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 63746
>Temperature, Vcc, and process variations are already (and have always >been) covered by the worst-case assumptions behind the Xilinx timing >analyzer numbers. But they don't know anything about the input clock jitter. In the old days, we mostly ignored clock jitter. Or rather build clock distribution systems with low enough jitter that it was reasonable to ignore it. I think part of the round-down that people are doing today is to cover the clock jitter that they haven't thought about much. It's interesting/important at todays higher speeds. Quick. How much jitter on the clock going into your PCI card? (Is that even covered in the specs?) Don't forget Ray's stories of SSO adding to the jitter. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 63747
In article <29bqsvcjgj4lrivf4jfet6rdlalpjknbqd@4ax.com>, Allan Herriman wrote:
> On Tue, 2 Dec 2003 16:07:51 -0600, Richard Iachetta <no@virus.com>
> wrote:
>>
>>Larry, your clocks must be pretty slow if you can afford to add 3 ns to every
>>path in the design instead of just the few async boundary paths. I would
>>call that majorly, not slightly, over-constraining the design.
>
> Yes. I have some 1.6ns clocks in my current design. It would be a
> bit hard to make the constraint 3ns tighter.
"Everything is relative". My current design needs to make 25 ns in
a XC2Sxxx-5. I can afford to pad that by a few ns.
> Moral: avoid cookbook solutions.
It's worth knowing about cookbook solutions, using them properly when
they apply, _and_ understanding how to go beyond them when necessary.
- Larry
Article: 63748As Subroto suggests, SignalTap II best matches what you're asking for, in that it does not require debug pins. Something else that may be of interest is SignalProbe. It lets you bring signals to unused output pins for debugging, without changing the placement & routing (and hence timing) of the rest of your design. So it does require debug pins, but it avoids the chaning timing issues you're worried about. Vaughn > Altera provides the SignalTap II tool to allow monitoring live signals > inside the FPGA. This solution uses the internal RAM. Details of how this > tool can be used are provided in > http://www.altera.com/literature/an/an280.pdf > > Hope this helps. > > - Subroto Datta > Altera Corp. > > > "ALuPin" <ALuPin@web.de> wrote in message > news:b8a9a7b0.0312020511.4194c798@posting.google.com... > > Dear Sir or Madam, > > > > when tyring a complex FGPA design on real hardware > > what possibilities do exist to analyse the design ? > > Of course one possibility are debug pins but the problem > > is that their availableness is not always given. > > > > Simulation might be a good first step in order to prove > > first correct functionality but what if there are > > some components which cannot be reproduced my models so > > easily? > > Are their any tools (for Altera Cyclone FPGA) which allow > > to observe the diffent signals live (not simulation!) without having > > to route them to output pins (which are of limited number anyway, > > apart from that > > the timimg may be changed in an unmeant way) ? > > > > Thank you for your information and help. > > > > Best regards > > > > AndreArticle: 63749
Larry Doolittle wrote: > In article <3FCC13DB.8F643B8F@attbi.com>, Phil Hays wrote: > > I try to enter the constraints that exactly match the timing that the > > design will need to function, including board delay, loading delay, > > clock jitter and clock skew. > > Don't forget metastability slack. In theory it does not apply to the > purely synchronous nets; in practice I don't want to go through the > work of separating them out, and it's a good excuse to add one more > conservative assumption. Yes. When crossing clock domains, make a time group of the synchronizing flipflops and make a FROM TO style constraint for just those flipflops. While my current designs are slow by my standards (125 MHz fastest clock in a Virtex 2), I can't afford to reduce the periods by 3 ns, as that is a large fraction of an 8 ns period! -- Phil Hays
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