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Messages from 63850

Article: 63850
Subject: Re: XILINX FPGA: DCM locked Signal
From: Tullio Grassi <tgrassi@cut_here.mail.cern.ch>
Date: Fri, 5 Dec 2003 20:47:24 +0100
Links: << >>  << T >>  << A >>
So is possible the situation desscribed below ?

- the DCM is locked on an input clock; 
- I stop completly the clock (from outside the FPGA),
- the DLL looses lock, but the LOCKED signal is
never updated and remain high

I think I observed something like that.
If it is correct, it's a disturbing feature.

Tullio


On Fri, 5 Dec 2003, Austin Lesea wrote:

> Muthu,
> 
> It is generated on the rising edge of CLKIN -- synchronous.
> 
> Austin
> 
> Muthu wrote:
> > Is the locked signal of DCM, is synchronous / Asynchronous ?


Article: 63851
Subject: Re: XILINX FPGA: DCM locked Signal
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 05 Dec 2003 13:32:28 -0800
Links: << >>  << T >>  << A >>
Tullio,

That is what the status bit "CLK_IN_STOPPED" is for.

Austin

Tullio Grassi wrote:
> So is possible the situation desscribed below ?
> 
> - the DCM is locked on an input clock; 
> - I stop completly the clock (from outside the FPGA),
> - the DLL looses lock, but the LOCKED signal is
> never updated and remain high
> 
> I think I observed something like that.
> If it is correct, it's a disturbing feature.
> 
> Tullio
> 
> 
> On Fri, 5 Dec 2003, Austin Lesea wrote:
> 
> 
>>Muthu,
>>
>>It is generated on the rising edge of CLKIN -- synchronous.
>>
>>Austin
>>
>>Muthu wrote:
>>
>>>Is the locked signal of DCM, is synchronous / Asynchronous ?
> 
> 


Article: 63852
Subject: Xilinx 5.2 and EDK 3.2: Simulation given 'Z' ouput form tutorial design
From: mnownby21@tntech.edu (Matt)
Date: 5 Dec 2003 14:53:15 -0800
Links: << >>  << T >>  << A >>
I need help....I installed Xilinx 5.2 SP3, EDK 3.2 SP2 and ModelSim
5.7b. After running through the compxlib and vmap to setup the
libraries for Modelsim, I went through the Microblaze tutorial. I
completed the tutorial up to downloading the design to hardware. I
skip over to the simulation section and recompiled the microblaze with
the simulation.c code. When I run the behavioral simulation, the
output from the microblaze is Z's. WHat am I doing wrong???

Confused,
Matt

Article: 63853
Subject: Re: Dual-port and single-port BlockRAM instantiation
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 05 Dec 2003 15:01:55 -0800
Links: << >>  << T >>  << A >>
There is a nifty trick:
If you need several single-port memories of up to 8Kbit size each, then
you can put two of them into one dual-port RAM, if you make sure that
the two ports never address the same RAM space (Make one port's MSB
High, the other one's MSB Low.
If you think about it, you can of course take any other address bit
position and drive it permanently High for one port, Low for the other.
And you can even divide the RAM in a not-50-50 manner, but that requires
slightly more complex addressing control.

Peter Alfke
============
John_H wrote:
> 
> Your tools may combine two single port memories into one dual-port if the
> memory sizes are compatible.  By instantiating the dual-port, you no longer
> have the option of the combination.  The tool flow you use may not take
> advantage of this packing anyway, so the point might be moot.
> 
> Check what your BlockRAM usage is - see if the tools are already
> implementing two single-port memories in a dual-port.  As long as the total
> number of BlockRAMs you infer and instatiate fit within the available number
> of BlockRAMs for the device, you're set.
> 
> "arkaitz" <arkagaz@yahoo.com> wrote in message
> news:c1408b8c.0312050623.52b9b1fa@posting.google.com...
> > Hi all,
> >
> > I am working with a 1 million gate Virtex II FPGA. I am instantiating
> > large amounts of Block RAMs in my design and even though I am using
> > Single-Port ones, I would like to know if there would be a trouble to
> > instantiate them as Dual-Port ones. I mean, would it need twice the Block
> RAMs
> > I am using now, or would it just configure them as Dual-Port?
> >
> > Thanks,
> >
> > Arkaitz.

Article: 63854
Subject: Block RAM simulation VII
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Fri, 05 Dec 2003 23:25:50 GMT
Links: << >>  << T >>  << A >>
Page 155, XST User guide:

"XST does not support block RAM initialization in Verilog."

Why not?

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



Article: 63855
Subject: Re: Floorplanning techniques
From: richieb@rediffmail.com (richie singh)
Date: 5 Dec 2003 15:45:06 -0800
Links: << >>  << T >>  << A >>
richieb@rediffmail.com (richie singh) wrote in message news:<a0238c18.0312041811.56cc43d9@posting.google.com>...
> Hi, 
> I recently started working with FPGAs and am would like to learn about
> floorplanning techniques. Could someone point me to documents or
> design guides dealing with what issues should be kept in mind while
> floorplanning a complex design..
> Thanks to all who reply!!
> R.B.

Muthu,
Thanks for your reply. I am interested in floorplanning because there
can be a scenario where the tool will not be able to meet timing and
manual effort will be involved in floorplanning. In such a case what
type of issues need to be kept in mind. Thanks!!
R.B

Article: 63856
Subject: Re: Xilinx 5.2 and EDK 3.2: Simulation given 'Z' ouput form tutorial
From: Ryan Laity <ryan_dot_laity@x-i-l-i-n-x_pleasenospam_dot_com>
Date: Fri, 05 Dec 2003 17:01:18 -0700
Links: << >>  << T >>  << A >>
Matt,

It sounds to me like you haven't compiled the EDK behavioral model 
libraries.  If that's the case then check out the "Behavioral Model 
Libraries" section on page 5 of the "Getting Started with the EDK" 
document ($EDK/doc/edk_getstarted.pdf) for the instructions.

Best regards,
Ryan Laity
Xilinx Applications

Matt wrote:
> I need help....I installed Xilinx 5.2 SP3, EDK 3.2 SP2 and ModelSim
> 5.7b. After running through the compxlib and vmap to setup the
> libraries for Modelsim, I went through the Microblaze tutorial. I
> completed the tutorial up to downloading the design to hardware. I
> skip over to the simulation section and recompiled the microblaze with
> the simulation.c code. When I run the behavioral simulation, the
> output from the microblaze is Z's. WHat am I doing wrong???
> 
> Confused,
> Matt


Article: 63857
Subject: Re: Synchronization between CPU-clock and FPGA clock.
From: "Vinh Pham" <a@a.a>
Date: Sat, 06 Dec 2003 01:13:41 GMT
Links: << >>  << T >>  << A >>
Google's a great tool for digging up information, and it can be used to
search news groups exclusively.

Go to groups.google.com (instead of www.google.com) and punch in:

crossing clock boundaries group:comp.arch.fpga

It'll bring up past conversations where people have already rehashed this
same issue.  You'll get the information you need much faster that way.  But
here's one possible solution:


The key thing to synchronizing is making sure the data doesn't change during
the clock edge where it's being paid attention to (i.e. you want to
guarantee that you don't have a hold/setup-time violation).

Yeah the easiest thing to do is to avoid the problem by using the CPU clock
(or perhaps more accurately the CPU bus clock), unless it happens to be too
slow for your FPGA to achieve the performance you need.  But if your
algorithm can be executed in parallel, you can increase performance without
increasing your clock speed.  Or you could use the clock doubling feature of
the DLLs, which should maintain a constant relationship between the clock
edges, though I have no experience with this.

If for some reason you can't have the same clock, then having your FPGA
clock be faster than the CPU clock will make things easier.  One straight
forward method is for the CPU to write it's data to one register.  Then
write a 0 and then a 1 to another register.  The output of this single bit
register is sent serially through two flip flops that are clocked on the
FPGA clock.  You then send it through one more flip flop and logic that
detects when the input of this flip flop is 1 and the output is 0.  This is
a simple edge detect circuit that will generate a clock enable that will
tell a register to latch the data from the CPU data register.

Basically you have a system that tells the FPGA when the CPU data is stable
and safe to read.

With a bit more work on the hardware side, you can eliminate the CPU having
to write a 0 and a 1 by creating logic that detects when the CPU does a
write to the data register.

This is a low bandwidth solution.  If you need more bandwidth (which it
doesn't sound like you do), then you can look into implementing an
asynchronous fifo.  And you'll have to do something slightly different if
your FPGA clock has to be slower than the CPU clock, for some reason.

Good luck on your project.


Regards,
Vinh




Article: 63858
Subject: Re: Block RAM simulation VII
From: "Vinh Pham" <a@a.a>
Date: Sat, 06 Dec 2003 01:16:42 GMT
Links: << >>  << T >>  << A >>
> "XST does not support block RAM initialization in Verilog."
>
> Why not?

Obviously because Verilog is inferior and you're being punished for your
sins.  >:_)

VHDL is the superior language, especially if you want carpel-tunnel
syndrome.


Regards,
Vinh



Article: 63859
Subject: Re: Dual-port and single-port BlockRAM instantiation
From: wv9557@yahoo.com (Will)
Date: 5 Dec 2003 17:21:34 -0800
Links: << >>  << T >>  << A >>
It should use the same amount of block ram whether configured
as single or dual ported RAM. You can look at the log to be sure
how many block ram are actually utilized.

arkagaz@yahoo.com (arkaitz) wrote in message news:<c1408b8c.0312050623.52b9b1fa@posting.google.com>...
> Hi all,
> 
> I am working with a 1 million gate Virtex II FPGA. I am instantiating
> large amounts of Block RAMs in my design and even though I am using
> Single-Port ones, I would like to know if there would be a trouble to
> instantiate them as Dual-Port ones. I mean, would it need twice the Block RAMs
> I am using now, or would it just configure them as Dual-Port?
> 
> Thanks,
> 
> Arkaitz.

Article: 63860
Subject: How to explicitly call out cell elements in Altera Stratix?
From: hooiwai@yahoo.com (J.Ho)
Date: 5 Dec 2003 17:31:30 -0800
Links: << >>  << T >>  << A >>
Hi all,

In Xilinx Virtex world, each element in the logic cell has a name and
can be explicitly instanstiated, such as "muxcy_l" etc...   Is there a
way to do the same thing for the Altera Stratix device?

In Xilinx data sheet all those cell elements has a name associated
with it in the figure, so it made it easy to know which element to
call up from the virtex library in the synthesis tool.  I can't find
any reference in the Altera document however, so just by inspecting
the stratix hdl technology/timing model library I can't be sure which
carry mux is which in the logic element.

Would someone who had hand massage the code with technology elements
share their method or the reference material from the vendor?

Thanks!

Jon

Article: 63861
Subject: Re: Floorplanning techniques
From: "Vinh Pham" <a@a.a>
Date: Sat, 06 Dec 2003 01:49:31 GMT
Links: << >>  << T >>  << A >>
R.B.

Yeah ideally you'd like to solve your problem by setting up constraints to
guide the tools, because your floorplanning work is more likely to be wasted
if your design changes significantly enough (though creating relative
placement macros for sub blocks of your design can help preserve your work).
Area constraints, as opposed to timing constraints, can be helpful in
nudging the tools to placing smarter.

Of course, like you said, the tools might not have enough smarts to do what
you want or it might take too long to place/route without some intervention.

As far as floorplanning, the main thing is is to understand the layout of
the routing resources in your target FPGA.  Xilinx's Spartan-III, for
example, has direct lines (that connect adjacent CLBs), double lines (that
connect every other), hex lines (which don't connect every 6 but every 3),
and long lines (which do connect every 6).  So from best to least, you want
logic in: 1) the same CLB, 2) adjecent CLB, 3) two CLBs away, 4) three CLBs
away, or 5) six CLBs away.  Four and five CLBs away could be worse than six.

A lot of times I find that when I floorplan I'm fixing some crazy things the
tools have done.  Like for some reason the tools will take a 32-bit register
and instead of keeping it in order, it'll mix it up in a seemingly random
fashion.

They seemed to have architected their FPGAs for data to flow horizontally,
so keep that in mind.  I'm not sure if it matters, but I always go
left-to-right because it feels natural.

Heh sorry I don't have too many pointers.  I try not to floorplan (unless I
want to veg out.  I find Xilinx's Floorplanner relaxing, it uses pretty
colors) and it feels more like an intuitive art than a science.  One thing
you can try is to compile your design with only the difficult logic and the
other logic removed.  This will help speed up the floorplan-route-results
cycle which sometimes can be more productive than trying to plan everything
up front, especially when we don't have a good knowledge of the routing or
we have the wrong ideas.

Best of luck,
Vinh



Article: 63862
Subject: Re: Ideal Development Machine Specifications
From: "Vinh Pham" <a@a.a>
Date: Sat, 06 Dec 2003 02:08:30 GMT
Links: << >>  << T >>  << A >>
> Although the price of a decent 17" screen's down to
> just over 300, and the screen area is nearly as big
> as my 21" monitor.

Yeah considering 21" doesn't mean 21" of useful screen space, for CRTs.
LCDs are a bit more honest.  They're easier on the eyes too.

Though getting cheaper still a bit pricey for me.  I really hope they can
bring organic LED into high volume manufacturing.

> The thinner surrounds would mean
> there would be less breaking up the desktop too.

Yeah so not only more virutal desktop space, but more real desktop space.  I
got enough junk on my desk already.

> Matrox also do 4 monitor output graphics cards :-)

LOL.  I think your brain would mutate from the EM waves coming from those
CRTs ;_)

 Regards,
Vinh


P.S.  Sorry Eric, for going off topic here, but it seems everyone has given
you good advice already  :_)  In general sufficent RAM (to prevent the use
of virtual memory) is more useful in all situations, while a dual CPU will
only help when you do a lot of seedhunting or want to run another app while
routing.



Article: 63863
Subject: Re: Ideal Development Machine Specifications
From: "Vinh Pham" <a@a.a>
Date: Sat, 06 Dec 2003 02:12:13 GMT
Links: << >>  << T >>  << A >>
> "Eric BATUT" <grostuba@ifrance.com> wrote in message
news:ee81678.9@WebX.sUN8CHnE...
> Thanks a lot to everyone for the various advices.
> For the techie lovers out there, the video car will be a NVidia Quadro 4
280 NVS with dual-screen output > and DVI adapters, for the two Eizo 19" LCD
screens.
> And yes, I'm drooling while I'm writing this...
> Once again, thanks a lot, and have a nice day...
> Eric

You gloating bastard ;_)  How did you convince your boss, that's what I want
to know!  Enjoy and happy routing.

Vinh



Article: 63864
Subject: Re: VHDL-Testbench-Simulation in QuartusII
From: "Subroto Datta" <sdatta@altera.com>
Date: Sat, 06 Dec 2003 02:15:05 GMT
Links: << >>  << T >>  << A >>
http://www.altera.com/support/software/nativelink/quartus2/glossary/def_vht.
html

- Subroto Datta
Altera Corp.




A VHDL Test Bench File is the same as a standard VHDL test bench file, saved
with a .vht extension.



"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0312050619.24a357e6@posting.google.com...
> Hi @ all,
>
> how can I simulate a testbench written in VHDL in QuartusII 3.0
> software?
>
> Do I have to save it as a .vhd file or what kind of file is needed
> to simulate with Altera-Modelsim?
>
> Under SETTINGS --> EDA TOOL SETTINGS --> SIMULATION I choose
> ModelSim-Altera
> Under SETTINGS --> EDA TOOL SETTINGS ---> SIMULATION
> --> ADVANCED
> there can be chosen "Test Bench Mode". But when I want to select
> the Test Bench File there are only .vht files?
> How can I save a .vhd file as a .vht file?
>
> Thank you very much
>
> Kind regards
> A.Lapa



Article: 63865
Subject: MicroBlaze - how much memory?
From: RISC_taker@alpenjodel.de (RISC taker)
Date: 5 Dec 2003 21:40:07 -0800
Links: << >>  << T >>  << A >>
Hi! How much extra RAM (additional to the pure code size of the user
program) do I usually need for a MicroBlaze system??

I am considering MicroBlaze for a Spartan-3 project. Peripherals would
be a UART and my own memory mapped peripheral. Assuming that my
program can be compiled into less than 300 assembly instructions, it
should fit into one single BlockRAM, right? (300 * 32 bits = 9600 bits
< 18 KBits).

Now what about data memory? My program wouldn't need much. Could I
squeeze that into the second half of the same blockRAM? Or is that
physically not possible?

And most important: do the binaries get significantly bigger than just
the assembled functions? Is there any other stuff that gets compiled
into the program (UART stuff or whatever) that makes it big?

Thanks a lot for your answers!

Article: 63866
Subject: Re: Block RAM simulation VII
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Sat, 06 Dec 2003 06:18:15 GMT
Links: << >>  << T >>  << A >>
"Vinh Pham" wrote:

> > "XST does not support block RAM initialization in Verilog."
> >
> > Why not?
>
> Obviously because Verilog is inferior and you're being punished for your
> sins.  >:_)

Ain't that the truth!  The first part, I mean. :-)


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



Article: 63867
Subject: Re: Floorplanning techniques
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Sat, 06 Dec 2003 06:32:46 GMT
Links: << >>  << T >>  << A >>
"Muthu" wrote:

> For FPGAs, the Vendor tools will do the the floor planning job in a
> better way.

Well ... first of all, the tools don't floorplan.  At all.  They simply
place and route the logic for a design in order to meet whatever constraints
you specify.  Floorplanning, from my vantage point, involves (and requires)
a higher level of thinking than what these tools can provide.

There have been many discussions on this N.G. about this.  Hands down, if
you know what you are doing you can squeeze gobs more performance out of a
smaller and cheaper device than the tools seem to be able to deliver.
Floorplanning might also involve knowledge that the tools would not have
purely from timing constraints, like "my dev board has a two million gate
device but the product will have a 500K".

Again, discussed extensively here, the pushbutton approach doesn't tend to
do a good job aligning data paths and getting creative about layout.  All
you have to do is start getting into building RPM's to realize how bad it
can get (when you compare to pushbutton) even in small test designs.

Also, floorplanning might be absolutely necessary for certain design flows.


The bottom line is that the pushbutton approach does not floorplan at all,
that still requires a human brain with more than one neuron firing.

The good news is that a properly constrained design is very likely to work
well via pushbutton these days.  I would imagine that most designers out
there don't get into floorplanning and RPM's at all.  It is only when you
want (or need) to push some limit (area, speed, device migration, etc.) that
playing in deeper water is the only way to go.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"




Article: 63868
Subject: Verilog-2001 `define expressions?
From: toby <toby@toby.com>
Date: Sat, 06 Dec 2003 07:07:58 GMT
Links: << >>  << T >>  << A >>
I was trying to use a macro 'expression' --

`define MAXIMUM2( x, y ) ( ((x)>(y))?(x):(y) ) // return greater value

parameter A_W = 10;  // Abus width (#bits)
parameter B_W = 12;  // Bbus width (#bits)
parameter C_W = `MAXIMUM2( A_W, B_W ); // Cbus: intersect(A_W, B_W)

This works in NC-Verilog 4.0, Modelsim 5.6, Design Compiler 2003.06, and 
Ambit/PKS 5.0.  Xilinx ISE 6.1i's "XST" doesn't like it.  Overall, so 
far so good!

Then I tried to get more clever ...

`define MAXIMUM3(x,y,z ) ( (`MAXIMUM2(x,y)>z) ? (`MAXIMUM2(x,y)):(z) )

This barfs on most of the above...

Do any Verilog tools support nested MACROs?

('common, C-programmers have been doing this sort of #define stuff for 
ages!)

Also don't worry...I'm not using the MACROs to evaluate combinational 
exprsesions.  I use the MACROs in parameter definitions.  (I have some 
data-bus width conversions in a few datapath modules.  Each 'node' needs 
to be sized to the larger of the 2 endpoints.)


Article: 63869
Subject: Re: Altera's altsyncram MAXIMUM_DEPTH
From: =?iso-8859-15?Q?Manfred_M=FCcke?= <manfred.getmuecke@ridgmxof.thisat>
Date: Sat, 06 Dec 2003 09:29:44 +0100
Links: << >>  << T >>  << A >>
Hi Subroto,

I would like to renew my question: Why do you restrict FIFO depths to 
powers of two? I can't see the need for that.

Regards, Manfred

Article: 63870
(removed)


Article: 63871
Subject: Mixing simulation of behavioral and synthesized code
From: "Silvano Bettinzana" <bettinzana@diadix.it>
Date: Sat, 06 Dec 2003 14:36:10 GMT
Links: << >>  << T >>  << A >>
Dear friends,

I'm a novice and playing with Xilinx ISE Webpack and ModelsimXE.
I have a 'TOP' Verilog module in which I have instanced 2 module: 'A' and
'B';
I have a testbench for 'TOP' and want to simulate with 'A' sinthesized and
'B' not synthesized ('B' is not synthesizable; it has for example '#...'
statement).
Is this possible ?
How ?

Thanks and Regards

Silvano




Article: 63872
Subject: Re: Block RAM simulation VII
From: "Vinh Pham" <a@a.a>
Date: Sat, 06 Dec 2003 19:37:56 GMT
Links: << >>  << T >>  << A >>
> > Obviously because Verilog is inferior and you're being punished for your
> > sins.  >:_)
>
> Ain't that the truth!  The first part, I mean. :-)

Heh heh.  Time to start a VHDL vs. Verilog flame war :_)

Page 155 of the manual...oh I see, it's talking about having XST implicitly
infer a block ram from your HDL code.  Hmm I don't know Verilog, but I would
assume it'd have the ability to initialize the values of an array, similar
to VHDL.  But even if it doesn't, you would think they can pass
initialization information through another mechanism, even perhaps through a
specially formatted comment section.

It's probably the usual "not enough people to implement all the features
we'd want; and not enough customers, or big customers, complaining about
it."

I suppose you could always go through CoreGen/explicite declaration of
BlockRAM route, and use it to initialize your ram.  The contents would be
easy to modify, when it comes to simulation at least, since it uses a text
file (.MIF) to get the values.  I'm not sure about the real hardware though.
The values might be embedded in the EDIF, which would be a bit more of a
hassle to modify.

In either case, you don't have the values handy inside of your Verilog code.
I guess you could write a Perl script that looks for a specially formattted
comment section in your Verilog, and then modify the EDIF.

Just another reason why VHDL is better ;_)

Actually I haven't used Verilog so I can't make an informed opinion...but
then again, that's never stopped people before!


Regards,
Vinh




Article: 63873
Subject: Re: Floorplanning techniques
From: Philip Freidin <philip@fliptronics.com>
Date: Sat, 06 Dec 2003 20:47:47 GMT
Links: << >>  << T >>  << A >>
richieb@rediffmail.com (richie singh) wrote in message news:<a0238c18.0312041811.56cc43d9@posting.google.com>...
> Hi, 
> I recently started working with FPGAs and am would like to learn about
> floorplanning techniques. Could someone point me to documents or
> design guides dealing with what issues should be kept in mind while
> floorplanning a complex design..
> Thanks to all who reply!!
> R.B.

Somewhat dated, but at least a start:

    http://www.fliptronics.com/floorplanning1.html

Philip




Philip Freidin
Fliptronics

Article: 63874
Subject: Re: Block RAM simulation VII
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Sat, 06 Dec 2003 23:55:52 GMT
Links: << >>  << T >>  << A >>
"Vinh Pham" wrote:

> Heh heh.  Time to start a VHDL vs. Verilog flame war :_)

Don't feel like doing that.  But, clearly there are very compelling reasons
to use VHDL for synthesis if you go beyond plain-vanilla pushbutton designs.
Part of it might be due to the folks involved in writing the standards, I
learned about this in the Verilog NG ... it was like talking to someone from
another planet.

> Page 155 of the manual...oh I see, it's talking about having XST
implicitly
> infer a block ram from your HDL code.

I don't really use inference for these constructs, I instantiate explicitly.
Why would you speak Greek when you know you need to say something in French
and you can speak French?  Maybe 'cause I'm old school ... I still have my
auto-stripping electric wire-wrap gun.

No, I was just doing the usual "look through every manual to see why this
isn't working" routine.  That was the only reference I found on this
question.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"






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