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"Jesse Kempa" <kempaj@yahoo.com> wrote in message news:95776079.0405160944.ecb0ac@posting.google.com... > geoffrey wall <wallge@eng.fsu.edu> wrote in message news:<c82o6r$g2m$1@news.fsu.edu>... > > Im looking to do some real-time video processing algorithms, > > but i am mostly a software person... i need an fpga with good > > development tools (not buggy) that will be easy to use for someone who > > is learning how to program hdl and use the hardware for the first time. > > Ideally i would like a powerful and flexible board with good development > > tools, good tech support and documentation. Any suggestions? > > > > thanks > > I normally don't plug my employer's products, but what you're asking > for is covered quite nicely by the embedded dev kits from Altera as > well as from our partner Microtronix. I suggest this approach as > putting processor core(s) on the FPGA is very simple these days; for > someone with software experience this can make getting started with > hardware design a bit more simple as a processor allows you to bring > up a design/debug/interface to your hardware with familiar means > (software dev. & debug). Also consider a soft-processor has terrific > potential for controlling the various hardware processing blocks in a > design very easily. > > Also note that with any of these products you aren't required to use > the processor; they're really just FPGA dev. boards with additional > design tools/IP/RTOS support in the box. > > http://www.microtronix.com/ > http://www.altera.com/products/ip/processors/nios/kits/nio-dev_kits.html > > Jesse Kempa > Altera Corp. > jkempa at altera dot com I'll second Jesse's recommendations. I'm an EE, but have been primarily involved in software. When I and another software guy went to a free class on the Altera Nios running on the Cyclone devkit board we were instantly hooked. The tools and the workflow are very familiar to a software engineer. Do a google and google groups search if you want more details. KenArticle: 69626
Martin Maurer wrote:
> i am trying to learn how to use ModelSim with a VHDL Testbench, but i don't
> find any answers on a few of my answers.
Learn google grooups searches.
> 1) I can see all my stimuli, which are mainly the external in- and outputs.
> They seems to toggle fine. But how can i display the internal signals ? Is
> the only solution to assign a port to an internal signal to see it in
> ModelSim. I already tried to simply define new signals, they are drawn in
> ModelSim, but it seems they are not connected to the real signals. I think i
> was able to add internal signals via "Signal" window, but next time i
> simulate the signal was lost again...
http://groups.google.com/groups?q=vsim+add+wave
> 2) I am currently can simulate my design once. When i external edit my vhdl
> source or testbench i always must close ModelSim and restart it via Xilinx
> Projects Manager. If i don't close it, i get an error message, that
> "ModelSim is already running". Is there a more convenient way ?
http://groups.google.com/groups?q=vsim+command+line+vmap
> 3) I found a few nice commands like "view wave", "add wave *". Is there a
> command for full zoom ? Where can i say, that certain commands should be
> executed e.g. after drawing of a wave ?
http://www.google.com/search?q=vsim+wave+zoom
>
> 4) Every time when i open ModelSim the wave window is only a small window,
> positioned at right/lower corner of my screen. I already edited the wave
> window "geometry", saved it to default name modelsim.tcl of my project
> directory. But on next restart same windows size and position as before.
> Must i move this file to a certain position. Is there a command like "use
> preferences" that i can execute like in question 3 ?
Don't know. I size windows manually.
> 5) In my vhdl source file i use a "std_ulogic_vector", because i want to use
> tristate pins, for bidirectional data transfer of data. In the testbench the
> xilinx tool created a testbench with "std_logic_vector". It compiles fine.
> When i change it to "std_ulogic_vector" in testbench, ModelSim brings a
> compile error, that source and testbench does not fit together. I already
> use 'Z' for assignments and it seems to work. Should i just ignore this or
> must i pay attention when doing it this way ? ModelSim can handle tristate
> logic ?
http://groups.google.com/groups?q=vhdl+oe_demo
> 6) Is there a FAQ for such questions ?
http://www.model.com/
http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html
-- Mike Treseler
Article: 69627"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote... > I have been doing some investigation into blob analysis algorithms > and would like to know if there are any designs that have been > rendered into FPGAs. Brad, We are doing some work in this area for a robotics application. When we first started our investigation of the literature, we found that the existing implementations did not meet with our requirements for implementation in an FPGA. In our system we require that the pixels be presented to any image processing engine only once, or we will get killed on memory bandwidth. Most of the existing literature details algorithms that are stack based that iterate through the image in a pattern that can not be known a priori. Additionally, these algorithms tend to require a variable amount of time, depending on the number of blobs that are identified, and the shapes of these blobs. A run length encoding approach, which I have seen detailed in the literature, is a good starting point for the requirements that we had, especially since we could ignore non-convex blobs in our application. Though, it should be noted, a linescan blob finder can find non- convex blobs, as long as it is capable of merging two or more blobs that are found to overlap later in the image. For any discussion to go forward, it would be helpful to understand what your requirements are. If this is a commercial application, please feel free to contact me offline, as we may be able to adapt an existing core from our library. If this is to be a public exercise, please offer the group an idea as to the following: performance requirement application maximum number of objects that you wish to find in a given image whether you need to just find objects, or track across images do you need to find non-convex blobs? Blobfinding can be done in guaranteed time in a linescan fpga implementation, the details of the implementation are highly dependent upon the answers to the above questions. Regards, Erik Widding. --- Birger Engineering, Inc. -------------------------------- 617.695.9233 100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.comArticle: 69628
Hi Ed, Well, if you use a DCM to manage your on chip clock, you should be able to adjust the timing to whatever you want. For example on the output side, you can set the DCM to eliminate any phase difference between the on-chip clock and the SDRAM's clock. Use the IOB's output FFs. Then the delay introduced by the FPGA is simply the 'clock CLK to PAD' IOB output delay, specified in the data sheet, (<2ns at a guess), assuming you meet the setup specification. Also, you can fiddle about with the DCM phase shift to further optimise things, have a play! As for getting the data into the chip, you need to consider the 'Pad to I output' .... etc.. It's all in the manuals! Cheers, Syms.Article: 69629
Alessandro, Alessandro Scaglione wrote: > By default IPIF ssp1 uses generic driver, that seems not support > PARAMETER INT_HANDLER. > 1.How can attach a int_handler to IPIF device? I have to write a > specific driver for each IPIF device? Rather than using the default generic driver, you will need to create a custom driver for your device that supports interrupts. Specifically, you will need an array that describes the interrupt handler for a unique interrupt port. For an idea of how the MDD file should look, see the timer-counter drivers as reference. Also, consult the EST Guide for information on MDD syntax. > 2.It's possible to specify interrupt level for external interrupt signals? Yes, it is. This is done on the interrupt declaration line in the MHS file. Below is an example snippet. Consult the EST Guide for the MHS attributes that can be attached on interrupt ports. Matt # Global Ports PORT external_int = external_int, DIR = IN, EDGE = RISING, SIGIS = INTERRUPT, LEVEL=LOW PORT GPO = GPO_OUT, DIR = IO PORT sys_clk = sys_clk, DIR = IN PORT sys_rst = sys_rst, DIR = I > > ThanksArticle: 69630
coop62194@yahoo.com (David Cooprider) wrote: >[CUT] >get that info from Lattice. Just let them know what you need. >Hope this helps. Sure it helps! :-) I do want to thank you and the other people who are helping me to solve my problems with the software. Before writing here I did not expect I could receive so much useful feedback ;-) Just give me some time to apply your suggestions. I will let you know about news. Thank you again, Fabio PS: I also received your email. I will reply to the other questions soon. -- Per rispondermi via email sostituisci il risultato dell'operazione (in lettere) dall'indirizzo -*- To reply via email write the correct sum (in letters) in the email addressArticle: 69631
Hi Comp.arch.fgpa, Is it possible to use output pins in parallel to get higher output currents? Specifically, I want to pair outputs of my cpld. In the assignment editor I can't assign the signal to two different output pins. I was playing around with conduits and stuff in the schematic, forking the counduit to two conduits and trying to assign each of them to output pins. However, this resulted in an "Error: Can't use conduits in network without blocks" Is there some way of doing this without using two macrocells per parallel output and if so, how can I achieve this? Your help is appreciated, FlorianArticle: 69632
So here is a "simple" thing that clearly isn't as simple as one would like.
I'm constructing a PWM unit for a robotics application, given the shortage
of pins on my microprocessor, I'm serially clocking in my data.
My "module" has sdata_in, sdata_out, sclock_in, sclock_out, clock_in,
pwm_out.
As I'm doing this in an inexpensive CPLD, I'd like to be able to gang a
couple together and just tie the sclock_out, sdata_out, to the next chip in
series and then create a chain of these things. However, inside my CPLD I'm
using code like
process (sclock_in, sdata_in) is
begin
if rising_edge(sclock_in) then
data_reg <= data_reg(14 downto 0) & sdata_in;
sdata_out <= data_reg(15);
end if;
end process;
sclock_out <= sclock_in;
Now the trick is that I want to insure that the rising edge of sclock_out
really happens when sdata_out is valid. So basically I'd like to "push" the
assignment of sdata_out ahead of the clock or delay clock out. In a non-CPLD
design I could simply put a buffer between the output clock and the next
chip to add some setup time (at the cost of system throughput I know, I
know) but since we're way under the speed limits here (400K serial
bitstream) it wouldn't be too egregious.
Thoughts? Just let it ride? pointers to a discussion on clock management?
--
--Chuck McManis
Email to the devnull address is discarded
http://www.mcmanis.com/chuck/
Article: 69633I need to make a mpeg layer1 decoder description in vhdl and I don't find any information. Can somebody help me?Article: 69634
>Now the trick is that I want to insure that the rising edge of sclock_out >really happens when sdata_out is valid. So basically I'd like to "push" the >assignment of sdata_out ahead of the clock or delay clock out. In a non-CPLD >design I could simply put a buffer between the output clock and the next >chip to add some setup time (at the cost of system throughput I know, I >know) but since we're way under the speed limits here (400K serial >bitstream) it wouldn't be too egregious. buffers like that are kludges. They are asking for troubles with CPLDs or FPGAs since the software is likely to eat them and/or the routing may be much slower than a buffer. (They can be made to work if you don't have any other choices and are willing to hand route and hand check that area.) Can you clock data_out on the falling edge? You really want to do something like that. (both in your repeater logic and at the source) Another approach which takes more logic is to have a local clock that runs much faster than the bit rate and just watch for transistions on the "clock" line. Then you can insert delays by whole clocks. (including negative delays) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 69635
"rat" <rattt@col.edu.cn> wrote in message news:c7kjvf$2l0m$1@mail.cn99.com... > Hi, > Is it possible to make a USB 1.1 interface only with FPGA chip, I mean, > without addtional transceiver chip? I don't believe so, the signalling levels and pin tolerances of the USB spec aren't supported by any FPGA vendor AFAIK. You can get tiny SMD trancievers anyway so what's the problem? Another question would be does anyone have a HOST controller core? --ChuckArticle: 69636
On 16 May 2004 17:49:22 -0700, jacobocg@yahoo.es (jacobo) wrote:
>I need to make a mpeg layer1 decoder description in vhdl and I don't
>find any information.
>
>Can somebody help me?
1) Go to Google.
2) Type:
mpeg decoder VHDL
3) Hit "Enter" key.
Bob Perlman
Cambrian Design Works
Article: 69637"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message news:tm6ga01gfffuana5ppdc005n3cfu0hm4t2@4ax.com... > On 16 May 2004 17:49:22 -0700, jacobocg@yahoo.es (jacobo) wrote: > > >I need to make a mpeg layer1 decoder description in vhdl and I don't > >find any information. > > > >Can somebody help me? > > 1) Go to Google. > > 2) Type: > mpeg decoder VHDL > > 3) Hit "Enter" key. > > Bob Perlman > Cambrian Design Works Bob, I tried your suggestion, too, about Google. It really worked. Thanks for letting loose of this secret. From now on, I won't have to rely on others to do the work that I can do for myself. It's like the old saying goes: Give a man a fire and he'll be warm for a day. Set a man afire and he'll be warm for the rest of his life. Regards, BobArticle: 69638
If I've got two signals in VHDL :
signal pwm_thresh : std_logic_vector (31 downto 0);
signal pwm_count : std_logic_vector (31 downto 0);
and I write ...
if ( pwm_thresh > pwm_count ) then
pwm <= '1';
else
pwm <= '0';
end if;
Does it work? I've not managed to successfully simulate it yet. Perhaps if I
wrote:
if ( unsigned(pwm_thresh) > unsigned(pwm_count) ) then
--
--Chuck McManis
Email to the devnull address is discarded
http://www.mcmanis.com/chuck/
Article: 69639Hal Murray wrote: >>Now the trick is that I want to insure that the rising edge of sclock_out >>really happens when sdata_out is valid. So basically I'd like to "push" the >>assignment of sdata_out ahead of the clock or delay clock out. In a non-CPLD >>design I could simply put a buffer between the output clock and the next >>chip to add some setup time (at the cost of system throughput I know, I >>know) but since we're way under the speed limits here (400K serial >>bitstream) it wouldn't be too egregious. > > > buffers like that are kludges. They are asking for troubles > with CPLDs or FPGAs since the software is likely to eat them > and/or the routing may be much slower than a buffer. (They > can be made to work if you don't have any other choices and > are willing to hand route and hand check that area.) > > Can you clock data_out on the falling edge? You really want > to do something like that. (both in your repeater logic and > at the source) > > Another approach which takes more logic is to have a local > clock that runs much faster than the bit rate and just watch > for transistions on the "clock" line. Then you can insert > delays by whole clocks. (including negative delays) Besides Hal's comments of 'Care and watch the tools like a hawk', I'd suggest : Look at the 4094 / HC4094 data, which show a cascade scheme, but with a common clock. Buffering the clock can sometimes be necessary (eg cascade opto-isolations ), and if you do that, it is good practice to derive the SHIFT CLOCK from the OUTPUT pin - that avoids creeping race conditions, and also if ANY form of additional buffering is being used, you will need to latch your cascade data on the opposite edge. ( gives 1/2 CLK Tsu.Th ) If you want to cascade a lot of these, you will also need to watch skew degradation. -jgArticle: 69640
"Jon Beniston" <jon@beniston.com> wrote in message > Why bother with Open Source stuff when various incarnations of > commerical tools are free to use? Check out for the Xilinx WebPack: > Because I'm using FreeBSD/KDE ? I really sympathize with the desire to get tools that are "open" or at least interoperable. I had the misfortune of participating in the "CAD Framework Initiative" back in the early 90's when briefly, the major powers of CAD believed they could agree to some open interfaces so that each others tools could be mixed and matched. Some of that work lives on in things like EDIF but for the most part vendors don't want to do anything that might make it possible for someone to compete with them. --ChuckArticle: 69641
Hi, I have a small doubt regarding the load seen by a primary global clock buffer in a FPGA. My design consumes 1940 flops out of 3072,and also the load in the BUFGP shows only 1940 flops .I thought as the clock tree is pre-synthesized, no matter how many flops are consumed, the clock signal is driven to each and every flop.Can anybody comment,how it is disabled in unused flops so that clock buffers do not see the load in unused flops.Is it same for GSR?? thanks --rajArticle: 69642
On Sun, 16 May 2004 23:59:33 GMT, "Chuck McManis" <devnull@mcmanis.com> wrote: > > .... > cascaded devices with serial data In and Out, also considering > daisy chained clock. Freq is 400 KHz. > .... > A good example of how this is solved is the serial daisy chain configuration of the Xilinx FPGAs. It even uses one less pin than what you are thinking of, since there is no need for a clock out pin. The clock goes to all devices. What Xilinx does, is it samples the data coming into each chip on the rising edge, and the daisy chained data out is clocked on the falling edge. For your application with a 2.5 us cycle time, that gives you a setup and hold window of 1.25 us, which should work regardless of logic family, and the size of your PCB. Depending on the length of the shift register within each device, the latency is N + 0.5 clock cycles per device. But this does not accumulate across devices, as the .5 cycle of latency is treated as part of the device to device delay. Example of devices with 5 bits of SR. DEV1: rising edge , clocks in data bit 0. 5 th rising edge clocks bit 0 into last position of SR in device 1. (DEV 1 now has bits 0..4) Following falling edge (5.5 cycles after start), Serial out is updated with bit 0 DEV2: 6 th rising edge clocks bit 0 into the second device. (and data bit 5 goes into DEV 1) This scheme (at your clock rates) is extremely tolerant of variations in both clock and data routing. It can tolerate 100's of ns skew. Obviously it would be best if the original data source follows this protocol too, changing the source data at about the same time as the falling edge of the clock source. This is easily done even in a bit-banged micro interface. Philip Freidin Philip Freidin FliptronicsArticle: 69643
Good description. Thanks. >For your application with a 2.5 us cycle time, that gives you a >setup and hold window of 1.25 us, which should work regardless of >logic family, and the size of your PCB. Unless the chain gets too long and the signal integrity on the clock isn't good enough. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 69644
You think that it works? I'm looking for the vhdl description. Have you a direct link??????(It isn't so simple.)Article: 69645
Hi, I have the following problem: My FPGA has an input clock CLOCK30. This clock comes from an external transceiver. The clock CLOCK30 is used as the input clock of a PLL which generates a fast clock CLOCK90 whose period is a third (90MHz). For my FPGA controller I need CLOCK90 to be in phase alignment with CLOCK30. CLOCK30 is also used to clock the data into the external transceiver. (clock name at FPGA output pin (CLOCK30_OUT) So how can I manage that CLOCK30_OUT is in phase alignment with CLOCK30 and CLOCK90 ? I am using Altera Cyclone Device with its PLL. The paper "AN251 : Using PLLs in Cyclone Devices" does not show anything about aligning phase relationship of clock input pin, clock at register clock port AND clock output pin" I would appreciate your help. Kind regardsArticle: 69646
Thanks for your answers, in Xilinx forum http://toolbox.xilinx.com/cgi-bin/forum?50@60.SnQlabZvfnD.5@.ee82b9c I read that someone uses uartlite driver instead generic driver to handle interrupts. Another question on external interrupts: I need to write a device driver for extenal interrupts, too?Article: 69647
"Chuck McManis" <devnull@mcmanis.com> writes: > If I've got two signals in VHDL : > signal pwm_thresh : std_logic_vector (31 downto 0); > signal pwm_count : std_logic_vector (31 downto 0); > Why not define these as "unsigned(31 downto 0)"? You're representing real numbers after all, not just large collections of bits (which is all a std_logic_vector implies). > and I write ... > if ( pwm_thresh > pwm_count ) then > pwm <= '1'; > else > pwm <= '0'; > end if; > Then that should work. Remember to include use ieee.numeric_std.all; at the top! Then you don't need to faff about with type-casting. HTH, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 69648
Hi guys and gals, Could I call on your collective experience and expertise? I'd like to get hold of an FPGA development board for a data streaming project. Requirements are as follows: - Low cost (around 200 UK pounds ideally). - At least 16 i/os routed out to connectors. - High speed cabled interface to a PC, capable of sustaining a streaming rate of at least 15Mbits/s. I've been considering USB2 or 100M Ethernet for this. - Enough onboard RAM to ensure continuous data transfer to software running on a Windoze PC. - Single power supply @ 5V or 3.3V. The best boards I've found so far are: Cyclone FPGA + basio (too expensive + 10M Ethernet too slow) http://www.jopdesign.com/cyclone/index.jsp Easy FPGA (USB too slow + not enough RAM for streaming) http://www.easyfpga.com/ez2susb_features.htm NuHorizons Spartan 3 and others (no high speed interface) http://www.nuhorizons.com/products/xilinx/spartan3/development-board.html Emulation Technology System board + Ethernet module (not enough RAM for streaming) http://www.emulation.com/catalog/off-the-shelf_solutions/devsystems/xilinx2.html Does anyone know of a board which might meet my requirements? Of the above, the Emulation Technology solution provides the closest fit, if only it had some onboard RAM. Cheers DaveArticle: 69649
Hello, =20 There are some schematic files (*.sch) developed using Xilinx Foundation 4.2.=20 I am going to use those file using 3rd party software, which does not recognized *.sch. =20 Is there such away so that i can convert those *.sch files to *.vhd files ? It seems like i could not find that function in Xilinx Foundation 4.2 =20 Kindly please advice. =20 Thanks, =20 -Basuki-
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Compare FPGA features and resources
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