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rickman wrote: > > > I don't think it will make much difference either way, except for fast > designs where you need to control each state variable and output to meet > timing. Then it will likely be easier to control your result if the > counter is separate. I doubt that the synthesizer can figure out that > several counters can be optimized into one, but it won't see your delay > states as a counter. They will just be more states in your FSM and the > entire machine will be optimized together. As long as you don't try to > use one hot encoding, it will do a reasonable job of it. The only > question is, will the added counter states make the FSM too complex to > run at your required speed? Keeping the counter separate will allow you > to make the FSM simpler and easier to meet timing. > I thinks that's exactly right. I use embedded counters in relatively simple SMs or ones clocked by a slow clock e.g. dumb io device or Flash timing or 33MHz PCI, but separate ones in e.g. the SDRAM controller. For clarity though I tend to use a separate "wait" state to do the counting in the embedded case. Wouldn't it be nice though if something like this was synthesisable: my_state_N: begin repeat ?? @(posedge clk); state <= <figure out next state>; endArticle: 40251
Ray Andraka wrote: > "<snip> ...the BRAM acts as though it is registered, although I believe > the actual implementation has the register on the address, not on the memroy > outputs. That is correct. When enabled, the clock edge latches up the address (and the data for a write operation). That's why Enable and WE have a longer set-up time than A and D. This also explains the longer clock-to-out time: it involves a big address decoder. But, timing aside, the read output appears registered, since it does not change until the next enabled clock edge (on the same port). Address and data inputs have no effect by themselves, they always have to wait for a clock. Hope this clarifies it. Peter Alfke, Xilinx Applications >Article: 40252
> I doubt that the synthesizer can figure out that > several counters can be optimized into one, but it won't see your delay > states as a counter. They will just be more states in your FSM and the > entire machine will be optimized together. As long as you don't try to > use one hot encoding, it will do a reasonable job of it. Humm. Anybody ever build a one-hot state machine with a clump of states hidden inside a LUT used as a shift register? Probably not practical if you need a big count, but it might be denser than the control logic and an external counter for sizes up to 32 or 64. This obviously only works if you don't need to use the hidden state bits. Or you build extra logic to remember that you are in that clump of states. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 40253
Hal Murray wrote: > > I doubt that the synthesizer can figure out that > > several counters can be optimized into one, but it won't see your delay > > states as a counter. They will just be more states in your FSM and the > > entire machine will be optimized together. As long as you don't try to > > use one hot encoding, it will do a reasonable job of it. > > Humm. Anybody ever build a one-hot state machine with a clump > of states hidden inside a LUT used as a shift register? > > Nice! One for the toolbox.Article: 40254
I developed a small vhdl module to handle an SPI interface to a chip.
The cpu (8051 derivative) will pull pce down, wr or rd down to
write/read, and then pulls pce/rd/wr up. wr/rd pulse is 750ns. pce to
wr is appx 100ns. the global clock to 3064A-10ns is 24.576Mhz.
raddr/caddr are set with pce and are stable during rd/wr cycle.
pce/rd/wr/addr lines are direct from the cpu, data is thru a 74lcx245
where enable is simply (not ( (not pce) and (rd xor wr) ) ).
for some odd reason, about 2% of writes that set xcs or rst are
failing (i.e. wrong value is set). reads seem to be quite stable
[always give the right value]. scope doesn't show anything weird but
the wire connecting the clock output to the max3064A global clock
input is 2" or so which is a little long, but i can't see how that
would explain this behavior.
i tried changing the code to latch the value once a few clock cycles
into wr to no avail. i am out of ideas at this stage -- anyone have
any suggestions? thanks.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity chipint is
port (
mclk : in std_ulogic; -- master clock
mrst : in std_ulogic; -- master reset
pce : in std_ulogic; -- enable (active low)
rd : in std_ulogic; -- read (active low)
wr : in std_ulogic; -- write (active low)
raddr : in std_ulogic; -- reset address bit
caddr : in std_ulogic; -- clock addr bit
data : inout std_logic; -- data bus
rst : buffer std_ulogic; -- chip reset
xcs : buffer std_ulogic; -- chip chip select
sck : out std_ulogic; -- chip shift clock
si : out std_ulogic; -- shift in to chip
so : in std_ulogic); -- shift out from chip
end chipint;
architecture behavior of chipint is
begin -- behavior of chip spi communication
chipint_ctrl: process (mclk, mrst)
begin
if ( mrst = '0' ) then
xcs <= '1';
sck <= '0';
si <= '0';
data <= 'Z';
rst <= '0';
elsif ( rising_edge(mclk) ) then
if ( pce = '0' ) then
if ( wr = '0' ) then
if ( raddr = '1' ) then
if ( caddr = '1' ) then
rst <= data;
else
xcs <= data;
end if;
else
sck <= caddr;
si <= data;
end if;
elsif ( rd = '0' ) then
if ( raddr = '1' ) then
if (caddr = '1' ) then
data <= rst;
else
data <= xcs;
end if;
else
sck <= caddr;
data <= so;
end if;
else
data <= 'Z';
end if;
else
data <= 'Z';
end if;
end if; -- clock
end process chipint_ctrl;
end behavior;
Article: 40255As far as I know, you will get junk (undefined data). I believe the initiator (master) has to turn off the driving of AD[31:0] immediately after an address phase in a read cycle. Normally, you shouldn't have to reference the data on AD[31:0] in a read cycle after the address phase because in a read cycle, the target device supplies the data to AD[31:0]. Kevin Brace (Don't respond to me directly, respond within the newsgroup.) Vladimir Ralev wrote: > > There is still something unclear: > If I sample the data on AD[31:0] during a turnaround cycle after the > address phase(the example u mentioned about), what would i get? The > last state? > > ThanksArticle: 40256
I heard somewhere that ModelSim XE runs at 1/5 of the speed of ModelSim PE. But isn't ModelSim XE about 1/5 of the price of ModelSim PE? (ModelSim XE < $1,000 vs. ModelSim PE = $4,500 to $6,000 I think.) In my case, I am really poor, so I use ModelSim XE-Starter which is free, but it is even slower than ModelSim XE after 500 lines of code. Despite ModelSim XE-Starter being really slow, I have done a Post P&R simulation with it, where I simulated a design for 10,000ns at 33MHz that occupied about 50% of XC2S150-5. The simulation took about 3 to 4 hours to finish, but it is much much better than not being able to do a Post P&R simulation at all. Of course, an RTL simulation takes only 2 minutes when I use the exact same test code, so most of the time I do most of my simulation in RTL (like everyone else), and do a Post P&R simulation when I am finally ready to burn a Configuration PROM. Kevin Brace (Don't respond to me directly, respond within the newsgroup.) Yunhsianghsu wrote: > > Dear All, > > I am using Xilinx Spartan II only in my projects. I have ModelSIm PE to be my > simlulator. As I known, Xilinx release a new simulator, MXE 5.5. Comparing > those two proces, MXE seems much cheaper. > > If I am going to use Spartan II only, is it better to purchase MXE ? > > Please advise, thanks. > > KennyArticle: 40257
Ray Morales wrote: > > I developed a small vhdl module to handle an SPI interface to a chip. > The cpu (8051 derivative) will pull pce down, wr or rd down to > write/read, and then pulls pce/rd/wr up. wr/rd pulse is 750ns. pce to > wr is appx 100ns. the global clock to 3064A-10ns is 24.576Mhz. > raddr/caddr are set with pce and are stable during rd/wr cycle. > pce/rd/wr/addr lines are direct from the cpu, data is thru a 74lcx245 > where enable is simply (not ( (not pce) and (rd xor wr) ) ). > > for some odd reason, about 2% of writes that set xcs or rst are > failing (i.e. wrong value is set). reads seem to be quite stable > [always give the right value]. Is the 8051 clocked from the 24.576MHz, or in another clock domain ? Try and qualify on the leading edge of WRITE, rather than LOW write. -jgArticle: 40258
OK that gave me a push in the right direction. The problem turned out to be not letting the global pulses sit around long enough and that was in fact violating some setup time. Thanks! > > If you are using the post-fit net list then you have moved into the realm > of timing simulation and so you may be getting setup/hold violations on > your T-FF. The simprim models used for this simulation will set the > output to `X' when such a violation occurs. This is esp. likely if the FF > is sampling an asynchronous input. You could try either:Article: 40259
I will like to know if there is anyone who got NativeLink
feature of Quartus II 2.0 to work with LeonardoSpectrum-Altera.
I have been trying that with Quartus II 1.1 Web Edition yesterday, and
Quartus II 2.0 Web Edition today, but I never got it to work.
When I tried the NativeLink feature of Quartus II 1.1 WE with LS-Altera
Level 1 2001_28a, the Quartus II 1.1 WE simply hang up (Quartus_cmp.exe
caused a General Protection Fault when it tried to access MSVCRT.DLL or
something like that.).
So, I downloaded Quartus II 2.0 WE and LS-Altera Level 1 2002_014, and
this time Quartus II was able to start LS-Altera, but LS-Altera wasn't
able to synthesize my design.
Here is the message I got on Quartus II's screen.
____________________________________________________________________
Info: EDA tool information: Device is:
Info: EDA tool information: EPF10K100EFC484-1
Info: EDA tool information: Family is:
Info: EDA tool information: FLEX10KE
Info: LeonardoSpectrum software information: EPF10K100EFC484-1
Info: LeonardoSpectrum software information: FLEX10KE
Info: LeonardoSpectrum software information: spectrum
..\My_Design\My_Design.v ls_work\My_Design_Top.edf -product=ls1
-tar=flex10ke
Info: LeonardoSpectrum software information: LeonardoSpectrum Level 1 -
v2002a.14_OEM_Altera (Release OEM Altera Candidate, compiled Jan 22 2002
at 02:33:16) Info: LeonardoSpectrum software information: Copyright
1990-2001 Exemplar Logic, Inc. All rights reserved. Info:
LeonardoSpectrum software information: Info: LeonardoSpectrum software
information: Checking Security ... Info: LeonardoSpectrum software
information: Messages will be logged to file
'C:/My_Design/ls_work/My_Design_Top.log'... Info: LeonardoSpectrum
software information: -- Info: LeonardoSpectrum software information: --
Welcome to LeonardoSpectrum Level 1 Info: LeonardoSpectrum software
information: -- Run Started On Sun Mar 03 17:31:17 Central Daylight Time
2002 Info: LeonardoSpectrum software information: -- Info:
LeonardoSpectrum software information: -- Reading target technology
flex10ke Error: LeonardoSpectrum software error: Error, cannot find file
'flex10ke.syn' Info: LeonardoSpectrum software information: Warning:
Can't analyze file -- file C:\My_Design\ls_work\My_Design_Top.edf is
missing
Info: Found 0 design units and 0 entities in source file
C:\My_Design\ls_work\My_Design_Top.edf
Error: Node instance instantiates undefined entity My_Design_Top
Error: Design My_Design_Top: Full compilation was unsuccessful. 2
errors, 1 warning.
____________________________________________________________________
Note that I changed the file names of the log file for privacy reasons.
What is going on, and am I doing something wrong?
I already set PATH and EXEMPLER environmental variables to point to the
directory LS-Altera resides.
When I create a project in LS-Altera, LS-Altera handles the synthesis
fine, so I am puzzled why the thing doesn't work from Quartus II 2.0.
Is Altera releasing their products without adequate testing?
From my past bad experiences with Altera tools, I suspect that might
have just happened.
I am currently running both software on a Windows 98SE PC.
Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)
Article: 40260In my circuit there's a shift register with clk_enable and clk ports so if clk is 10ns period 50% duty Cycle while clk_enable is on just for (10*3)ns I would want to know how to set the constrain in this case. Attached there's the code of the shift register : library IEEE; use IEEE.std_logic_1164.all; entity shift_reg is port ( clk : in std_logic ; clk_en : in std_logic ; reset : in std_logic ; in_reg : in std_logic ; out_ffd_1 : out std_logic ; out_ffd_2 : out std_logic ; out_ffd_3 : out std_logic ; out_ffd_4 : out std_logic ; out_ffd_5 : out std_logic ; out_ffd_6 : out std_logic ); end entity; architecture shift_reg_arch of shift_reg is signal temp_out_reg : std_logic_vector(5 downto 0); begin process(clk, clk_en, reset) begin if reset = '1' then temp_out_reg <= "000000"; elsif rising_edge(clk) then if clk_en = '1' then temp_out_reg <= in_reg & temp_out_reg(5 downto 1); end if; end if; end process; out_ffd_6 <= temp_out_reg(0); out_ffd_5 <= temp_out_reg(1); out_ffd_4 <= temp_out_reg(2); out_ffd_3 <= temp_out_reg(3); out_ffd_2 <= temp_out_reg(4); out_ffd_1 <= temp_out_reg(5); end architecture;Article: 40261
Other simple (..not for me) questions : 1) Is a good Idea to attach a TIG to a reset net ?? 2) In my QPSK modulator there are two data input each of 1 bit, the maximum input data rate could be 55Mbps , until now I've not setted a pad to setup constrain but I'm asking if it is truly necessary, if I'm not in error this have to be (1/55e6) = 18ns . And this have to be done also for the output with a clock to pad constrain of (1/165e6) = 6.06ns Does this is right ?? AntonioArticle: 40262
I use Quartus2 1.1 SP2 with LS 2001.1d and find that I use Leonardo to
control quartus command line for P&R.
I didn't successfully get Q2 to control LS however
However I also now use ActiveHDL and that controls the command line of both
LS (for synthesis) and Q2 for P&R OK.
I would say I wasn't at all keen on trying the new LS until I hear some good
reports.
Take a look at the problems left in. If they can't get library (LPM etc) to
work correctly in a release something needs fixing. LPM integration is such
a basic requirement of an Altera tool IMHO.
>From the LS readme file:
5. The LeonardoSpectrum-Altera Software Version 2002a.14 will not recognize
LPM instantiations in HDL as black boxes. This may result in one or more
of the following types of Error messages :-
=======================================================================
Error : output port/net "<net>" of instance "<instance>" of cell
<blackbox> has no driver.
WARNING: output port is not driven -- <port_name>
=======================================================================
<followed by a script fix>
Reports on Q2 v2 and LS2002 gratefully areceived.
Paul
PS did you install Q2 or LS into a path containing spaces? Leo doesn't
appear to be finding a system library (flex10e.syn)
"Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in
message news:a5v55k$b9v$1@newsreader.mailgate.org...
> I will like to know if there is anyone who got NativeLink
> feature of Quartus II 2.0 to work with LeonardoSpectrum-Altera.
> I have been trying that with Quartus II 1.1 Web Edition yesterday, and
> Quartus II 2.0 Web Edition today, but I never got it to work.
> When I tried the NativeLink feature of Quartus II 1.1 WE with LS-Altera
> Level 1 2001_28a, the Quartus II 1.1 WE simply hang up (Quartus_cmp.exe
> caused a General Protection Fault when it tried to access MSVCRT.DLL or
> something like that.).
> So, I downloaded Quartus II 2.0 WE and LS-Altera Level 1 2002_014, and
> this time Quartus II was able to start LS-Altera, but LS-Altera wasn't
> able to synthesize my design.
> Here is the message I got on Quartus II's screen.
>
>
> ____________________________________________________________________
> Info: EDA tool information: Device is:
> Info: EDA tool information: EPF10K100EFC484-1
> Info: EDA tool information: Family is:
> Info: EDA tool information: FLEX10KE
> Info: LeonardoSpectrum software information: EPF10K100EFC484-1
> Info: LeonardoSpectrum software information: FLEX10KE
> Info: LeonardoSpectrum software information: spectrum
> ..\My_Design\My_Design.v ls_work\My_Design_Top.edf -product=ls1
> -tar=flex10ke
> Info: LeonardoSpectrum software information: LeonardoSpectrum Level 1 -
> v2002a.14_OEM_Altera (Release OEM Altera Candidate, compiled Jan 22 2002
> at 02:33:16) Info: LeonardoSpectrum software information: Copyright
> 1990-2001 Exemplar Logic, Inc. All rights reserved. Info:
> LeonardoSpectrum software information: Info: LeonardoSpectrum software
> information: Checking Security ... Info: LeonardoSpectrum software
> information: Messages will be logged to file
> 'C:/My_Design/ls_work/My_Design_Top.log'... Info: LeonardoSpectrum
> software information: -- Info: LeonardoSpectrum software information: --
> Welcome to LeonardoSpectrum Level 1 Info: LeonardoSpectrum software
> information: -- Run Started On Sun Mar 03 17:31:17 Central Daylight Time
> 2002 Info: LeonardoSpectrum software information: -- Info:
> LeonardoSpectrum software information: -- Reading target technology
> flex10ke Error: LeonardoSpectrum software error: Error, cannot find file
> 'flex10ke.syn' Info: LeonardoSpectrum software information: Warning:
> Can't analyze file -- file C:\My_Design\ls_work\My_Design_Top.edf is
> missing
> Info: Found 0 design units and 0 entities in source file
> C:\My_Design\ls_work\My_Design_Top.edf
> Error: Node instance instantiates undefined entity My_Design_Top
> Error: Design My_Design_Top: Full compilation was unsuccessful. 2
> errors, 1 warning.
> ____________________________________________________________________
>
>
>
> Note that I changed the file names of the log file for privacy reasons.
> What is going on, and am I doing something wrong?
> I already set PATH and EXEMPLER environmental variables to point to the
> directory LS-Altera resides.
> When I create a project in LS-Altera, LS-Altera handles the synthesis
> fine, so I am puzzled why the thing doesn't work from Quartus II 2.0.
> Is Altera releasing their products without adequate testing?
> From my past bad experiences with Altera tools, I suspect that might
> have just happened.
> I am currently running both software on a Windows 98SE PC.
Article: 40263This is a multi-part message in MIME format. --------------BB3BD880B53329CB4BDD0192 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Antonio, Attach a TNM to the Clk_enable net, and then apply it to the gouping. The TNM will be forward propagated to all the synchronous elements attached to the net: NET clk_enable TNM = clk_en; TIMESPEC TS_multi_cycle = FROM clk_en TO clk_en 30; Dave Antonio wrote: > In my circuit there's a shift register with clk_enable and clk ports > so if clk is 10ns period 50% duty Cycle while clk_enable is on just for (10*3)ns > I would want to know how to set the constrain in this case. > > Attached there's the code of the shift register : > > library IEEE; > use IEEE.std_logic_1164.all; > > entity shift_reg is > port ( > clk : in std_logic ; > clk_en : in std_logic ; > reset : in std_logic ; > in_reg : in std_logic ; > out_ffd_1 : out std_logic ; > out_ffd_2 : out std_logic ; > out_ffd_3 : out std_logic ; > out_ffd_4 : out std_logic ; > out_ffd_5 : out std_logic ; > out_ffd_6 : out std_logic > ); > end entity; > > architecture shift_reg_arch of shift_reg is > signal temp_out_reg : std_logic_vector(5 downto 0); > begin > > process(clk, clk_en, reset) > begin > if reset = '1' then > temp_out_reg <= "000000"; > elsif rising_edge(clk) then > if clk_en = '1' then > temp_out_reg <= in_reg & temp_out_reg(5 downto 1); > end if; > end if; > end process; > > out_ffd_6 <= temp_out_reg(0); > out_ffd_5 <= temp_out_reg(1); > out_ffd_4 <= temp_out_reg(2); > out_ffd_3 <= temp_out_reg(3); > out_ffd_2 <= temp_out_reg(4); > out_ffd_1 <= temp_out_reg(5); > > end architecture;Article: 40264
This is a multi-part message in MIME format. --------------F2E6F3346A171357EEED03A8 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Antonio, These figures do not take into account where the signals are proagating from. You may want to include PCB time of flight (dependant on trace length ~150ps/in to 200ps/in depending on material loading etc.), and the tCO of the source of the signal. A fair comment would be - I've registered all my IO, so do I really need to constrain these paths as they are fixed into the IOB's. That is up to you. If they are registered then yes they are fixed for Inputs, and the Outputs can be modified somewhat (drive strength/slew etc) Dave Antonio wrote: > Other simple (..not for me) questions : > > 1) Is a good Idea to attach a TIG to a reset net ?? > 2) In my QPSK modulator there are two data input each of 1 bit, the > maximum input data rate could be 55Mbps , until now I've not setted a > pad to setup constrain but I'm asking if it is truly necessary, if I'm > not in error this have to be (1/55e6) = 18ns . > > And this have to be done also for the output with a clock to pad > constrain of (1/165e6) = 6.06ns > > Does this is right ?? > > AntonioArticle: 40265
David, you easily can reproduce the performance advantage over Virtex 2 by just installing Quartus 2 software from Altera together with an appropriate sybthesis tool (both, Synplicity's Synplify and Exemplar) and run your designs with Stratix selecetd as target device family. P&R already supports Stratix devices. Timing report is always some kind of estimation. Just remember when Xilinx introduces Service Pack 8 for its M3.1 software. It showed up that timing estimates were a lot worse than previously reported results. Any questions on that? regards PhilArticle: 40266
Altera says that QuartusII 2.0 working with Synplify 7.1 ,but I can only found ver 7.03 on SYNPLICITY website for download.Article: 40267
Salve, volevo farle una domanda a proposito del software ISE4.1. E' possibile che le net tra un foglio ed un'altro di un progetto non si possano collegare tra loro se non utilizzando uno schematico di livello superiore che connetta le net di fogli diversi? Quetsa cosa era possibile nel vecchio Foundatin Series 3.1 !!! La ringrazio anticipatamente per l'attenzione.Article: 40268
I'm using Atmel Figaro 7.5, Leonardo Spectrum level 2 and VHDLSimili for simulation. I have problems with post layout simulation. I simulated the circuit using the same script for rtl description and for post layout netlist. Simulation results for rtl code are ok but for post-layout nestlist all output signals got 'X'. All input signal are initialized in test bench. I'm using At6002 parts. Anyone have any suggestions? Thanks in advance JarekArticle: 40269
Hi all, I got a doubt and hope this group clears my doubt.I have a core which is to be implemented in a virtex fpga.In the core I have three cores which offer at different frequencies.so,when I try to implement in the fpga,I will have asynchronous domains.Is it allowed?as for my knowledge,all blocks should operate at the same frequency(??).please clear my doubt. Regards - satyaArticle: 40270
I'm looking for some general text on fpga, nothing specific but that explains what a FPGA is, a bit of history, etc. Sort of "what is an FPGA" faq. Thanks in advance.Article: 40271
Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3C82C4A4.47B4@designtools.co.nz>... > Ray Morales wrote: > > > > for some odd reason, about 2% of writes that set xcs or rst are > > failing (i.e. wrong value is set). reads seem to be quite stable > > [always give the right value]. > > Is the 8051 clocked from the 24.576MHz, or in another clock domain ? > > Try and qualify on the leading edge of WRITE, rather than LOW write. > 8051 is clocked from another clock domain entirely. What do you mean 'qualify'? Thanks.Article: 40272
Just to let you all know that I have solved all of the problems. I am now using an asynchronous FIFO with independant write and read clocks courtesy of Xilinx Core Generator. Process B no longer exists and my DAC process just takes data directly from the FIFO when it needs it and process A just does what it always did and keeps the FIFO full as much as possible. I have no need to do clock synchronisation using this method and everything is more stable since I have no ACK signals crossing clock domains - the FIFO is the interface. Thanks for all of your help - each suggestion was useful in helping me solve the problem. Cheers, Ken "Ken Mac" <aeu96186@yahoo.co.uk> wrote in message news:a5lbej$92a$1@dennis.cc.strath.ac.uk... > > Hello, > > I am using ISE 4.1 SP3 with a Spartan-II. > > My VHDL design has 3 processes: > > Process A: Runs at 33MHz to fill a 16 location FIFO with 8-bit data > samples and then keep it full. > Process B: Runs at 33MHz to take data from the FIFO when told to and > supply it to process C via a register. > Process C: Runs at 425kHz and sends FIFO 8-bit data samples to a DAC > bit-serially then asks process B for next piece of data. > > Process A is fed with data via a Visual C++ app (the Spartan-II is mounted > on a PCI board) which is synchronised with the FPGA using an interrupt pin > that the FPGA can assert and the C++ can read. > > I have used this system for many designs with no trouble (none of them had > multiple clock domains however). The problem here is that the design is > getting stuck in state for no apparent reason! (i.e. the C++ hangs waiting > for the interrupt pin!). > > The system works for a random number of samples (between 28 and 33 it seems) > and then gets stuck in state. This is very strange because it means that my > protocols do work. > > The weird thing is that I put a piece of debug code in another state to send > a signal out to a pin to probe, I ran the flow again to get a bitstream and > the system ran perfectly for all 75001 samples I am using! The debug code > was "Debug <= '1'". > > Then I enabled clock DLLs using the BUFGDLL component and it hangs again! > > Previously, I had it working perfectly using the clock DLLs but without a > FIFO (i.e. 1 sample at a time from C++ to FPGA to DAC) but I got some > stutters hence I introduced the FIFO. > > In that design I also had hanging problems but after I rejigged my protocol > in my VHDL state machines it worked perfectly. > > It seems that seemingly random changes of VHDL make or break the system. I > guess it must be to do with my 2 different clock rates but that is the way > it has to be. > > I am at a loss - anyone any ideas? > > Thanks for your time, > > Ken > > >Article: 40273
The "performance advantage" is going to be highly dependent on your design implementation.
Phil wrote:
> David,
>
> you easily can reproduce the performance advantage over Virtex 2 by just installing Quartus 2 software from Altera together with an appropriate sybthesis tool (both, Synplicity's Synplify and Exemplar) and run your designs with Stratix selecetd as target device family. P&R already supports Stratix devices. Timing report is always some kind of estimation. Just remember when Xilinx introduces Service Pack 8 for its M3.1 software. It showed up that timing estimates were a lot worse than previously reported results.
>
> Any questions on that?
>
> regards
>
> Phil
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 40274Nicholas, All you see is the top metalization, which is the redistribution layer for the flip chip solder bumps .... not very interesting at all. Austin Nicholas Weaver wrote: > Does anyone have a nice hi-res photo of a Xilinx Virtex CLB or general > die? Google has failed me. > > thanks. > > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu
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