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John_H wrote: > Now that you know some of the timing numbers are worse you can skip downloading the > update and your parts won't run slower! > > ( ? ) > That's it. Head planted firmly in the sand, butt exposed high in the air for a good kicking! Missing from first post: ISO :-) joke symbol. But there was a serious point behind it In da olden days it used was possible to be selective & only go for the timing updates but now I have to have it all at once. So I tend to be quite slow about incorporating service packs, quite often only do it when I trip over a bug that's been fixed (got burned over the 2.1i SP2-SP3 DLL cock-up) => my timing butt is more exposed than it should be.Article: 39426
I'm going to make some assumptions because I'm not sure if I understand your description, correct me if I'm wrong. Like you suggested, go ahead and run your internal processor at twice the external interface. Enable the data capture and data launch flops on every other clock. Clock every flip/flop in your design on the higher 2X clock. Don't try to have a 66MHz mem interface and 100MHz internal clock. Maintain that 2/1 ratio. Run the memory at 50 and the processor at 100 or run the memory at 66, and run the processor at 133MHz. Your life will be much easier. Hope this help, Regards Richard Meester <rme@quest-innovations.com> wrote in message news:<3C63F9C2.6CBF3BE7@quest-innovations.com>... > Hi All, > > I have some problems finding a good design practice for a bus-interface. > > We have a processor running internally at 100Mhz, and externally at > 50Mhz (2 internal bus cycles used for 1 complete external bus cycle). > Now the addresses are set, the cs lines are set, the re_n and we_n > signals are set and the data is set or read. I know all the timing > variables on these lines. > > Now i need to design a bus interface, but i want the internal clock to > run at least at 66 Mhz because i need to access ram at this speed and > want to keep the internal clock speeds at the same speed. > > Now how can i best trigger my internal signals, the we_n line goes > active low after 8 nsecs of valid data, should i use this signal and > feed it into a fflop to trigger on, or should i let the flop trigger at > the internal clock speed and detect that the line has changed state and > take action from there, or should i make the desing completely > combinatorial? > > Thanks in advance, > > RichardArticle: 39427
Any chance you have hardwired your reset inactive? This would explain the registers not changing state, and the synthesizer optimizing away your flops. Regards. shengyu_shen@hotmail.com (ssy) wrote in message news:<f4a5f64f.0202080707.513bc3f8@posting.google.com>... > Hi > I am using synplify pro 6.2.4 to synthesis, after synthesis, I use the > .vm file and the quartus II 1.1 library file to perform post syn > simulation in modelsim, > > but it seems that all register do not change even the simulation time > progress forward for a long time. > > it seems that the external clock can not enter the design > > why? > > BTW : I uncheck the "disable io insertion" option in synplify,I think > this may be the cause. > > and about the warning, there are following warning > > 1 some output pin have undriven bit > 2 many many many register have been removed or stuck at a fix value > > amd about the replace, in the synthesis , the syntheser have optimize > across the border of module,how to deal with this > > kayrock66@yahoo.com (Jay) wrote in message news:<d049f91b.0202061722.56bb6195@posting.google.com>... > > If you are new at using HDL's to design ciruits, it is very possible > > you have coded something that will not behave the same in gates (post > > synthesis) as it does in RTL form. Often time the sythesizer will > > warn you of these coding style issues, but not always. You should run > > a post syth, pre P&R simulation against you existing test-bench and > > see if it flys. If it doesn't you, among other techniques, you can > > replace on by one, each module with its RTL version until you make it > > work. > > > > Good luck to you! > > > > shengyu_shen@hotmail.com (ssy) wrote in message news:<f4a5f64f.0201310054.234aa10f@posting.google.com>... > > > Hi every one > > > > > > I am using sopc board from altera, it hold an APEX20k400E, I am using > > > synplicity 6.2.4 to synthesis and then use quartus II 1.1 to P&R, > > > > > > my design is an cpu, the cpu hold one cpu core(design by me), an > > > interconnect network(design by other), and some slave device(design by > > > my team member) > > > > > > the cpu core have two master port to fetch instruction and data > > > > > > the interconnect network have 8 master and 16 slave, any unuse port's > > > output pin will not connect and input pin will assign 0, > > > > > > I run pre syn rtl simulation, all ok,but after burn on the board, it > > > is error, > > > > > > I want to know possible cause of synthesis/simulation mismatch.Article: 39428
All the stuff the other guys are posting about meta-stability applies in the general case, but if your 2 clocks are synchronized (e.g. derived from the same source, as I suggested in the other post) then you usually would not do this. Regards Richard Meester <rme@quest-innovations.com> wrote in message news:<3C628E7A.94695F98@quest-innovations.com>... > Hello All, > > Why do you typically use 2 ffflops on a source signal to synchronize > between 2 clocks with 2 different speeds. Has this to do with glitches? > > Could someone perhaps point me to a website which has good information > about this topic. > > > Thanks, > > RichardArticle: 39429
I'm with you there. The major revisions are usually the ones that really bite you. Been
nailed there a couple of times. I also don't like switching horses midstream, so I
usually put off making a change to major releases until a convenient time in my schedule.
Now, since you can't get a timing update for 3.3sp8, we are forced to do all the things I
don't like, or as you said leave out butt hanging out in the breeze. Personally, I don't
care for the head in the sand and butt in the air trick, someone's liable to mistake it
for a bicycle rack or something (not to mention the sunburn). As a result, I have both on
my system now until I finish up the old projects (I've got a couple that are either
Spartan or QPRO that don't look like they are hit).
Rick Filipkiewicz wrote:
> John_H wrote:
>
> > Now that you know some of the timing numbers are worse you can skip downloading the
> > update and your parts won't run slower!
> >
> > ( ? )
> >
>
> That's it. Head planted firmly in the sand, butt exposed high in the air for a good
> kicking!
>
> Missing from first post: ISO :-) joke symbol.
>
> But there was a serious point behind it In da olden days it used was possible to be
> selective & only go for the timing updates but now I have to have it all at once. So
> I tend to be quite slow about incorporating service packs, quite often only do it when
> I trip over a bug that's been fixed (got burned over the 2.1i SP2-SP3 DLL cock-up) =>
> my timing butt is more exposed than it should be.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39430
True, but be careful going between clock domains from different DLL outputs in the Xilinx parts. Ideally the
various clock outputs have very little skew, however when you take into account unequal clock net loading, normal
variations in the DLL outputs and jitter on the clock input you can easily get skews of several hundred ps, enough
to cause a problem in some cases where the prop delay between registers at the clock domain crossing is small.
Input clock jitter appears to be the biggest culprit. Even if your input clock is perfect you can get substantial
jitter inside due to modulation of the input threshold voltages. To minimize that, don't use single ended outputs
on the same bank as the clock input, and preferably use only differential signals for the clock and on I/O on the
clock bank. To keep things safe, I am very careful of how i treat signals that cross even related clock domains.
Jay wrote:
> All the stuff the other guys are posting about meta-stability applies
> in the general case, but if your 2 clocks are synchronized (e.g.
> derived from the same source, as I suggested in the other post) then
> you usually would not do this.
>
> Regards
>
> Richard Meester <rme@quest-innovations.com> wrote in message news:<3C628E7A.94695F98@quest-innovations.com>...
> > Hello All,
> >
> > Why do you typically use 2 ffflops on a source signal to synchronize
> > between 2 clocks with 2 different speeds. Has this to do with glitches?
> >
> > Could someone perhaps point me to a website which has good information
> > about this topic.
> >
> >
> > Thanks,
> >
> > Richard
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39431
strut911 wrote:
>
> yes,
> you have all discovered my secret. i wish to sell solutions manuals
> over the internet, especially the manuals to complex graduate
> algorithmic books.
[wonderful sarcasm deleted]
I hear you, man, and I would appreciate you sharing what you find with
me. I've been around this block too and came up empty handed.
Bob
--
"Things should be described as simply as possible, but no simpler."
A. Einstein
////////////////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
To contribute your unused processor cycles to the fight against cancer:
http://www.intel.com/cure
\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\///////////////////////////////////////
Article: 39433
Hi Jay,
Thanks for the response,
Jay wrote:
> I'm going to make some assumptions because I'm not sure if I
> understand your description, correct me if I'm wrong.
>
> Like you suggested, go ahead and run your internal processor at twice
> the external interface. Enable the data capture and data launch flops
> on every other clock. Clock every flip/flop in your design on the
> higher 2X clock.
What do you meen by every other clock, clock the lines, and than wait
one clock, and then clock again for the next complete cycle?
Don't i have a metastability problem with the asynchronous read/write/cs
lines
the problem is that the signal below is i.e. the r/w signal. it is
asynchronous. if i sample this at twice the frequency i will at
somepoint get the correct valie that i need to trigger on.
---\________/------
^ ^ samples at one of these points at 100 Mhz.
^ DATA must be stable at this point
However i need to have the data stable before the rising edge of this
signal, which is one clock cycle wide @ 100 Mhz. so i have one clock
cycle to put the data on the bus.
I see how to design this, but i am worried about metastability on the
asynchronous lines. If i need to take care of this i need to add 2 flops
behind it, and after that start making the data available. Overall this
will take me at least 3 clock cycles.
Richard
>
> Don't try to have a 66MHz mem interface and 100MHz internal clock.
> Maintain that 2/1 ratio. Run the memory at 50 and the processor at
> 100 or run the memory at 66, and run the processor at 133MHz. Your
> life will be much easier.
>
> Hope this help,
> Regards
> Richard Meester <rme@quest-innovations.com> wrote in message news:<3C63F9C2.6CBF3BE7@quest-innovations.com>...
>
>>Hi All,
>>
>>I have some problems finding a good design practice for a bus-interface.
>>
>>We have a processor running internally at 100Mhz, and externally at
>>50Mhz (2 internal bus cycles used for 1 complete external bus cycle).
>>Now the addresses are set, the cs lines are set, the re_n and we_n
>>signals are set and the data is set or read. I know all the timing
>>variables on these lines.
>>
>>Now i need to design a bus interface, but i want the internal clock to
>>run at least at 66 Mhz because i need to access ram at this speed and
>>want to keep the internal clock speeds at the same speed.
>>
>>Now how can i best trigger my internal signals, the we_n line goes
>>active low after 8 nsecs of valid data, should i use this signal and
>>feed it into a fflop to trigger on, or should i let the flop trigger at
>>the internal clock speed and detect that the line has changed state and
>>take action from there, or should i make the desing completely
>>combinatorial?
>>
>>Thanks in advance,
>>
>>Richard
>>
Article: 39434
Hi,
I've use Xilinx FPGA a few month, and use System Generator to program
the chip.
But I found that the SystemGen is not that convinience to design
something need looping
or interatively calculation.
Is there any other language beside System Generator to program the chip.
I am quite familiar with
Java programming, is JBits a good choice??(I know nothing about the LUT or
things inner the FPGA chip.)
Thanks!!
Terrence
Article: 39435On Fri, 08 Feb 2002 14:09:49 -0500, Jerry Avins <jya@ieee.org> wrote: (snipped) >> >> Telegraph lines!! Maybe I was right when I >> once posted that you knew Abraham Lincoln personally. >> >> [-Rick-] > >Not true! But had he he studied engineering instead of law, I might have >used some of his cast-off texts. I know how to build an Alexanderson >alternator to generate RF directly with a rotating machine (and I live >near the first major installation.) I used to be a whiz at tube design, >and there were no courses in logic design, let alone computers when I >graduated in 1962 (at age 30). I can design (or at least evaluate a >design well enough to avoid being sold garbage) power-station steam >turbines -- Keenen and Keyes' "Thermodynamic Properties of Steam" is on >my book shelf. I know a Worthington steam-operated boiler-return pump on >sight, and I can compound a DC generator any way that's called for. So >why not telegraph? At least I got as far as simplex connection to ride a >free telegraph line on top of a telephone pair, and simultaneous >east-west signaling on a single telegraph wire with a new-fangled >"duplex" connection. There's a lot of stuff in there that only seems >useless: it gives me shortcuts when thinking about new stuff. It's nice >to have learned to design commercial antenna towers, too (down to >figuring the rivet patterns), but that has been useful only privately. > >Jerry These are other examples of why I like to call you "Mr. Wizard". (I'll bet aren't many guys out there who remember Mr. Wizard.) [-Rick-]Article: 39436
On Sat, 09 Feb 2002 12:05:39 GMT, ricklyon@remove.onemain.com (Rick Lyons) wrote: >These are other examples of why I like to >call you "Mr. Wizard". (I'll bet aren't many guys >out there who remember Mr. Wizard.) Actually, I think one of the greatest things about Mr. Wizard was the string of parodies that has followed him over the years. Eric Jacobsen Minister of Algorithms, Intel Corp. My opinions may not be Intel's opinions. http://www.ericjacobsen.orgArticle: 39437
Eric Jacobsen wrote: > > On Sat, 09 Feb 2002 12:05:39 GMT, ricklyon@remove.onemain.com (Rick > Lyons) wrote: > > >These are other examples of why I like to > >call you "Mr. Wizard". (I'll bet aren't many guys > >out there who remember Mr. Wizard.) > > Actually, I think one of the greatest things about Mr. Wizard was the > string of parodies that has followed him over the years. > > Eric Jacobsen > Minister of Algorithms, Intel Corp. > My opinions may not be Intel's opinions. > http://www.ericjacobsen.org He must have been after my time. The name rings only a very faint bell. (I got my first TV, a hand-me-down in need of repair, in 61.) Jerry -- Engineering is the art of making what you want from things you can get. -----------------------------------------------------------------------Article: 39438
Hi, gurus, I'm a Computer Architecture grad school teacher at a small college here in NH. I have a question about FPGA protoyping, if you bear with me for a minute or two, I'll eventually get to ask you a question. I have structured my course to be Verilog HDL centered: I teach my students enough HDL for them to be able to understand the main issues at a programming level, and I walk them through a number of code examples that implement different parts of a cpu, at least a a theoretical level. The course is given in a lab-like class with one PC per student, so, we have a lot of flexibility as far as what the kinds of activities we do in class. We use Synapticad's Verilogger Pro to compile and simulate our toy code, and we use Ciletti's book as our HDL reference. Students go through a few toy assignments that implement registers, simple state machines, and other components, and simulate them. I then give them a piece of code I wrote that implements a very simple RISC pipeline. Once they spend the time understanding it, I ask them to do things such as generate errors in the pipeline by pushing the "wrong" sequence of instructions through it, and if there's time, to add code to the pipeline to implement bypass or renaming and thus solve the problem. I also wrote a very simple assembler for a mock instruction set, so that they can write assembler programs, pass them trough the assembler, which generates absolute machine code files that are read by the pipeline HDL code. This is all fine and dandy, and works beautifully at simulation level. What I want to do now is, next course I would like to have some FPGA prototyping system that I can carry to class, hook to my machine's parallel port, and show it actually working in hardware, as opposed to just see it through Verilog simulations. If this works, I might get myself in a position to get a few of those sets to the students themselves, which would make the course yet better. So, my question is this. Ciletti's book comes with the Xilinx Student Edition of their Foundation software. I want to take the plunge, and by myself some prototyping system, so that I can graduate from doing things at simulation level to having a piece of Verilog HDL that actually works on the prototyping hardware. How should I proceed ? Is the XSE enough, or do I need something else ? What kind of prototyping hardware do I get, if what I want is to learn fast and have something that works but not necessarily at production level ? I'm an EE myself and I can write code in many languages, but I have no direct exposure to FPGAs. Help ? Alberto.Article: 39439
Alberto Moreira wrote: > Hi, gurus, > > I'm a Computer Architecture grad school teacher at a small college > here in NH. I have a question about FPGA protoyping, if you bear with > me for a minute or two, I'll eventually get to ask you a question. > > I have structured my course to be Verilog HDL centered: I teach my > students enough HDL for them to be able to understand the main issues > at a programming level, and I walk them through a number of code > examples that implement different parts of a cpu, at least a a > theoretical level. > > The course is given in a lab-like class with one PC per student, so, > we have a lot of flexibility as far as what the kinds of activities we > do in class. > > We use Synapticad's Verilogger Pro to compile and simulate our toy > code, and we use Ciletti's book as our HDL reference. Students go > through a few toy assignments that implement registers, simple state > machines, and other components, and simulate them. I then give them a > piece of code I wrote that implements a very simple RISC pipeline. > Once they spend the time understanding it, I ask them to do things > such as generate errors in the pipeline by pushing the "wrong" > sequence of instructions through it, and if there's time, to add code > to the pipeline to implement bypass or renaming and thus solve the > problem. I also wrote a very simple assembler for a mock instruction > set, so that they can write assembler programs, pass them trough the > assembler, which generates absolute machine code files that are read > by the pipeline HDL code. > > This is all fine and dandy, and works beautifully at simulation level. > What I want to do now is, next course I would like to have some FPGA > prototyping system that I can carry to class, hook to my machine's > parallel port, and show it actually working in hardware, as opposed to > just see it through Verilog simulations. If this works, I might get > myself in a position to get a few of those sets to the students > themselves, which would make the course yet better. > > So, my question is this. Ciletti's book comes with the Xilinx Student > Edition of their Foundation software. I want to take the plunge, and > by myself some prototyping system, so that I can graduate from doing > things at simulation level to having a piece of Verilog HDL that > actually works on the prototyping hardware. How should I proceed ? Is > the XSE enough, or do I need something else ? What kind of prototyping > hardware do I get, if what I want is to learn fast and have something > that works but not necessarily at production level ? I'm an EE myself > and I can write code in many languages, but I have no direct exposure > to FPGAs. > > Help ? Alberto: You should use google to do a search in the comp.arch.embedded newsgroup using the search terms "FPGA starter kit". I just did this and got 70 hits. This will give you an idea of the options you have in this area. You can also look at the list of FPGA board manufacturers at www.optimagic.com. That's my objective answer. My subjective answer is that the XS40 Boards from XESS Corp were made to meet the needs of instructors like you. They are inexpensive, interface to the parallel port, have online tutorials written around XSE-2.1i that you can adapt to your class, etc. You can look at these boards by going to http://www.xess.com. These boards use the older Xilinx XC4000XL FPGAs so you are not going to get the highest denisty or fastest speeds. That may not make a difference in a classroom setting. There are also a lot of boards that use the newer SpartanII FPGAs (including our XSA-100 Board). You should be careful when considering these since XSE-2.1i doesn't support some of the SpartanII packages. You should also consider your use of XSE-2.1i software in the future. This software will be discontinued within a few months since Synopsis and Xilinx have decided that the FPGA Express synthesizer will no longer be supported in the Student Edition. It looks like the longer-term solution for students will be the WebPACK software that you can download freely from www.xilinx.com. WebPACK supports all the SpartanII FPGAs so this may be a reason to look at SpartanII boards while planning for the future. -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||Article: 39440
Hi!
I am searching the programs to convert an EDIF file to a .BIT file, which
can be downloaded into a Xilinx FPGA.
I found out that these tools are called ngdbuild, par, ... and are part of
the Xilinx Foundation/Alliance/WebPack.
I downloaded the WebPack, but it doesn't contain the ability to make a
.BIT file for the Spartan XCS10 FPGA which I have on an evaluation board.
Where can I get only the command line tools to convert an EDIF file to a
.BIT file for _all_ Xilinx devices?
I read the very long thread about these tools as open source two months
ago. I am a Linux user, so I'd like to have them open source too. But that
is not necessary. If I can get the executabels would be enough. If they
are windows-executables, I can use Wine, so this isn't a problem, too.
Question to the @xilinx.com readers: Could Xilinx please release at least
these programs for free download? Without the nice graphical frontends,
only the command line tools. And without the source code. Only the
executables for some operating systems.
All other tools I already have (VHDL/Verilog Compiler, downloader to the
FPGA).
Thanks
Hansi
--
Johann Glaser <Johann.Glaser@gmx.at>
Vienna University of Technology
Electrical Engineering
http://stud3.tuwien.ac.at/~e9825761/index.html
Article: 39441Jerry Avins <jya@ieee.org> wrote: > Eric Jacobsen wrote: > > > > On Sat, 09 Feb 2002 12:05:39 GMT, ricklyon@remove.onemain.com (Rick > > Lyons) wrote: > > > > >These are other examples of why I like to > > >call you "Mr. Wizard". (I'll bet aren't many guys > > >out there who remember Mr. Wizard.) > > > > Actually, I think one of the greatest things about Mr. Wizard was the > > string of parodies that has followed him over the years. > > > > Eric Jacobsen > > Minister of Algorithms, Intel Corp. > > My opinions may not be Intel's opinions. > > http://www.ericjacobsen.org > > He must have been after my time. The name rings only a very faint bell. > (I got my first TV, a hand-me-down in need of repair, in 61.) > > Jerry You had to Watch him. Adrian. -- Dr A.P. Whichello Phone: +61 2 6201 2431 Electronics & Telecommunications Engineering Fax: +61 2 6201 5041 University of Canberra Email: adrianw@ise.canberra.edu.au Australia WWW: http://www.ee.usyd.edu.au/~adrianw "I wish to God these calculations had been executed by Steam!" C.BabbageArticle: 39442
Hi again, So the question became more specific. What remaines yet – where (in what ModelSim library) I may find analogs for GND/VCC I receive from Leonardo making .v/.sdf pair? Another option I found in Leo is to replace them by supply0/1 correspondingly, but ModelSim clarifies as error such construction as : supply1 (was VCC) nx709_rename (.Y (nx709)) ; Thanks in advance, Igor Peker vnpeker@netvision.net.il (Igor Peker) wrote in message news:<9a4e9472.0202061306.4b8929a7@posting.google.com>... > Hi, > > What libbaries should I reference to make preliminary timing > simulation by ModelSim just after optimization and generating SDF file > by Leonardo - not after Altera P&R? What are extension of them and > where to search - either in ModelSim or Leo folders? > > Thanks in advance, > Igor PekerArticle: 39443
"John McCluskey" wrote > This is an interesting question, since ISE 4.2 is now working it's way > through the manufacturing channel. The following excerpt is from the > "What's New in ISE 4.2" file on the release CD. <snip> > For syntax examples, see Xilinx Answer Record #13166. How would we do that?Article: 39444
Serial port driver is inherent to WinNT/2K.
To access serial port from a user program you should open COM1 as a file.
Certain control functions are necessary to set up this port properly.
Here is a C++ code sample:
hComm = CreateFile(\\\\.\\COM1,
GENERIC_READ | GENERIC_WRITE,
0, // exclusive access
NULL, // no security attrs
OPEN_EXISTING,
FILE_ATTRIBUTE_NORMAL,
NULL);
if (hComm == INVALID_HANDLE_VALUE)
{
SoftFault("*ERROR*-Can not open communication port %s. ERR=%u\r\n",
nam, GetLastError());
}
COMMPROP cprop; // communications properties structure
if (!GetCommProperties(hComm, &cprop))
{
SoftFault("*ERROR*-Can not get properties for communication port %s.
ERR=%u\r\n",
nam, GetLastError());
}
Regards,
Alex Sherstuk
"Theron Hicks" <hicksthe@egr.msu.edu> wrote in message
news:3C6414DE.C5192D11@egr.msu.edu...
> Does any one have serial drivers for WinNT/2K? I need to get a driver,
etc.
> to allow me to talk to an FPGA based device via the com ports in an NT
> machine.
>
> Dave Vanden Bout wrote:
>
> > Rick Filipkiewicz wrote:
> >
> > > I'm after an WinNT/2K Parallel port driver so I can realise a Flash
> > > based FPGA config data store.
> > >
> > > I'd prefer free or share ware but a modest cost wouldn't be out of the
> > > question. Could someone point me in the right direction ?
> >
> > One package is the DriverLINX software and driver. Check for it at
> > www.sstnet.com. We also have an installation file for it (port95nt.exe)
> > at
> > http://www.xess.com/ho07000.html.
> >
> > Another option is UNIIO. The source for this is completely available so
> > you
> > can compile the parts you need. Look for it at www.bbdsoft.com.
> >
> > --
> > || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 ||
> > || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 ||
> > || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||
>
Article: 39445This is a multi-part message in MIME format. ------=_NextPart_000_003B_01C1B1D1.9EC95380 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi, I would make sure the gate level simulations pass without backannotating the SDF. This will assure you your synthesis an P&R are behaving as you expect. Then try backannotaion without glitch generation. If that passes, turn on glitch generation. Good luck "niv" <niv@ntlworld.com> wrote in message = news:BWx48.27902$ka7.4621195@news6-win.server.ntlworld.com... Hi, anyone help with this? Got a design in RTL plus some Xilinx coregen form Xilinx 3.1iSP4. RTL simulates just fine. Done synth. and PAR. BUT, the PAR was Xilinx 3.3iSP8. Now trying to do post PAR simulation. It fails fairly dismally. Should I point my simprim library mapping at the compiled simprim = library that is compiled as follows: Option 1. Xilinx simprim 3.1i compiled by Modelsim 5.5b Option 3. Xilinx simprim 3.3i compiled by Modelsim 5.5b Option 1. Xilinx simprim 3.3i compiled by Modelsim 5.5d I should add that we are now using MS5.d for all sims. I should that then when an older model was simulated with Xilinx 3.1i = and MS5.5b used everywhere, then the post PAR sim worked OK. TIA, Niv.Article: 39446
"Alberto Moreira" <junkmail@moreira.mv.com> schrieb im Newsbeitrag news:3c68636f.12626205@news.mv.net... > and I can write code in many languages, but I have no direct exposure > to FPGAs. www.burched.com www.nuhorizons.com www.insight-electronics.com www.altera.com For Xilinx FPGAs, I would not go for old stuff like XC4000 or Spartan, go for Spartan-II/Spartan-IIE or Virtex-E. -- MfG FalkArticle: 39447
Johann Glaser wrote: > Hi! > > I am searching the programs to convert an EDIF file to a .BIT file, which > can be downloaded into a Xilinx FPGA. > > I found out that these tools are called ngdbuild, par, ... and are part of > the Xilinx Foundation/Alliance/WebPack. > > I downloaded the WebPack, but it doesn't contain the ability to make a > .BIT file for the Spartan XCS10 FPGA which I have on an evaluation board. > > Where can I get only the command line tools to convert an EDIF file to a > .BIT file for _all_ Xilinx devices? > > I read the very long thread about these tools as open source two months > ago. I am a Linux user, so I'd like to have them open source too. But that > is not necessary. If I can get the executabels would be enough. If they > are windows-executables, I can use Wine, so this isn't a problem, too. > > Question to the @xilinx.com readers: Could Xilinx please release at least > these programs for free download? Without the nice graphical frontends, > only the command line tools. And without the source code. Only the > executables for some operating systems. > > All other tools I already have (VHDL/Verilog Compiler, downloader to the > FPGA). > > Thanks > Hansi > > -- > Johann Glaser <Johann.Glaser@gmx.at> > Vienna University of Technology > Electrical Engineering > http://stud3.tuwien.ac.at/~e9825761/index.html I'm afraid you have the wrong end of the stick here. There is no utility the `converts' an EDIF file to a .bit file. By ``VHDL/Verilog Compiler'' I assume you mean a synthesis tool ? If so which one ? Form then on the basic process is, roughly: o NGDBUILD takes in the EDIF(s) and produces a .ngd (= Native Generic Database). This is where you specify the Xilinx device family. Since you are using an eval board with fixed pinout you will need to specifiy this either here in a UCF file or at the next stage via a PCF. o MAP takes in the .ngd and allocates your logic to LUTs., assigns FFs to IOB cells if required, etc. and produces a .ncd file (= Native Circuit Database) but this has no placement or routing information. Here you specify the actual device you're using. o PAR takes the MAP output and does placement & routing, giving now a P&R'ed .ncd. Unless you have done it by hand PAR will auto-allocate external pins for your IOs. o BITGEN takes the post PAR .ncd and produces a .bit file. Once you've understood it its pretty easy to set up a makefile. You can get the Xilinx free tools by downloading ``WebPACK'' from their site but, as you surmise, they are Windows tools. For the command line descriptions you'll have to download some of the manuals separately, they're not part of the WebPACK package. The 2 `Bibles' are the ``Development System Reference Guide'' and the ``Libraries Guide''.Article: 39448
Hi Rick! Thanks for you excellent description of the design flow. It is now much clearer for me. I think I didn't depict my problem exact enough. I need _these_ tools, you described. NGDBUILT, MAP, PAR, BITGEN. 1) WebPack only offers them for SpartanII, I need them for Spartan (my Device is XCS10). 2) I'd like to have them for linux. But windows executabes (.exe-files) are good enough for me, because I can use Wine (the windows emulator). 3) These tools come from the unix field. They have been developed in some kind of Unix (i think Solaris or HP-UX). It shouldn't be very complicated to compile these command line tools for Linux. But this is optional. 4) I'd like to have only these tools and the necessary libraries and files released for free by Xilinx. Without sources, with the same kind of support they offer for the WebPack (support.xilinx.com). And without the colorful GUI programs. Bye HansiArticle: 39449
"Johann Glaser" <Johann.Glaser@gmx.at> schrieb im Newsbeitrag news:a45vet$1btfvn$1@ID-115042.news.dfncis.de... > I think I didn't depict my problem exact enough. I need _these_ tools, you > described. NGDBUILT, MAP, PAR, BITGEN. > > 1) WebPack only offers them for SpartanII, I need them for Spartan (my > Device is XCS10). Not available in WEBPACK. You have to go for commecial software, maybe the student edition of foundation suports Spartan. > 2) I'd like to have them for linux. But windows executabes (.exe-files) > are good enough for me, because I can use Wine (the windows emulator). No native windos version available yet. -- MfG Falk
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