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I am not sure what you are looking for. Normally to use a JTAG emulator, you just need to make sure you have a JTAG connector on your target board and use the vendor supplied emulator hardware and software. Boundary scan is used at board test to verify correct construction. This normally take some understand of the process in order to get the test vectors set up correctly and to understand the results. Not all JTAG devices support boundary scan, BTW. What exactly are you trying to accomplish? satya wrote: > > Hi all, > Can any body please point me to tutorials on JTAG Emulator.Please help > me by sharing "how-to's" on JTAG Emulator. > > Thanks and Regards, > - satya -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39126
hi in xillinx s/w there will be Integrated logic analyzer which can be helpful (it is called ILA) to you. please refer the help file regading that in xillinx s/w best of luck regards MPSArticle: 39127
Ulf Samuelsson wrote: > > > > > Btw Ulf, What's your idea about MSP430 series suggested by Jim > > Granville? > > > > > > Ulf is an Atmel representative, so it is not likely he will say much > > > about a TI product. He would be ill advised to say anything good for the > > > sake of his job and won't say anything bad for being thought of as > > > badmouthing the competition. :) Even if we ask... > > > > > Yes, I can, There are many applications where the MSP430 is excellent > including but not limited to "road-filling" in China. > Especially the larger packages are suitable :-) I wondered if you would rise to the occasion, or bait depending on how you look at it... ;) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39128
Peter Alfke wrote: > > rickman wrote: > > > > > Ulf is an Atmel representative, so it is not likely he will say much > > about a TI product. He would be ill advised to say anything good for the > > sake of his job and won't say anything bad for being thought of as > > badmouthing the competition. :) Even if we ask... > > I don't like this statement. I am a Xilinx employee, and I hope that my postings > are not considered Xilinx propaganda. I have even recommended Atmel EEPROMs ( > long ago ) when they offered a solution that Xilinx did not have then. > As employees, we have to be loyal to our employer; but as engineers, we also have > to be honest and forthright. Sometimes this can be tricky to combine, and one > solution is to shut up. > But, please, do not consider us spineless mercenaries or marketing puppets. > We are not! > And kudos to Xilinx management for never even having tried to censor me. > > Peter Alfke, Xilinx Applications You are entitled to your opinion, but I was making the point that a Sales Engineer or an FAE would not be very likey to recommend a competing part (which is what we are talking about in this case) even if it had clear advantages. If someone asked about reprogrammable boot PROMs that you don't sell, then of course you are not in competition on that product. But when was the last time you posted something good about an Altera FPGA? Do you really believe there is NOTHING good about them and that Xilinx parts are best for ALL applications? That was my point. I am not trying to say that anyone is dishonest in any way. But the practicality is that one just does not promote the competion over your own product even if they have advantages. My real point was that I am sure Ulf (like others) would like to say many negative things about the competition, but there is always the danger of appearing to be a politician campaigning for reelection. No one likes that. ;) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39129
Kevin Brace wrote: > > rickman wrote: > > So you need to get direct quotes from the disti's rather than count on > > web pricing. > > > > Who else is a distributor of Altera? > The only one I know is Arrow. > Regarding ACEX 1K, I sort of made a mistake when comparing > devices. > The $90 price tag I meant was actually for ACEX 1K100K-1 484-pin FPBGA > package, not ACEX 1K100K-1 208-pin PQFP package. > For ACEX 1K100K-1 208-pin PQFP package, the price is something like $58, > but that is twice as much compared to Spartan-II XC2S200-5CPQ208 (around > $25 to $30). > I suppose that if someone buys a lot, the distributor may give a volume > discount, but will the same discount apply when buying only one or two > for prototyping? The point is that Arrow has very high web pricing. If you call your local office (not the 800 number on the web site) I am sure you will get much better pricing. That is what I have found. Some distis work that way. They are using the web as a way to get into the low volume, high markup business. Meanwhile they sell with more modest profits through the local offices that call on the known accounts. Avnet does not have this dichotomy and so the web pricing is much more in line with reality (meaning what you will pay through the local office). > Like you, I never liked MAX+PLUS II, so I instead started off > with ISE WebPACK. > I must say that Quartus II 1.1 Web Edition is a major improvement over > MAX+PLUS II-BASELINE, but for some reason, ACEX 1K is not supported > in Quartus II 1.1 Web Edition, but some how MAX+PLUS II-BASELINE (free > version) supports it. > Since Quartus II 1.1 Web Edition supports FLEX 10KE, I don't see a > reason why Altera doesn't support ACEX 1K. I know about the 1k parts being in the paid QuartusII and not the free QuartusII. That may be due to the fact that the free tool is a version behind the paid version, I don't know. But it is a PITA. All of the 10K parts as well as the 1K parts which are very similar started in MAX+PlusII. They migrated the higher volume parts to Quartus this past summer. The 1K and 10KE parts are now in QuartusII (paid) but the 10KA parts did not make it across... Go figure. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39130
"Elizabeth D. Rather" wrote: > The CD that comes with the FET also includes information about the > SwiftX > development system, including a link to download a free trial version > (also > limited in program size). SwiftX is available for only $450, including > a royalty-free multitasking kernel, library of several hundred > functions, > full support for low-power mode, etc. The HLL is Forth, but assembler > is also supported. > > Cheers, > Elizabeth At this point I am leaning away from the MSP430 and more toward the ATmega64 or 128 if I can get a better price. The lack of boundary scan in the MSP430 is a problem for me. Are the ATmega parts supported by SwiftX? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39131
hi. i am having trouble getting chipscope to run on the XC2V3000ES FG676 -5 part. i was wondering if this was a known issue with the samples or if it somehow has to do with my configuration. i have ran chipscope on the XC2V1000 parts with no problem (the Insight board) and i would really like to get it up on the 3000. strut911Article: 39132
rickman <spamgoeshere4@yahoo.com> writes: > Ignoring the "special" features, I expect you will find that the Altera > parts achieve somewhat higher densities for a given gate count. Between > the XC2V and ApexII families, I guess you meant to say Apex familiy. ApexII has a different naming. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 39133
Austin Lesea <austin.lesea@xilinx.com> writes: > Rick, > > True, the I grade improvement is smaller than the C grade improvement. > > Kick starting that 'bike on those cold -40C mornings is hell. Surely no worse than -40F? :-) HomannArticle: 39134
"rickman" <spamgoeshere4@yahoo.com> skrev i meddelandet news:3C5A34E2.7690B964@yahoo.com... > > I don't like this statement. I am a Xilinx employee, and I hope that my postings > > are not considered Xilinx propaganda. I have even recommended Atmel EEPROMs ( > > long ago ) when they offered a solution that Xilinx did not have then. > You are entitled to your opinion, but I was making the point that a > Sales Engineer or an FAE would not be very likey to recommend a > competing part (which is what we are talking about in this case) even if > it had clear advantages. Well Xilinx in this case had a competing part, which was was non-reprogrammable, so I think Peter proved his point by recommending a "competing part since it had clear advantages" > My real point was that I am sure Ulf (like others) would like to say > many negative things about the competition, but there is always the Ain't my goal in life. If I want to say something, I generally do... As I said, the MSP430 is an excellent product, but I do prefer the major applications for it to be of the road filling kind ;-) > danger of appearing to be a politician campaigning for reelection. No > one likes that. ;) > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden.Article: 39135
Thank you Eric, yes it helps, but looking at some sample drivers (WinDk environment) it seems to me I don't need to set the Master enable bit by myself in the PCI command register. Elsewhere someone has said that the the BIOS does this job and I wonder how. Any other comments? Marco Eric Crabill <eric.crabill@xilinx.com> wrote in message news:<3C5992D3.4249D633@xilinx.com>... > Hi, > > My admittedly limited experience has shown that you should not > count on the operating system to do anything for you, particularly > if you are using a non-PNP operating system like WindowsNT. > > I have seen identical boards left in different states of "configuration" > by WindowsNT after the operating system boots when placing them in > different machines. I think (don't know for sure) that these > differences > are the result of what the BIOS on the machine is doing before the > operating system boots -- not actually the doing of WinNT. If you go > look at your BIOS settings, you may see things like: > > Slot 1: Enable BusMaster Y/N > Slot 2: Enable BusMaster Y/N > Enable PNP OS Y/N > etc... > > Or, you may not see anything at all. This particular BIOS help > indicated this was for legacy devices with a non-PNP operating > system where you needed the BIOS to set the bit before the OS > booted. > > So, for a robust solution, the key is to not assume anything, and > when you write the device driver, go out and set the bit yourself > as part of the routine that executes when the driver is loaded. > > If you are using one of the common device driver kits, I am sure > there is a function call to do this. If you are writing the driver > without one of these kits, refer to some of the example drivers in > the WinNt4.0 DDK. You can manually read the command register, set > the bit, and then write it back using HalGetBusData and HalSetBusData. > > Hope that helps, > Eric >Article: 39136
A question I cannot seem to find a consistent answer for in the xilinx docs: What's the value of an output port (e.g. port A) on a dual ported RAM block, when data is written to this location through port B. Device = SpartanII IMO it can be either the data from port B, the data that was stored at that location or undefined data. In my design it doesn't really matter if it's the data from port B or the stored data, as long as it's not undefined. Does anybody know if the output goes really undefined or not ??? Thanx, H.Article: 39137
Hi Ben and Mike, thanks for your advise! Yes, I missed that the clock pin now is asyncronous ... Would have been too easy :) Thus I'll go back to traditional techniques. Max Mike Treseler wrote: > > However, the gated clock could glitch > and the clear signal could cause a runt pulse > if it happens at just the wrong time near the wrong clock edge. > No problem for the clear signal! In my case it will never happen near any asyncronous signal. VhdlCohen wrote: > > You missed something!!! > You are ANDing the asynchronous input with the clock (eoc.clk = as_in & (global > (lclk)); and > using this newly created clock to clock in clock in a ONE. > What if your as_in is at the analog transition level of the AND gate at the > same time as your system clock? You may get a slow rising clock, or a partial > clock.Article: 39138
still reading..... If the data does go 'undefined', can I use the RDY port (Inserted when you make a DP RAM with the Core generator) to slow down the read-process ?? The RDY should go high if the dat is valid, so maybe it's usefull for this pupose.... H.Article: 39139
Hi, I can give you some suggestions: if assigning a device, allow for future growth and fitting: -10% of the device LEs Unused -10% of the device Pins Unused if you must assign Pins, for best performance: -assign Bi-directional I/O to row pins -assign speed critical, low fanout inputs to row pins -assign high fan-out inputs to column pins if dedicated inputs are not available -assign wide buses to row pins for easy fitting: -more pins per row than per column In Altera software help you can find on what row and column each pin is located I hope that helps. Marco "Jeroen Van den Keybus" <vdkeybus@esat.kuleuven.ac.be> wrote in message news:<1011993874.881445@seven.kulnet.kuleuven.ac.be>... > Hello, > > I want to connect an EP1K100 ACEX to a 32-bit host which will access it > asynchronously. So there is a 32 bit data bus and a 16 bit address bus and > some control signals (nWE, nRD, nCS). A colleague of mine will be designing > the PCB for it and he would like to start routing asap even while the FPGA > software is still being written. So he wants to have a complete pin > assignment already. As a matter of fact, the FPGA software will probably > often be rewritten on the same PCB to accomodate different lab setups. > > My question: are there any guidelines regarding the pin position or should I > rather have him (my colleague) define the pinout for easiest layout. More > precisely, should we rather put D[0..31] and A[0..15] on column or row > interconnects (the ACEX will be written to and read from). We'd hate to see > the Max+2 fitter fail at the end of the month just because of stupid pin > positions we can't change anymore. > > Because of this issue we have already oversized the FPGA, normally max. > 60-70% of the LE's will be used. But apart from EMC guidelines stating that > 'bunching' of large groups af signals should be avoided, we have found > nothing more on this topic. > > Jeroen.Article: 39140
you can use the LUT primitives in the current tools and assign the INIT
attribute/generic, which is basically a vector containing the karnaugh map. Not
quite the same as the karnaugh maps in the old XDE, but about as close as you're
going to get in a text based design environment.
Tim wrote:
> With dear old XACT you could play with Karnaugh maps directly.
>
> "Ray Andraka" wrote
>
> > You haven't lived!
> >
> > Rick Filipkiewicz wrote:
> >
> > >
> > >
> > > Karnaugh - what's that ? :-).
> > >
> > > I got into digital design with the PAL/ABEL generation &, since those nice
> people
> > > at Berkley supplied Expresso and Presto reduction for me, I've never done a
> K-map
> > > in my life [no self-timed design] and have rarely had to DeMorganise by
> hand.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39141No errata on the errata sheet affects Chipscope ILA, I worked personally with one customer who was using it to resolve a design issue on some 2V3000ES parts. If you need help, open a hotline case. Austin strut911 wrote: > hi. > i am having trouble getting chipscope to run on the XC2V3000ES FG676 > -5 part. i was wondering if this was a known issue with the samples or > if it somehow has to do with my configuration. i have ran chipscope on > the XC2V1000 parts with no problem (the Insight board) and i would > really like to get it up on the 3000. > strut911Article: 39142
rgf <erwh@iurf.jhf> wrote in message news:<ee74982.-1@WebX.sUN8CHnE>...
> I generate a crc (data width 2 bit,32 bit crc,802.3)from (www.easics.com ).Then ,i study the module.there is a function in the module.but it need input "input [31:0] CRC".i think the crc result is what i need.where is it
> from?that is ,the crc result should be calculated by it.
> can you help me?
I experimented some with the 1-bit data input CRC32. I think I
renamed the function to nextCRC32_D1.
My use of the functions is as follows:
crc32_s <= nextCRC32_D1(Data => CRC_DIN, CRC => crc32_s);
The inputs for me, was a 1 bit data input, and the last result or
initial value.
The function returns the result.
Newman
P.S. Thank-you Ray for the combinatorial RLOC tips.
Article: 39143Harjo, the read operation is dynamic, it occurs as a result of the active clock edge. After that, it ignores the content of the cell that has been read, So, the simple answer is that any writing into the already read cell has no impact on the read output. But, there is no internal arbitration. If read and write clock edges are very close to each other ( within a ns or two ), the read output cannot be guaranteed, is "undefined". It could be the old, the new, or any mixture of the two. Hope this helps Peter Alfke, Xilinx Applications ======================= Harjo Otten wrote: > A question I cannot seem to find a consistent answer for in the xilinx docs: > > What's the value of an output port (e.g. port A) on a dual ported RAM block, > when data is written to this location through port B. Device = SpartanII > > IMO it can be either the data from port B, the data that was stored at that > location or undefined data. > > In my design it doesn't really matter if it's the data from port B or the > stored data, as long as it's not undefined. Does anybody know if the output > goes really undefined or not ??? > > Thanx, > > H.Article: 39144
Hi all, I'm trying to do the same: export to EDIF and use the result in another design (VHDL or Verilog) as an instantiated core. But the Xilinx WebPACK ISE 4.1 cannot do it (or I don't know) and the licensed ISE 4.1 cannot do it either (by the way, someone can explain me the differences between these two programs, one free and the other not). I'm amazing: the WebPACK can compile and implement Verilog files, and can implement EDIF files ... but cannot implement mixed Verilog-with-EDIF-cores designs. Hey, Xilinx guys, this can be a good idea for people who want to give their cores to the community ;-). Good luck to all. Cheers, Santiago (sanpab@eis.uva.es). --------- Vikram escribió: > > John, > > Your top-level seems to be a wrapper file with instantiations of I/O > buffers and processor core. If this is the case, all you need to do is > > 1. Synthesize the lower level processor core and generate the edif file. > While generating this netlist file, make sure the synthesis tool does not > inserts any I/O buffers (all synthesis tools have an option to turn I/O > buffer insertion off). > > 2. Synthesize only the the top-level file and use black box attribute for > the processor core instantiation. > > Now you have two netlist files, top level netlist file and processor core > netlist. Make sure these two netlist files are in the same folder and run > your DOS batch file. Ngdbuild will combine these two netlists and > generates a ngo file. > > The processor netlist can be distributed instead of your HDL source code. > If you need to interface/add any other module to this processor, this can > be done with a different hierarchy in the top level HDL file. > > Hope this helps !!! > > -Vikram > Xilinx Design Services. > > In Memory of tecNovia wrote: > > > I have a processor core synthesized and turned into a complete FPGA > > programming file by Xilinx Foundation 3.3i. > > > > Instead I need to turn the processor into a module which would be only > > a part of the FPGA, so that other IP could be linked with it inside > > the FPGA. I must deliver only the EDIF or similiar file to potential > > users so as to keep the source code secure. > > > > I'm currently using Foundation (XST) to synthesize to an EDIF file > > then running a DOS batch file to get from the EDIF file to the MCS > > programming file. > > > > edif2ngd pscxl.edn > > ngdbuild -p xcv600ehq240-6 pscxl > > map -p xcv600ehq240-6 -cm speed -pr b pscxl > > par -w -ol 3 -t 4 -i 3 pscxl.ncd pscxl_par.ncd > > trce -e 10 -s 6 -o pscxl.twr pscxl_par.ncd pscxl.pcf > > bitgen -d -w pscxl_par.ncd pscxl.bit pscxl.pcf > > promgen -w -p mcs -u 0 pscxl.bit > > > > I'm a novice user - the processor core and Xilinx setup was created by > > another - I'm just making minor mods and learning as I go. > > > > So, exactly how are IP blocks combined inside one FPGA? My source code > > is partitioned into VHDL modules with the top layer only a Xilinx > > wrapper with components ibuf, ibufg, and the next lower level VHDL > > module, so I assume my first step would be to compile an EDIF file > > without the top level. > > > > John > > jkolb@ptsc.comArticle: 39145
Hi, If you are using a driver development kit, perhaps the setting of the enable bit is obscured by being called in some other routine that sets up an adapter. I am not familiar with WinDK, only with the Compuware Driver Works package and the examples I have seen in the NT DDK. You'll probably have to consult the documentation or the online help. If you were an operating system, and you located a card which you didn't know what it was (e.g. not having a class code with a pre-defined programming interface) would you enable its bus master enable bit automatically? I wouldn't. Eric Marco Serafini wrote: > > Thank you Eric, > > yes it helps, but looking at some sample drivers (WinDk environment) > it seems to me I don't need to set the Master enable bit by myself in > the PCI command register. Elsewhere someone has said that the the BIOS > does this job and I wonder how. Any other comments? > > Marco > > Eric Crabill <eric.crabill@xilinx.com> wrote in message news:<3C5992D3.4249D633@xilinx.com>... > > Hi, > > > > My admittedly limited experience has shown that you should not > > count on the operating system to do anything for you, particularly > > if you are using a non-PNP operating system like WindowsNT. > > > > I have seen identical boards left in different states of "configuration" > > by WindowsNT after the operating system boots when placing them in > > different machines. I think (don't know for sure) that these > > differences > > are the result of what the BIOS on the machine is doing before the > > operating system boots -- not actually the doing of WinNT. If you go > > look at your BIOS settings, you may see things like: > > > > Slot 1: Enable BusMaster Y/N > > Slot 2: Enable BusMaster Y/N > > Enable PNP OS Y/N > > etc... > > > > Or, you may not see anything at all. This particular BIOS help > > indicated this was for legacy devices with a non-PNP operating > > system where you needed the BIOS to set the bit before the OS > > booted. > > > > So, for a robust solution, the key is to not assume anything, and > > when you write the device driver, go out and set the bit yourself > > as part of the routine that executes when the driver is loaded. > > > > If you are using one of the common device driver kits, I am sure > > there is a function call to do this. If you are writing the driver > > without one of these kits, refer to some of the example drivers in > > the WinNt4.0 DDK. You can manually read the command register, set > > the bit, and then write it back using HalGetBusData and HalSetBusData. > > > > Hope that helps, > > Eric > >Article: 39146
1. Only I add is that I want to use Leo, it seems me more suitable for the purpose, but ... it asks 5500 LCs with opimization for Area and some tricks yet. 2. I cannot to pass yo a largeer device - PCB is already made. 3. It'll be interesting to hear opinion of somebody from Exemplar Logic - designer of LeonardoSpectrum . Any way, thanks for reply, Igor Peker Kevin Brace <ihatespamkevinbraceusenet@ihatespamhotmail.com> wrote in message news:<a3daq8$rkt$1@newsreader.mailgate.org>... > I suppose the answer is that not all synthesis tools are created > equally. > Have you ever tried synthesizing your design from Quartus II 1.1 Altera > in-house synthesis tool (not the third party ones you use)? > I must say that from my experience synthesizing the exact same Verilog > design with both LeonardoSpectrum-Altera (free version) and Quartus II > 1.1 Altera in-house synthesis tool is that Quartus II 1.1 Web Edition > Altera in-house synthesis tool used far more LEs (LeonardoSpectrum used > 1,600 LEs versus 2,500 LEs for Quartus II 1.1 Web Edition Altera > in-house synthesis tool.). > The FPGA I targeted was the same chip you are targeting, FLEX 10K100E-1. > All I can say is that you should try to adjust the synthesis > options to reduce the number of LEs that gets generated (i.e., optimize > for area rather than speed), or move to a larger device. > > > > > Kevin Brace (Don't respond to me directly, respond within the > newsgroup.) > > > > > Igor Peker wrote: > > > > Hi, > > > > Can anybody explain me why the same Verilog design from Synopsys FPGA > > Express is fitted by MaxPlus/Quartus into 4992 LCs of Flex10KE-100, > > but from Leonardo - > > no ? > > +: all procedures to extract ROM/RAM, etc. were made in Leo instead of > > FPGA, but Synopsys wins. > > > > Thanks in advance, > > Igor PekerArticle: 39147
You need to put a placeholder in your design in the form of a black box for the
edif component. Leave the component out of the synthesis of your top level.
When you run the xilinx PAR tools, NGDBUILD will glue together the edif files,
provided it can find them. This should work no matter what the source was as
long as the port descriptions of instantiated edifs match the ports in the
blackboxes.
Note that this only works for getting you the FPGA bitstream, not for
simulation of the design. To simulate it, you will generally need a model of
the design for the simulator to plug in for the black box. One option, the one
that seems the easiest, is to use the mapped output from the synthesis (in
synplicity that is the *.vhm file). It is about as readable as the edif, and
is basically a netlist of primitives with any user attributes (like RLOCs)
stripped off. It is simulatable.
Santiago de Pablo wrote:
> Hi all,
>
> I'm trying to do the same: export to EDIF and use the result in
> another design (VHDL or Verilog) as an instantiated core. But the Xilinx
> WebPACK ISE 4.1 cannot do it (or I don't know) and the licensed ISE 4.1
> cannot do it either (by the way, someone can explain me the differences
> between these two programs, one free and the other not).
>
> I'm amazing: the WebPACK can compile and implement Verilog files, and
> can implement EDIF files ... but cannot implement mixed
> Verilog-with-EDIF-cores designs. Hey, Xilinx guys, this can be a good
> idea for people who want to give their cores to the community ;-).
>
> Good luck to all. Cheers, Santiago (sanpab@eis.uva.es).
> ---------
> Vikram escribió:
> >
> > John,
> >
> > Your top-level seems to be a wrapper file with instantiations of I/O
> > buffers and processor core. If this is the case, all you need to do is
> >
> > 1. Synthesize the lower level processor core and generate the edif file.
> > While generating this netlist file, make sure the synthesis tool does not
> > inserts any I/O buffers (all synthesis tools have an option to turn I/O
> > buffer insertion off).
> >
> > 2. Synthesize only the the top-level file and use black box attribute for
> > the processor core instantiation.
> >
> > Now you have two netlist files, top level netlist file and processor core
> > netlist. Make sure these two netlist files are in the same folder and run
> > your DOS batch file. Ngdbuild will combine these two netlists and
> > generates a ngo file.
> >
> > The processor netlist can be distributed instead of your HDL source code.
> > If you need to interface/add any other module to this processor, this can
> > be done with a different hierarchy in the top level HDL file.
> >
> > Hope this helps !!!
> >
> > -Vikram
> > Xilinx Design Services.
> >
> > In Memory of tecNovia wrote:
> >
> > > I have a processor core synthesized and turned into a complete FPGA
> > > programming file by Xilinx Foundation 3.3i.
> > >
> > > Instead I need to turn the processor into a module which would be only
> > > a part of the FPGA, so that other IP could be linked with it inside
> > > the FPGA. I must deliver only the EDIF or similiar file to potential
> > > users so as to keep the source code secure.
> > >
> > > I'm currently using Foundation (XST) to synthesize to an EDIF file
> > > then running a DOS batch file to get from the EDIF file to the MCS
> > > programming file.
> > >
> > > edif2ngd pscxl.edn
> > > ngdbuild -p xcv600ehq240-6 pscxl
> > > map -p xcv600ehq240-6 -cm speed -pr b pscxl
> > > par -w -ol 3 -t 4 -i 3 pscxl.ncd pscxl_par.ncd
> > > trce -e 10 -s 6 -o pscxl.twr pscxl_par.ncd pscxl.pcf
> > > bitgen -d -w pscxl_par.ncd pscxl.bit pscxl.pcf
> > > promgen -w -p mcs -u 0 pscxl.bit
> > >
> > > I'm a novice user - the processor core and Xilinx setup was created by
> > > another - I'm just making minor mods and learning as I go.
> > >
> > > So, exactly how are IP blocks combined inside one FPGA? My source code
> > > is partitioned into VHDL modules with the top layer only a Xilinx
> > > wrapper with components ibuf, ibufg, and the next lower level VHDL
> > > module, so I assume my first step would be to compile an EDIF file
> > > without the top level.
> > >
> > > John
> > > jkolb@ptsc.com
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39148
Hi all,
I'm trying to implement a read only "register" in a Spartan xcs05xl. It's
not a register, it's simply a constant that is set in the vhdl and I want to
return this constant on the databus when a specific address shows up on the
address bus. I currently just use an output mux, and when the select signal
is right, I just return a constant 8 bit value. This doesn't seem to be
working reliably in the synthesized device, yet it simulates fine. Am I
missing something, or does the problem lie elsewhere? Here's a snippet to
show what I'm trying to do:
signal A,B,C,Y : unsigned(7 downto 0);
-- process to select output
muxout : process(SEL, A, B, C)
begin
case SEL is
when "00" => Y <= A;
when "01" => Y <= B;
when "10" => Y <= C;
when "11" => Y <= "11001010";
when others => Y <= (others => 'X');
end case;
end process;
Thanks
Dave
Article: 39149Steven, this sounds similar to Paul's MP3 player at www.pjrc.com. An 8051 accesses the storage on an IDE drive and talks to a Xilinx part (not sure of the size, but small, in an 84 PLCC) that buffers to a SIMM DRAM for playback through an MP3 decoder. He is offering the configuration for $150 (minus HD and SIMM) so it is pretty cost-effective. Just some notes on your questions: -Anything over 20MHz PCB trace lengths you pretty much need to simulate trace length and impedances. ( or gamble if you feel lucky...) -I certainly don't know your application, but what about adding a FLASH part to buffer HD data. You could probably find one for about $1 and have a jumper that prevents HD from overwriting the FLASH buffer. If you are doing run-time reconfigurations, maybe having a separate partition on the drive that is unknown to the other users of the drive might be a method... -I think Paul's board is a 4"x5" at four layers. I think the first spin took less than two months. Ask him for more accuracy, but this certainly depends on your expertise. -Steen (respond to steen at tech-forge.com) Steven Derrien <sderrien@irisa.fr> wrote in message news:<3C554CD1.893D0AA0@irisa.fr>... > Hello, > > This post is just for submitting an idea to those who are familiar with > embedded system design, in order to get some feed-back (with respect to > feasibility, cost, usefulness and so on…). > > The basic idea is the following : > > We want to design a reconfigurable SoC, which will be connected to an > IDE hard-drive, used by the application running on the SoC. One of the > key point, is that we need to perform dynamic reconfiguration of the > FPGA. > > Our idea is to use the Hard-drive memory to store the various FPGA > configurations, and to use a small 32 I/O MCU (8051) to perform the FPGA > reconfiguration from the HDD. (the 8051 would share the IDE bus with the > FPGA, but they would have a mutual exclusive use of the HDD, since the > MCU would only be used during reconfiguration) > > Since the FPGA should be a relatively big Virtex/Spartan-II, and since a > large density configuration EEPROMs (several Mbits) are quite expensive > compared to a small MCU, we feel that this could be a nice way to reduce > the total system cost. > > Now we are wondering whether this idea is good or not :), we are > specifically concerned with : > > - PCB layout and signal integrity problems due to the fact that the IDE > connection is shared between the MCU and the FPGA. For ex. would it be > possible to use high-speed IDE (50Mhz clock) protocols from the FPGA ? > > - Reliability : since the hard-drive will be used for both read and > write operation during the application, we must ensure that some part of > the HDD storage is locked (to guarantee that the configurations are not > overwritten by mistake) > > - Feasibility : How difficult would it be to design and debug such a > system ? > > Any advice, comments, critics, ideas are welcome, > > Thank you in advance. > Steven
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