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rickman wrote: (I have snipped some parts) > If you can't accommodate more channels either though ganging of probes > or with wider probes, I can't see an application for this device with > the boards we design. Hard to argue with your points. But there are scenarios in which the Ant8 layout makes sense. One example is educational apps. Another which is more applicable to readers of this group is where you _know_ via simulation that the design is 100% correct, but it just does not work. The problem is often resolved by looking at just a few real-world signals on a logic analyzer. In fact one reason for going for something like the Ant8 is that in this situation the burden of searching out the logic analyzer trolley and refreshing your recollection of the manuals can be enough to put off looking at the signals for quite some time. At least, that is what happens when I am driving :-) > The HP probe attach is > just a 20 pin ribbon cable connector. I don't think this is > significantly more expensive than the sub-D connector. I bet the HP probe costs more than an Ant8+probe. My HP analyzer has a set of 8-bit probe pods, each of which is a little larger than an Ant8. We would like to support HP/Agilent probe technology, but I don't expect Agilent would like to do business with an upstart FPGA company. > But again, without a 16 input probe and software to allow multiple > probes to be ganged, this is not a useful product for debugging our > boards. Not trying to criticize, just giving some feedback. Thanks for > listening. That is something I don't feel like I get much from HP. Understood, but I will hear no word spoken against HP. At least not against the real HP. They are the good guys and gals. Thanks for the comments. TimArticle: 50651
Off topic: Do you know anyone who worked on the FPGA in the NCD Explora 451? It's a Quicklogic ql8x12b. It's acting as a PCI bridge and possibly part of the PCMCIA interface. NCD says the product is EOL'd and everyone who worked on it has left. I'm desperate to find out a few details of the bridge so some of us can boot Linux on the box... I'm close but I need to know what a few of the bits do. grasping at straws... Send me email if you know anything. Sorry for the noise. -bradArticle: 50652
Roger Green wrote:
>
> Hi Jeff,
>
> The PCI slot in your PC is most likely 32-bit, 33MHz flavor. You most
> likely will have to look in very new hi-end computers or "server" type
> platforms to find 64-bit, 66 MHz type PCI slots. PCI is the standard card
> edge connector form factor.
>
If I were to add one more thing, almost all desktop computers
have 5V 32-bit 33MHz PCI slots.
> If you're interested in learning all the gory details of PCI, I would
> recommend the book "PCI System Architecture" published by Mindshare, Inc.
> Its a very good reference and is easier to understand that the PCI sig's
> specifications, which they want $ for anyway.
> --
When I developed my own PCI IP core, I found the PCI
specification much more helpful than PCI System Architecture or PCI
Hardware & Software.
Unfortunately, the PCI specification now costs $100 + shipping for
non-PCISIG members instead of $40 + shipping it used to be a year ago.
Kevin Brace (If you want to respond to what I wrote, I prefer if you
will do so within the newsgroup.)
Article: 50653Duane, Not sure if this posting I made a while ago will help you, but it should be relevant. http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&newwindow=1&safe=off&selm=cc7b0b5f.0210081256.22ba2b1f%40posting.google.com I know that all three registers inside an IOB have to have the same clock, but CE input (Clock Enable) can be different. I am sure you already have, but make sure the fanout from the FF that you want to push into an IOB really has a fanout of one by using floorplanner. The above URL I gave you also has a URL explaining (in detail) how to get XST to generate an EDIF netlist. Reading the EDIF netlist should help you figure out what XST is doing to your design. In the worst case, you might have to edit the EDIF netlist by a text editor to duplicate FFs so that you can get the FFs into IOBs. Kevin Brace (If you want to respond to what I wrote, I prefer if you will do so within the newsgroup.)Article: 50654
Hi, Recently I have to switch from ISE for windows to ISE for solaris, everything works fine except that one of my design can not be synthesized in ISE for solaris. The XST reports me the following message when it is doing low level synthesis: Library "/CAD/tools/xilinx/data/librtl.xst" Consulted INTERNAL_ERROR:Xst:cmain.c:3195:1.89.2.1 - To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com --> This design can be synthesized very well in ISE for windows. Though I can still switch back to windows again, I am very curious about what happend here. Could anyone give me some enlightenment? Thanks a lot, HuaArticle: 50655
> I would like to implement a memory controller that allows > multiple components to access the same location at the same time How many components ? How many memory locations ? Do you mean at exactly the same time ? Is this for only read access, or both read and write access ? How fast does it have to run ? If there is some timing bandwidth available you can simulate simultaneous access using time division multiplexing. If there are more than two components, you can't do simultaneous access easily for write access, but you can use multiple block rams to get more read ports. > in a dual port ram I am using within a Virtex device. > What could be the best way to implement that? > In software we can use semaphores to control the memory region Unless I am mistaken, I think you would still need the software semaphores to control (serialize) access to specific objects. However, perhaps support for semaphores could be added in hardware making them more efficient. If you are trying to access different objects in same memory region then semaphores may not be needed. > but how do I accomplish that in HDL. > Thanks for your help.Article: 50656
Thanx the folks for ur replies. What will happen if OTP ROM faced SEU or SEL? Is triple-mode redundancy valid for OTP ROM? IS Xilinx OTP made of antifuse or MOS technique? waiting for reply. S.Thiruppathirajan Peter Alfke <peter@xilinx.com> wrote in message news:<3DFA73CE.2EC14CF8@xilinx.com>... > Josh Model wrote: > > > http://www.xilinx.com/products/military/radhardv.htm > > > > This should get you started, especially the SEU paper. Xilinx's FPGA's have > > their configuration stored in an external PROM, probably OTP. To summarize, > > suggested solutions involve Triple mode redundancy, and CRC checking the > > bitstream using periodic repeated reconfiguration. > > > > One thing to watch out for, though, is current surges during > > reconfiguration/power up. > > Just a slight correction: > Yes, Xilinx FPGAs prior to Virtex-II have an Icc surge when first powering up. > Virtex-II and later do NOT have that surge. > More importantly: > This surge does NEVER occur upon reconfiguration while Vcc is maintained, it > only occurs when Vcc is (re)applied. > > Peter Alfke, XilinxApplicationsArticle: 50657
Austin Franklin wrote: > > "glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message > news:Sh7K9.339038$P31.129678@rwcrnsc53... > > > > "hristo" <hristostev@yahoo.com> wrote in message > > news:b0ab35d4.0212120822.46ba96e@posting.google.com... > > > Hello, > > > general question here, sorry if it is off-topic. > > > > > > what makes an implementation be elligible for a patent status? > > > > > > i expect Novelty first. But if someone takes an architecture and > > > optimise it according to a special FPGA (eg. Virtex), so he takes the > > > maximum of the chip features to implement it optimally. can he submit > > > this work for a patent?? > > > > Since the XOR operator has been patented, and upheld twice, > > I would say that it doesn't take much to be eligible. > > Glen, > > It appears that it is NOT the XOR operator that is patented, but using it > for screen cursors, and yes, though apparently "upheld", is a completely > bogus patent, IMO, and I am amazed it was upheld. The patent was filed many > years after people had been using this technique, and not by the person who > actually used it first. > > It's apparently patent # 4,070,710 granted in 1978.... My understanding is that a patent can not be applied for more than a year after an invention is made public or otherwise used in a public invention by someone else. I belive this is called "prior art". If that is correct, how could this patent be granted and upheld when it was in common use for "years" before the patent was applied for? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50658
Tim wrote: > > rickman wrote: (I have snipped some parts) > > If you can't accommodate more channels either though ganging of probes > > or with wider probes, I can't see an application for this device with > > the boards we design. > > Hard to argue with your points. But there are scenarios in which > the Ant8 layout makes sense. One example is educational apps. > Another which is more applicable to readers of this group is where > you _know_ via simulation that the design is 100% correct, but it > just does not work. The problem is often resolved by looking at > just a few real-world signals on a logic analyzer. > > In fact one reason for going for something like the Ant8 is that > in this situation the burden of searching out the logic analyzer > trolley and refreshing your recollection of the manuals can be > enough to put off looking at the signals for quite some time. > At least, that is what happens when I am driving :-) I am not trying to argue any points. I am just giving feedback on our applications. > > The HP probe attach is > > just a 20 pin ribbon cable connector. I don't think this is > > significantly more expensive than the sub-D connector. > > I bet the HP probe costs more than an Ant8+probe. My HP analyzer has > a set of 8-bit probe pods, each of which is a little larger than an > Ant8. > > We would like to support HP/Agilent probe technology, but I don't > expect Agilent would like to do business with an upstart FPGA company. I am not suggesting that a probe be copied. I am suggesting that your probe end could use the same type of connector, a standard 0.1"x0.1"-20 pin ribbon cable connector, and the same pinout. I don't think HP (or Agilent) will mind since they make this info public. I also don't know that the pinout is patented, which is what I think would be required to prevent it from being copied. I can send you the document if you want so that you can see what I am talking about. > > But again, without a 16 input probe and software to allow multiple > > probes to be ganged, this is not a useful product for debugging our > > boards. Not trying to criticize, just giving some feedback. Thanks for > > listening. That is something I don't feel like I get much from HP. > > Understood, but I will hear no word spoken against HP. At least > not against the real HP. They are the good guys and gals. > > Thanks for the comments. They may be good folk, but they don't listen much to individuals. Same with Tektronix. I was at a seminar for their new logic analyzer once. It was very hands on and we got to play with their units. I told them that the big problem that I saw was the very slow drawing speed of their user interface which was the (then) new GUI look and feel, instead of the old many buttons and touch screen. Seems they used a PC (circa 1988) or something similar to implement the GUI in software and that they were not likely to "fix" it. I understood what they were saying, but that machine was a PITA to use. It seemed they just didn't want to hear any negative feedback. I don't mind a bit calling it like I see it. HP and Tek make some great instruments. But they just don't listen when they don't want to. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50659
rickman wrote: > > Austin Franklin wrote: > > > > "glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message > > news:Sh7K9.339038$P31.129678@rwcrnsc53... > > > > > > "hristo" <hristostev@yahoo.com> wrote in message > > > news:b0ab35d4.0212120822.46ba96e@posting.google.com... > > > > Hello, > > > > general question here, sorry if it is off-topic. > > > > > > > > what makes an implementation be elligible for a patent status? > > > > > > > > i expect Novelty first. But if someone takes an architecture and > > > > optimise it according to a special FPGA (eg. Virtex), so he takes the > > > > maximum of the chip features to implement it optimally. can he submit > > > > this work for a patent?? > > > > > > Since the XOR operator has been patented, and upheld twice, > > > I would say that it doesn't take much to be eligible. > > > > Glen, > > > > It appears that it is NOT the XOR operator that is patented, but using it > > for screen cursors, and yes, though apparently "upheld", is a completely > > bogus patent, IMO, and I am amazed it was upheld. The patent was filed many > > years after people had been using this technique, and not by the person who > > actually used it first. > > > > It's apparently patent # 4,070,710 granted in 1978.... > > My understanding is that a patent can not be applied for more than a > year after an invention is made public or otherwise used in a public > invention by someone else. I belive this is called "prior art". If > that is correct, how could this patent be granted and upheld when it was > in common use for "years" before the patent was applied for? > Patents are merely a license to litigate, or negotiate. In practice, "prior art", and "not obvious to one experienced in the field" conditions are rarely fully researched. -jgArticle: 50660
Hi, Is the Xilinx VirtexII Pro support floating point calculation?? What's the advantages of embedding the PowerPC in the FPGA? Will this benefit the application in real time hardware acceleration system (Gene matching, inline cracking...)? Any good suggestion of which prototyping board with VirtexII Pro and PCI interface is good for developing realing computation system? Thanks. Terrence MakArticle: 50661
Hi, Does Xilinx Virtex2Pro support the floating point computation? In fact what is the advantages of embedded the PowerPC in the FPGA. What's software design environment support the system design of Virtex2Pro with the PowerPC? Besides, would you mind suggest any FPGA prototyping board available in the market is embedding the Virtex2Pro and with PCI interface? Thanks. Terrence MakArticle: 50662
nkavv@skiathos.physics.auth.gr (Uncle Noah) wrote in message > > Unfortunately, LPM is now unsupported from Altera as stated at: > http://www.edif.org/lpmweb. Check if this link is still up. > > However, you can get the library and documentation on the modules from > there. If you search hard at Altera and Xilinx websites you can find > references on example uses of LPM. > > Uncle "The G.B. Man" Noah I don't think Xilinx ever supported LPM and I suspected Altera gave up on it too. But I am curious if most synthesis tools accept EDIF LPM as a valid input? I've developed a set of tools that generate hdl from another language. The problem I am encountering is keeping the generated hdl code independent from both the target platform and the downstream synthesis tool. The main problem is RAM and ROM inference. It's been my experience that synthesis tools are fairly picky about hdl coding styles for inferring memory. Plus, the number of options and memory types on modern fpgas further complicates the issue. I was hoping LPM could be a solution. That is a standard specification independent of synthesis and platform. Regards, TomArticle: 50663
Terrence, For floating point support in the 405PPC(tm IBM) in the Virtex II Pro, you can either inlcude the floating point c library for floating point calls, or create logic to perform the specific floating point operations that are needed and use it from the 405PPC. The use of hard logic for a floating point unit was considered too expensive a use of real estate. The advantage of having a processor on the FPGA is that 50% of all new complex ASICs now include a processor. So, might as well give folks one of the best ones, along with the best FPGA. Right now the software support is all there, along with the hardware support. Contact a FAE or sales partner for availability of the prototyping platforms. Austin Terrence Mak wrote: > Hi, > > Does Xilinx Virtex2Pro support the floating point computation? In fact what > is the advantages of embedded the PowerPC in the FPGA. What's software > design environment support the system design of Virtex2Pro with the PowerPC? > > Besides, would you mind suggest any FPGA prototyping board available in the > market is embedding the Virtex2Pro and with PCI interface? Thanks. > > Terrence MakArticle: 50664
> My understanding is that a patent can not be applied for more than a > year after an invention is made public or otherwise used in a public > invention by someone else. I belive this is called "prior art". If > that is correct, how could this patent be granted and upheld when it was > in common use for "years" before the patent was applied for? Hi Rick, You are correct, for the most part. You can, though, do a preliminary application, and continue working on the "patent" for quite some time, and can apply, and be rejected...and re-apply. Look at the fool patent for the microprocessor that the patent office granted some TWENTY YEARS (I don't remember the exact time, but it was absurd) after the fact... Think of it this way. If you were patenting a fishing lure, you better have your act together...as the guys in the patent office who deal with fishing lures are at the top of the game. Where else could you get $60k/year and play with fishing lures all day, if that was your bag...but then consider our type of patents...who on earth would want to only make $60k/year with the level of experience/knowledge required to deal with these type of patents? Issue is quality of people... Regards, AustinArticle: 50665
> Right now the software support is all there, along with the hardware support. Hi Austin, How does simulation work? When I simulate my FPGA, how do I also get it to simulate the processor/software etc.? Regards, AustinArticle: 50666
"Rob Finch" <robfinch@sympatico.ca> wrote in message news:<oleL9.1635$pS6.306825@news20.bellglobal.com>... > > I would like to implement a memory controller that allows > > multiple components to access the same location at the same time > > How many components ? How many memory locations ? Do you mean at exactly the > same time ? Is this for only read access, or both read and write access ? > How fast does it have to run ? > > If there is some timing bandwidth available you can simulate simultaneous > access using time division multiplexing. If there are more than two > components, you can't do simultaneous access easily for write access, but > you can use multiple block rams to get more read ports. > > > in a dual port ram I am using within a Virtex device. > > What could be the best way to implement that? > > > In software we can use semaphores to control the memory region > > Unless I am mistaken, I think you would still need the software semaphores > to control (serialize) access to specific objects. However, perhaps support > for semaphores could be added in hardware making them more efficient. If you > are trying to access different objects in same memory region then semaphores > may not be needed. > > > but how do I accomplish that in HDL. > > Thanks for your help. Actually there will be 8 to 16 identical components(simultaneously data bytes being fed to the components) doing number crunching and their outputs could be such that they could be writing data to the same location in a memory at exactly the same time.Article: 50667
alison wrote: > Actually there will be 8 to 16 identical components(simultaneously > data bytes being fed to the components) doing number crunching > and their outputs could be such that they could be writing data to the > same > location in a memory at exactly the same time. Well, let's for a moment forget about the implementation details: What is it you expect as a result after several sources have written different data "simultaneously" into the same location? Last man wins? But who is last ? Peter AlfkeArticle: 50668
Austin, The following link: http://toolbox.xilinx.com/docsan/xilinx5/data/docs/sim/sim0047_9.html discusses the Smart/Swift models which represent the 405ppc in encrypted HDL code for simulation. Austin Austin Franklin wrote: > > Right now the software support is all there, along with the hardware > support. > > Hi Austin, > > How does simulation work? When I simulate my FPGA, how do I also get it to > simulate the processor/software etc.? > > Regards, > > AustinArticle: 50669
I doubt that this patent is "bogus." After all from what I understand Autodesk had to pay up. I'm sure Autodesk had good laywers. I'm sure if it were true that it was in wide use before it was filed then the Autodesk laywers would have pointed that out. What is more likely is that one of the 32 claims are valid and Autodesk was forced to pay. So while it seems that it might be "bogus" nobody pays out money without going into court and "proving" the validity one way or the other. Steve "Austin Franklin" <austin@da98rkroom.com> wrote in message news:uvpinunbau1m12@corp.supernews.com... > It appears that it is NOT the XOR operator that is patented, but using it > for screen cursors, and yes, though apparently "upheld", is a completely > bogus patent, IMO, and I am amazed it was upheld. The patent was filed many > years after people had been using this technique, and not by the person who > actually used it first. > > It's apparently patent # 4,070,710 granted in 1978.... >Article: 50670
Steve, That's not always true. They only paid out $25k BTW, from what I understand. Sometimes it is simply cheaper and easier to make an out of court settlement, then to pay the lawyers to then take the chance of losing the suit. Austin "Steve Casselman" <sc@vcc.com> wrote in message news:VErL9.942$PA7.62014598@newssvr15.news.prodigy.com... > I doubt that this patent is "bogus." After all from what I understand > Autodesk had to pay up. I'm sure Autodesk had good laywers. I'm sure if it > were true that it was in wide use before it was filed then the Autodesk > laywers would have pointed that out. What is more likely is that one of the > 32 claims are valid and Autodesk was forced to pay. So while it seems that > it might be "bogus" nobody pays out money without going into court and > "proving" the validity one way or the other. > > Steve > > > "Austin Franklin" <austin@da98rkroom.com> wrote in message > news:uvpinunbau1m12@corp.supernews.com... > > > It appears that it is NOT the XOR operator that is patented, but using it > > for screen cursors, and yes, though apparently "upheld", is a completely > > bogus patent, IMO, and I am amazed it was upheld. The patent was filed > many > > years after people had been using this technique, and not by the person > who > > actually used it first. > > > > It's apparently patent # 4,070,710 granted in 1978.... > > > >Article: 50671
Peter Alfke <peter@xilinx.com> wrote in message news:<3DFE0CE9.37756DD4@xilinx.com>... > alison wrote: > > > Actually there will be 8 to 16 identical components(simultaneously > > data bytes being fed to the components) doing number crunching > > and their outputs could be such that they could be writing data to the > > same > > location in a memory at exactly the same time. > > Well, let's for a moment forget about the implementation details: > What is it you expect as a result after several sources have written different data "simultaneously" into the > same location? Last man wins? But who is last ? > > Peter Alfke Let me make a clarification, when i say data could be written simultaneosly i want data at that location increamented by the value of output data from component(s). So let say if the memory location FF has a value 5 in it. 13 out of 16 components could be trying to increament location FF with their particular output. In software you make them wait by using a semaphore. What could be a very fast way of doing that in Logic.Article: 50672
Tom Hawkins wrote:
>
> I don't think Xilinx ever supported LPM and I suspected Altera
> gave up on it too. But I am curious if most synthesis tools accept
> EDIF LPM as a valid input?
Xilinx never did, but lpm style code for dual port ram and fifos
is converted correctly by the synthesis vendors to either brand A or X.
> I've developed a set of tools that generate hdl from another language.
> The problem I am encountering is keeping the generated hdl code independent
> from both the target platform and the downstream synthesis tool.
>
> The main problem is RAM and ROM inference. It's been my experience that
> synthesis tools are fairly picky about hdl coding styles for inferring
> memory. Plus, the number of options and memory types on modern fpgas
> further complicates the issue.
>
> I was hoping LPM could be a solution.
It's a hint, not a solution. Read the source code.
It contains the least common denominator for A and X at least.
-- Mike Treseler
Article: 50673Read this. It say the Cadtrax patent was really all about inventing the frame buffer. They went to court and won after IBM and Apple licensed the technology. The bottom line is _nobody_ pays out a license just because. From what I have seen is a company would rather spend a million dollars not to pay _any_ kind of license fee. From what I've seen big companies will stomp on your head and put you out of business before they license anything from a small company. It's seen as a weakness if somebody else has done something in your space before you do. If you license it then your competitor can license it and _nobody_ wants that. http://www.swiss.ai.mit.edu/6805/articles/int-prop/heckel-debunking.html Steve "Austin Franklin" <austin@da98rkroom.com> wrote in message news:uvsn8dhdmb6odb@corp.supernews.com... > Steve, > > That's not always true. They only paid out $25k BTW, from what I > understand. > > Sometimes it is simply cheaper and easier to make an out of court > settlement, then to pay the lawyers to then take the chance of losing the > suit. > > Austin > > "Steve Casselman" <sc@vcc.com> wrote in message > news:VErL9.942$PA7.62014598@newssvr15.news.prodigy.com... > > I doubt that this patent is "bogus." After all from what I understand > > Autodesk had to pay up. I'm sure Autodesk had good laywers. I'm sure if it > > were true that it was in wide use before it was filed then the Autodesk > > laywers would have pointed that out. What is more likely is that one of > the > > 32 claims are valid and Autodesk was forced to pay. So while it seems > that > > it might be "bogus" nobody pays out money without going into court and > > "proving" the validity one way or the other. > > > > Steve > > > > > > "Austin Franklin" <austin@da98rkroom.com> wrote in message > > news:uvpinunbau1m12@corp.supernews.com... > > > > > It appears that it is NOT the XOR operator that is patented, but using > it > > > for screen cursors, and yes, though apparently "upheld", is a completely > > > bogus patent, IMO, and I am amazed it was upheld. The patent was filed > > many > > > years after people had been using this technique, and not by the person > > who > > > actually used it first. > > > > > > It's apparently patent # 4,070,710 granted in 1978.... > > > > > > > > >Article: 50674
alison wrote: > > So let say if the memory location FF has a value 5 in it. 13 out > of 16 components could be trying to increament location FF with their > particular output. In software you make them wait by using a semaphore. > What could be a very fast way of doing that in Logic. So what's the shortest possible time between two inputs from the same source? And when you say "increment" do you mean increment or accumulate? And how many locations do you have to serve? Parameters like these make a lot of difference in a hardware implementation. Peter Alfke
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