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Kevin Neilson wrote: > When using Synplify, you have to specify the initial contents twice: using > defparams (for the simulator) and using comments (for Synplify). Synplify > won't read the defparams for RAM initialization. I think XST works exactly > the same way, according to this solution on the Xilinx website: Try Synplify 7.2.2, it supports defparams as a way to send properties on black boxes into the EDIF. This way you don't have to duplicate the INIT info. It should work for both synthesis and simulation. > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= > 1&getPagePath=10695 > > -Kevin > > "Paulo Dutra" <paulo@xilinx.com> wrote in message > news:3E665040.225B2306@xilinx.com... > >>The RAMB models use the Verilog "parameter" to initialize the INIT >> > strings. > >>Since defparams are based on the scope hierarchy, you would need to know >>the location of the Rambs in your design. >> >>This would work for synthesis/simulation, as XST does read defparams. >> >> >>>$readmem would work for simulation, but not synthesis. The only >>>synthesizable way to initialize a blockRAM in a Xilinx that is is to use >>>comments or a particular syntax that the synthesizer passes on to the >>>place&route tool. The FPGA synthesizers aren't yet smart enough to use >>>$readmem; they just ignore it completely. >>> >>-- >>/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) >>\ \ ` Xilinx hotline@xilinx.com >>/ / 2100 Logic Drive http://www.xilinx.com >>\_\/.\ San Jose, California 95124-3450 USA >> > >Article: 53251
I'm with Mike on this one.... A good job shop can follow the design constraints and do a better job because they know the tools inside and out. They use them every day. I am getting 2 boards done for me starting Monday, and they will be perfect and done by Wednesday. Granted, they are much simpler, but I can sleep at night knowing I will make schedule. \/\/\/\\/ That said, if the original poster is going to do it himself, take the high speed pcb design course at UC Berkeley taught by Lee Ritchey. Or contract his firm for advice. Clyde Mike Treseler wrote: > Nicholas C. Weaver wrote: > > I'm in the very VERY preliminary planning stages, and looking to do > > one or more FPGA board designs with multiple Gb (1000-baseSX) ports & > > tranceivers. Thus there will be multiple 1.25 gigabaud differential > > pair traces running around, between the FPGA and the transcievers. > > > > Whats the general (rough order ballpark) figure for an ousourced > > design consisting of an FPGA, 8 transceivers, a DDR SO-DIMM slot, and > > a compact flash/bootup? > > If you mean a pwb layout from an existing schematic netlist, I would > guess about $10K. > > > Similarly, if doing it in-house, what are the prefered tool-suites? > > Is it the cadence branded tools? The cadence buyout ORCAD flow? > > Mentor Graphics flow? > > The preferred tools are the ones you have already used successfully. > > Consider taking a preliminary schematic to a layout contractor. > > -- Mike TreselerArticle: 53252
Peter Alfke wrote: > See my comments: > > "Theron Hicks (Terry)" wrote: > > > > > Peter, > > I don't seem to have been bitten by this problem yet, but I would rather > > not be bitten either so could I get a few clarifications please.... > > > > 1. How do you define a flipflop vs a latch? > > Is a latch a register with a level sensitive strobe? > > What is a flip-flop then? To me a Flip-flop is, for example, a pair of > > cross-coupled nand or nor gates (R-S flip-flop), or else a J-K, toggle, or > > D-type (edge sensitive.) Is the definition here different? > > I beg to differ. > In my book > A latch is a single-rank device, e.g. two cross-coupled gates, where the > output change is directly affected by an input change while the latch > is transparent. > A flip-flop changes it output only as a result of the clock edge. Data > input changes never change the output directly, a flip-flop is never > transparent. (This ignores the asynchronous preset and clear inputs). Apparently I mis-remembered. I was thinking of the really old CD4000 series and I thought that the 4043 and 4044 were listed as R-S flipflops. I checked all the data sheets I could find and they were _latches_ in all cases (as you said). That clears up the confusion. I guess old age is coming to me too soon. (The reference to the CD4000 series should really show my age. For those who don't remember, CD4000 logic used a 5 micron process that could run with up to a 15 volt supply. We used it on one of my first electronic jobs in the late 1970's. It was incredibly slow. The fastest part was the CD4013 D Flip-Flop which could toggle at an incredible 12 Mhz.) Theron > > > > > 2. Why are latches bad? Is it due to timing of clock distribution? > > Because they are transparent. You can send a race condition through the > latch, and you should not feed the latch output back to its input. > "Toggle latch" would be a contradiction in terms. > > > > 3. Can you point me at some examples of pitfalls and advantages? (Really I > > would like to just find them here, but I am not that lazy.) > > > > 4. How does one stay out of trouble with latches? > > > > 5. Are you saying, "Stick with edge sensitive devices, not level sensitive > > devices"? If I understand correctly, you really want us to stick with one > > clock domain and thus one clock frequency throughout the device, if at all > > possible, right? > > Well, that is the safe way, everything else is more risky. > BTW, all "registers" and "flip-flops" (in my book) are edge sensitive. > Level-sensitive "ones-catching" flip-flops died in the early seventies. > > Peter Alfke > > > >Article: 53253
My solution is to use JBits XHWIF as the interface between the PC and FPGA. You can easily read the data from the BRAM to the PC by the getBram methods. Terrence "Michael Wrighton" <wrighton@ieee.org> wrote in message news:d2e340ce.0303071526.48c9c9b@posting.google.com... > Hi, > I'm trying to figure out if there's a bit of IP out there that can > solve my problem before write my own solution: > > I'd like to put together a design with a block RAM, initializing it > from a ASCII file. At the end of simulation (or possibly several times > during simulation), I'd like to be able to write out the contents of > the memory to a text file (in the same format that I read them in, > ideally). > > I already know I can easily put a COE file into the VHDL that Xilinx > COREGEN produces, but I'm having trouble finding the bit to handle > writing out the file. > > My reason for doing this is that I'd like to demonstrate that the > significant part of my design works before I try to interface the > other half of of the DP memory to Ethernet via a Microblaze processor. > > I'd appreciate any help. > > Thanks, > -michaelArticle: 53254
Does the ByteBlasterMV download cable support the Cyclone EP1C6 configured with 3.3V I/O? For configuration through JTAG port? For SignalTAP (connected to JTAG port)? For configuration in AS mode? For programming of serial config device (EPCS1S18)? Rgds, KurtArticle: 53255
Peter Alfke wrote:
> Peter,
> go to the library or on the web, and RTFM ( Read The Manuals ). Might
^^^^?^^^^^^^^^^^
Sorry Peter, for all you're a great asset to this NG this really does
betray a rare lack of bottle ... as we say in the UK ... and you missed
a great chance to improve the OP's vocabulary.
Article: 53256There is a commercial device which does just that: A PCMCIA card that connects to an IDE drive. If you need a -small- quantity (one or two) contact me off-line. SH On Wed, 5 Mar 2003 11:10:36 +0100, "Brazil" <a.solinasNOSPAM@tiscali.it> wrote: >Dear all, >I would connect an hard-drive to the PCMCIA interface of my board. >Is there anybody that can suggest how to do with a simple fpga? >I know that a Fpga is too much but we would use to do other interfaces for >the board. >Thanks in Advance >Regards Brazil >Article: 53257
I use a 9-pin connector that matches the pinout of the Xilinx DLC4. I always use the manufacture's download pod for prototypes, but that's just the way I do things. In production, I make it match what ever hardware the assembly house uses. Your idea works too. Just make the download port on your PCB match whatever programming hardware you have. SH On Fri, 07 Mar 2003 22:46:21 +0100, TigerMole <none@nowhere.de> wrote: > >>I use now the Altera Bteblaster pinout for the JTAG header, even with the >>XILINX parallel cable. At least a little bit of interoperability. > >I have seen 4 different pinouts for a 10 pin headers now. >So it is true that there is no standard ? > >Isn't it strange, that Xilinx does not make a >suggestion ? > >Some are using the Atmel header: >MISO->TDO >SCK->TCK >/RESET->TMS >MOSI->TDI > >how about that ? > >TigerMole > > >Article: 53258
> john jakson wrote: > > > HandelC is a tool that lets C programmers who don't usually know much > > about HW design & architecture turn C into HW. Since this can only > > really be done on FPGA, they end up here. So we end up teaching basic > > HW 101 lessons for free. > > But the same point remains, if you think in software, and write Handel > C, you may well produce something that synthesises, but will it do what > you want, and in a reasonably efficient manner? Who knows. If you > think in hardware, and write Handel-C accordingly, you could probably > create circuits of great beauty. But then you could probably do that in > VHDL anyway... > There are other options to high-level logic design than just imperative programming languages. Our language, Confluence, combines the dataflow principles of HDL with the expression level of declarative functional programming. Unlike Handel C, where a program describes the behavior of a system, a Confluence program is an algorithm, or generator, that constructs an architecture from a set of logic primitives. Like HDL, this approach still forces the designer to think in terms of components and dataflow, rather than sequential algorithms. The resulting RTL is a direct translation of your specified logic structure; it's not an embedded machine to emulate a sequential process. Though Confluence is still a proprietary language, our company has little overhead so we can afford to provide our tools at low cost (students and universities receive cf for free). Give cf a try; you may like it! Regards, Tom -- Tom Hawkins tom1@launchbird.com Launchbird Design Systems, Inc. http://www.launchbird.com/Article: 53259
On Fri, 07 Mar 2003 23:39:35 -0500, "Theron Hicks (Terry)" <hicksthe@egr.msu.edu> wrote: > > >Peter Alfke wrote: > >> See my comments: >> >> "Theron Hicks (Terry)" wrote: >> >> > >> > Peter, >> > I don't seem to have been bitten by this problem yet, but I would rather >> > not be bitten either so could I get a few clarifications please.... >> > >> > 1. How do you define a flipflop vs a latch? >> > Is a latch a register with a level sensitive strobe? >> > What is a flip-flop then? To me a Flip-flop is, for example, a pair of >> > cross-coupled nand or nor gates (R-S flip-flop), or else a J-K, toggle, or >> > D-type (edge sensitive.) Is the definition here different? >> >> I beg to differ. >> In my book >> A latch is a single-rank device, e.g. two cross-coupled gates, where the >> output change is directly affected by an input change while the latch >> is transparent. >> A flip-flop changes it output only as a result of the clock edge. Data >> input changes never change the output directly, a flip-flop is never >> transparent. (This ignores the asynchronous preset and clear inputs). > >Apparently I mis-remembered. I was thinking of the really old CD4000 series and I >thought that the 4043 and 4044 were listed as R-S flipflops. I checked all the data >sheets I could find and they were _latches_ in all cases (as you said). That clears >up the confusion. I guess old age is coming to me too soon. (The reference to the >CD4000 series should really show my age. For those who don't remember, CD4000 logic >used a 5 micron process that could run with up to a 15 volt supply. We used it on >one of my first electronic jobs in the late 1970's. It was incredibly slow. The >fastest part was the CD4013 D Flip-Flop which could toggle at an incredible 12 Mhz.) The 4000 series parts are still available. I would still use them in new designs, if I was interested in the lowest possible current from a 9V battery. I can't think of any other reasons for using them in new designs though. Regards, Allan. >Theron > >> >> > >> > 2. Why are latches bad? Is it due to timing of clock distribution? >> >> Because they are transparent. You can send a race condition through the >> latch, and you should not feed the latch output back to its input. >> "Toggle latch" would be a contradiction in terms. >> > >> > 3. Can you point me at some examples of pitfalls and advantages? (Really I >> > would like to just find them here, but I am not that lazy.) >> > >> > 4. How does one stay out of trouble with latches? >> > >> > 5. Are you saying, "Stick with edge sensitive devices, not level sensitive >> > devices"? If I understand correctly, you really want us to stick with one >> > clock domain and thus one clock frequency throughout the device, if at all >> > possible, right? >> >> Well, that is the safe way, everything else is more risky. >> BTW, all "registers" and "flip-flops" (in my book) are edge sensitive. >> Level-sensitive "ones-catching" flip-flops died in the early seventies. >> >> Peter Alfke >> > >> >Article: 53260
Hi, I need to use a SpartanII-E device to receive a TTL 5V signal. I read in the xilinx answer database that the fpga is 5V tolerant provided a 100 ohm current limiting resistance in series with the pad. (http://www.xilinx.com/products/virtex/techtopic/vtt002.pdf) However, they say that : 'A 5V device can drive a standard Virtex-E I/O pin (excluding GCLK, MODE, and JTAG pins)'. Does this mean that I can't clock the fpga with a 5V input clock? In the pin description datasheet, it seems to me that the DLL pin could be used as a clock input: (http://direct.xilinx.com/bvdocs/publications/ds077_4.pdf) ''GCK0, GCK1, GCK2, GCK3 : Input Clock input pins that connect to Global Clock buffers or DLL inputs. These pins become user inputs when not needed for clocks. DLL : Input Clock input pins that connect to DLL input or feedback clocks. Differential clock input (N input of pair) when paired with adjacent GCK input. Becomes a user I/O when not needed for clocks.'' Am I right or only the GCKx can be used as clock input? Thank you very much DavidArticle: 53261
David, The best thing to do is to put a resistor divider at the source of the clock, then run the trace to the GCK input. The values of the resistor divider can be selected to give you the proper driving impedance (set to the characteristic impedance of the clock trace), and also to give you the proper Vih(max) at the GCK pin. Typically, I use a 33ohm series/150ohm to ground as the divider network -- when I need to go from LVTTL (3.3V) down to LVCMOS25 (2.5V). The output impedance of my clock driver, along with the 33/150 divider, gets close to the characteristic impedance of the clock trace (50ohms). Bob "David" <gretzteam@hotmail.com> wrote in message news:LQqaa.48534$RX1.457305@wagner.videotron.net... > Hi, > I need to use a SpartanII-E device to receive a TTL 5V signal. I read in the > xilinx answer database that the fpga is 5V tolerant provided a 100 ohm > current limiting resistance in series with the pad. > (http://www.xilinx.com/products/virtex/techtopic/vtt002.pdf) However, they > say that : 'A 5V device can drive a standard Virtex-E I/O pin (excluding > GCLK, MODE, and JTAG pins)'. > Does this mean that I can't clock the fpga with a 5V input clock? In the pin > description datasheet, it seems to me that the DLL pin could be used as a > clock input: (http://direct.xilinx.com/bvdocs/publications/ds077_4.pdf) > ''GCK0, GCK1, GCK2, GCK3 : Input Clock input pins that connect to Global > Clock buffers or DLL inputs. These pins become user inputs when not needed > for clocks. > > DLL : Input Clock input pins that connect to DLL input or feedback clocks. > Differential clock input (N input of pair) when paired with adjacent GCK > input. Becomes a user I/O when not needed for clocks.'' > > Am I right or only the GCKx can be used as clock input? > > Thank you very much > > David > > > >Article: 53262
"David" <gretzteam@hotmail.com> wrote in message news:<LQqaa.48534$RX1.457305@wagner.videotron.net>... > Hi, > I need to use a SpartanII-E device to receive a TTL 5V signal. I read in the > xilinx answer database that the fpga is 5V tolerant provided a 100 ohm > current limiting resistance in series with the pad. > (http://www.xilinx.com/products/virtex/techtopic/vtt002.pdf) However, they > say that : 'A 5V device can drive a standard Virtex-E I/O pin (excluding > GCLK, MODE, and JTAG pins)'. > Does this mean that I can't clock the fpga with a 5V input clock? In the pin > description datasheet, it seems to me that the DLL pin could be used as a > clock input: (http://direct.xilinx.com/bvdocs/publications/ds077_4.pdf) > ''GCK0, GCK1, GCK2, GCK3 : Input Clock input pins that connect to Global > Clock buffers or DLL inputs. These pins become user inputs when not needed > for clocks. > > DLL : Input Clock input pins that connect to DLL input or feedback clocks. > Differential clock input (N input of pair) when paired with adjacent GCK > input. Becomes a user I/O when not needed for clocks.'' > > Am I right or only the GCKx can be used as clock input? I have used the DLL pins as clock inputs and as feedback inputs for my DLLs. My FAE didn't even know the things existed until I found a bug in the tools (it wasn't always using the dedicated routing for them). I assume the bug is fixed in 4.2 and 5.1, but I now put a MAXDELAY of 1 ns on all my clock inputs just to make sure. MarcArticle: 53263
Tomas wrote: > Hi all, > > I am considering the future hardware platforms for our designs. As our > groups have a wide experience with unix environments (we have been > using Solaris for a while, now), we would like to continue in this > world. > What I am mostly curious about is the feasibility of Mac based FPGA > design. Mac Os X is a nice and SUPPORTED Unix OS, and the Xservers > from Apple are not too expensive compared to equivalent Intel boxes... > And with the rumored advent of the 970 chips from IBM they might > become even more interesting. Icarus Verilog supports Mac OS X just fine, although I rely on others if Mac specific problems come up. GTKWave is also known to work on MacOSX, for waveform viewing. Implementation tools (par, map) will never show up on MaxOSX. Keep a Linux or Solaris box around for that. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 53264
OK, one question regarding the Latch used in your TechXclusives example "Asynchronous FIFO in Virtex-II™ FPGAs". You show a pair of cross-coupled gates as the "direction" indicator (latch). If I write VHDL in exactly that style (2 gates), will XST correctly infer a latch from this, and instantiate a LD part (which, I assume, is the proper embodiment), or will it infer two gates (ie LUTs) and cross couple them (which, I assume, is deprecated)? Should I explicitly instantiate the LD? Peter Alfke <peter@xilinx.com> wrote: :See my comments: : :"Theron Hicks (Terry)" wrote: : :> :> Peter, :> I don't seem to have been bitten by this problem yet, but I would rather :> not be bitten either so could I get a few clarifications please.... :> :> 1. How do you define a flipflop vs a latch? :> Is a latch a register with a level sensitive strobe? :> What is a flip-flop then? To me a Flip-flop is, for example, a pair of :> cross-coupled nand or nor gates (R-S flip-flop), or else a J-K, toggle, or :> D-type (edge sensitive.) Is the definition here different? : :I beg to differ. :In my book :A latch is a single-rank device, e.g. two cross-coupled gates, where the :output change is directly affected by an input change while the latch :is transparent. :A flip-flop changes it output only as a result of the clock edge. Data :input changes never change the output directly, a flip-flop is never :transparent. (This ignores the asynchronous preset and clear inputs). :> :> 2. Why are latches bad? Is it due to timing of clock distribution? : :Because they are transparent. You can send a race condition through the :latch, and you should not feed the latch output back to its input. :"Toggle latch" would be a contradiction in terms. :> :> 3. Can you point me at some examples of pitfalls and advantages? (Really I :> would like to just find them here, but I am not that lazy.) :> :> 4. How does one stay out of trouble with latches? :> :> 5. Are you saying, "Stick with edge sensitive devices, not level sensitive :> devices"? If I understand correctly, you really want us to stick with one :> clock domain and thus one clock frequency throughout the device, if at all :> possible, right? : :Well, that is the safe way, everything else is more risky. :BTW, all "registers" and "flip-flops" (in my book) are edge sensitive. :Level-sensitive "ones-catching" flip-flops died in the early seventies. : :Peter Alfke :> :>Article: 53265
Allan Herriman wrote: > <snip> > The 4000 series parts are still available. > I would still use them in new designs, if I was interested in the > lowest possible current from a 9V battery. > > I can't think of any other reasons for using them in new designs > though. Power consumption and noise immunity / RFI ? A 40106 can give much lower ICC when driven from slow edges than HC/AHC devices. A 4069 will give a lower current XTAL osc than a HCU04, at the lower frequencies. A 4541 is a good low power, low cost, long timebase wdog/timer device. Their low drive, and slow edges, plus ability to ignore narrow pulses also make them good choices for interface aplications. -jgArticle: 53266
As part of a computer engineering senior project at NJIT (http://www.njit.edu), I am interested in extending an existing microcontroller or microprocessor core. The motivation behind the project is to implement an instruction reuse buffer, as described in http://www.ac.upc.es/homes/antonio/postscript/ics99.rcb.ps.gz . (Basically the paper describes a mechanism to exploit value locality within instruction streams.. kind of like an ALU result cache.) Given that the project time frame is approximately 7-8 months (in groups of two), can anyone recommend an open, online core in which to work with? Ideally, it would have the following: * Multi-cycle arithmetic instructions (must take longer than a buffer access). * Relatively simple design (no PIIIs please :) * Preferably VHDL, implemented in Xilinx or Altera FPGA * A few benchmark programs would be nice, but this could be coded myself I have browsed opencores.org, free-ip.com, etc. and have found a few interesting candidates, but was looking for a few opinions and suggestions here.Article: 53267
Hello all,
I am using Spartan 200K to synthesize my design. I am using
XST as the synthesis tool. In my Verilog code I have instantiated the
RAMB4_2S, which is the available block RAM for Spartan. When I use the
Graphical Interface of XST, the tool is able to infer block RAMs
RAMB4_2S. When I run the synthesis in command line, the tool gives an
error saying RAMB4_2S instance not found. I have given the sythesis
constraint -ram_extract YES and -ram_style BLOCK. I tried to give the
path for Xilinx library files but these files are behavoiral models
and hence not synthesizable. Can someone give a suggestion of how to
make the tool infer the RAM macro when I synthesize in command line.
Anbudan,
Anand~
Article: 53268Hi all, Absolute newbie to Fpga's, I am looking at building a high speed 3D router/engraver, based on step & direction input AC servo's. I'm looking for what is essentially a variable frequency pulse generator, from 1 to about 600Khz, a few 32 bit counters, acceleration generation, linear & circular interpolation , a few inz and outz for limit switches etc, There are plenty of motion control ASIC vendors out there but none of them seem to be just what i need. Is an Fpga implementation for this type of function possible ? are there any vendors that do this sort of stuff ? Any help / advice would be most welcome. Thanks. Martin Vellemax.Article: 53269
Hakon Lislebo <haklis@hotmail.com> wrote: > transmission or whatever it does. Personally I intend to make an > auto-reset based on the status signals from the DLL. In most Don't depend on the locked signal from the DLL to tell you when the DLL is really locked or not. Chances are that it will stay high if the DLL loses lock. I'm not sure if this is true of the Virtex-II DCM but it's no secret for the Virtex-E DLL. You could still monitor the clock output and make decisions using another (non-DLLed) clock. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 53270
Ken, That would be great, but I'm not sure how it works. I found an old design in which I initialize blockRAM using both defparams and the 'xc_props' comments, and I deleted the comments and synthesized on 7.2.2. I found that there were no initialization data in the EDIF netlist when I did that, but that the init data reappeared when I put the comments back in. Am I doing something incorrectly? I couldn't find any hints on the Synplicity website or in the release notes. -Kevin "Ken McElvain" <ken@synplicity.com> wrote in message news:3E694B85.1070406@synplicity.com... > > > Kevin Neilson wrote: > > > When using Synplify, you have to specify the initial contents twice: using > > defparams (for the simulator) and using comments (for Synplify). Synplify > > won't read the defparams for RAM initialization. I think XST works exactly > > the same way, according to this solution on the Xilinx website: > > > Try Synplify 7.2.2, it supports defparams as a way to send properties on > black boxes into the EDIF. This way you don't have to duplicate the > INIT info. It should work for both synthesis and simulation. > > > > > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= > > 1&getPagePath=10695 > > > > -Kevin > > > > "Paulo Dutra" <paulo@xilinx.com> wrote in message > > news:3E665040.225B2306@xilinx.com... > > > >>The RAMB models use the Verilog "parameter" to initialize the INIT > >> > > strings. > > > >>Since defparams are based on the scope hierarchy, you would need to know > >>the location of the Rambs in your design. > >> > >>This would work for synthesis/simulation, as XST does read defparams. > >> > >> > >>>$readmem would work for simulation, but not synthesis. The only > >>>synthesizable way to initialize a blockRAM in a Xilinx that is is to use > >>>comments or a particular syntax that the synthesizer passes on to the > >>>place&route tool. The FPGA synthesizers aren't yet smart enough to use > >>>$readmem; they just ignore it completely. > >>> > >>-- > >>/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) > >>\ \ ` Xilinx hotline@xilinx.com > >>/ / 2100 Logic Drive http://www.xilinx.com > >>\_\/.\ San Jose, California 95124-3450 USA > >> > > > > >Article: 53271
Hi, I am using HDL Design Browser that comes with FPGA Advantage(Mentor Graphics). In that I think we need to, for a new project, create a new library called work or temp and add all the vhdl source files to it. Also we need to add our own personal library to the above library as a child. Also we need to add the stardard libraries like mgc_portable to our project library as a child. So can anyone tell me how do I do that because when I try to add mgc_portable it gets opened as an independent library and not as a child of library work/temp. When I try to compile my project(design) with mgc_portable not as a child of work using ModelSim it gives error saying that the library mgc_portable not found. So someone please really help me. I am using FPGA Advantage for the first time and am stuck at this point since 4 days. Thank You, AbdulmoeedArticle: 53272
"Bob" <nimby1_not_spmmm@earthlink.net> wrote in message news:JNsaa.9090$gF3.920217@newsread1.prod.itd.earthlink.net... > David, > > Typically, I use a 33ohm series/150ohm to ground as the divider network -- > when I need to go from LVTTL (3.3V) down to LVCMOS25 (2.5V). The output > impedance of my clock driver, along with the 33/150 divider, gets close to > the characteristic impedance of the clock trace (50ohms). Isn't 18mA allot of current to expect a logic line to source? RalphArticle: 53273
In preping a nice "Motherhood and Apple Pie" fpga slide (showing, among other things, how FPGAs are scaling better that microprocessors, how they have shifted to a fab-leadership position, etc), I need to know the intro dates/sizes/marketing clock rate/process for the product history of either Xilinx or Altera. Intel has a very nice product timeline (http://www.intel.com/pressroom/kits/quickreffam.htm) Before I start digging through old press releases/datasheets etc, does there exist a similar timeline for either Xilinx or Altera? Thanks. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 53274
On Sun, 09 Mar 2003 00:57:34 -0800, =·MoLe= wrote: > Hi all, > > Absolute newbie to Fpga's, I am looking at building a high speed 3D > router/engraver, based on step & direction input AC servo's. I'm > looking for what is essentially a variable frequency pulse generator, > from 1 to about 600Khz, a few 32 bit counters, acceleration generation, > linear & circular interpolation , a few inz and outz for limit switches > etc, There are plenty of motion control ASIC vendors out there but none > of them seem to be just what i need. Is an Fpga implementation for this > type of function possible ? are there any vendors that do this sort of > stuff ? > > Any help / advice would be most welcome. > > Thanks. > > Martin Vellemax. Certainly do-able in a small FPGA. We've done some multi-axis DC servo controllers (up tp 8 axis) in 200K SpartanII. If all you need is step and direction (we are doing PID+feedforward) it should be quite easy, plus you dont need to worry about long term ASIC availability... Peter Wallace
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