Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"H.L" <alphaboran@yahoo.com> wrote in news:9v1rij$2oa5$1@ulysses.noc.ntua.gr: > Hello all, > i just installed xilinx ise 4. I decided to run the tutorial but when i > create a new project (named tutorial) i have a big problem : the ONLY > design flow i can select is the EDIF, i want to use the XST VHDL > design flow fot the tutorial's purposes but its absent. Can anyone help > me? > > Harris L. > > > What kind of device have you choosen ? XST vhdl is not valid for XC9500-family CPLDs for example. If you have installed the Alliance ISE4.1i youn dont't have vhdl support at all. You must have the Foundation ISE4.1i. -- -- Kind regards, -- Tobias Stumber, Robert Bosch Gmbh, Leonberg GermanyArticle: 37451
FPGAs positioned as a co-processor can accelerate software bottlenecks by executing in parallel. Sometimes you can find processes of an FPGA design that by their nature are sequential. These processes can therefore be executed by the microprocessor. Best of both world's I guess Noel sacrosantus@yahoo.com (Dennis) wrote in message news:<24f80317.0112110215.4b06c7ec@posting.google.com>... > sacrosantus@yahoo.com (Dennis) wrote in message news:<24f80317.0112100326.7f6c2a3b@posting.google.com>... > > Can the Community help me in understanding the basis for the Choice of > > Processor Cores in FPGAs(Both embedded & soft) for different kinds of > > applications? > > > > Dennis Richards > > > > And Most Importantly WHY????? > > DennisArticle: 37452
This is a non-problem: 1. Use the DLL, or 2. use a simple design that gives 2:1 duty cycle, or 3. use the XCell design and ignore the simulation complaint ( it is meaningless). So many choices... Peter Alfke Banana wrote: > I've already tried to implement this circuit : > > http://www.xilinx.com/xcell/xl33/xl33_30.pdf > > but how it is described in the article, it could have some glitch > problem during simulation phase and in fact I've it using Aldec 5.1 . > Can you explain me better how I can implement your idea in vhdl ??? > > ThanksArticle: 37453
Hi all, thank's a lot for all of your help suggestions ideas. I 'catched' it! Well, as it can happen, it was not what I expected. The DPM being sourced by two clock domains works as expected. The problem is in the DSP interface from Analog Device and in the fact that a burst read can be interrupted from this DSP making it necessary to add some enable disable logic for my data read out pipeline. The DSP is the ADSP-21161N from Analog Device. Up to now I only expected a pipeline fill latency of two clocks. After this furhter reads have been expected. However now I need to enable disable the clocking of the read out pipeline I order not to 'loose' some values ... I don't know if I made myself clear, maybe not. However concerning the Spartan-II I do have some additional questions. How can I constraint a Fast Mode for the IOB's in the user constraint file? How can I define a max output enable time in the user constraint file for a data output port? All the best markus thank's for all of "Markus Meng" <meng.engineering@bluewin.ch> schrieb im Newsbeitrag news:3c121b73_3@news.bluewin.ch... > Hi all, > > We are using the Block RAM's inside the Spartan-II device > in order to get a synchronous true dual-ported RAM buffer. > > The block RAM buffer clocks are being sourced from two different > clock domains. > > When using the design in real word we get sometimes 'data-flicker' on the > data we push from one clock domain to the other, not always, > only sometimes. As a second test we put in values on one side PortA > using a staircase generator - well a counter -. On PortB of the block RAM > we read out the the 'staircase'. However sometimes we see something like > an interference, a modulation on top of our digital generated staircase, > maybe > once per thousand scans. The dual ported synchronous RAM we generated > with the CoreLoigc tool from Xilinx using version 3.1i. Those are really > true > dual-ported, right ?? The clocks are really asynchronous to eatch other ... > > The question: How to you have to apply timing constraints for the block > ram, or is it not needed? Actually we did constraint the two clocks. Is that > enough, or is there a need for an additional block ram constraint ?? > > clk ist the clock for PortA > dsp_clock is the clock for PortB > > Reading and writing does interleave, but not an the same address ... > > NET "clk" TNM_NET = "clk"; > TIMESPEC "TS_CLK" = PERIOD "clk" 40 MHz HIGH 50 %; > > NET "chk_clk" TNM_NET = "chk_clk"; > TIMESPEC "TS_CHK_CLK" = PERIOD "chk_clk" 55 MHz HIGH 50 %; > > > Any idea how to furhter find the reason for the problem? > > thanks in advance > > markus > > -- > ******************************************************************** > ** Meng Engineering Telefon 056 222 44 10 ** > ** Markus Meng Natel 079 230 93 86 ** > ** Bruggerstr. 21 Telefax 056 222 44 10 ** > ** CH-5400 Baden Email meng.engineering@bluewin.ch ** > ******************************************************************** > ** Theory may inform, but Practice convinces. -- George Bain ** > > > > > >Article: 37454
Hi, This error message is driving me nuts: ERROR:NgdBuild:604 - logical block 'ddr_ctlr/clk_dll1/dll_u' with type 'DCMZ0' is unexpanded. Symbol 'DCMZ0' is not supported in target 'virtex2'. I have a DCM component in my design (VHDL) and I use Synplify to generate the netlist (edif) for the Xilinx ISE. Somewhere along this path the DCM turns into DCMZ0 and I get the error message from the ISE tool. I searched xilinx answer records but got nowhere, did anybody run into this? Thanks, jakabArticle: 37455
"MH" <blahblah@blahblah.blah> wrote in message news:<3c15de13$0$8505$cc9e4d1f@news.dial.pipex.com>... > "Kurt" <kdu@quantum3d.com> wrote in message news:1683007b.0112101717.72f9819b@posting.google.com... > > I heard that there is a $3995 special promotion for Synplicity's > > Synplify? FPGA synthesis solution. What is the difference between this > > special promotion and the 'full' version. > > Kurt, > > Where did you hear about this special promotion? > I can't find any information on the website.... > > Thanks > > MH http://www.synplicity.com/products/Xilinx.htmlArticle: 37456
Thank you all. Rick Filipkiewicz <rick@algor.co.uk> wrote in message news:<3C160E9A.55A3E9DD@algor.co.uk>... > "S. Ramirez" wrote: > > > Kurt, > > The $3995 version is a one year, node-locked license that is > > non-renewable and expires at the end of the year 2002. It does not come > > with HDL Analyst, which in my opinion is invaluable for large, complex > > designs. To get HDL Analyst, it costs $4,995. I think this is a steal, > > since 50% of the purchase price can be applied to a new and possibly > > different license the following year. > > It sounds to me that Synplicity recognizes that companies are strapped > > for cash, and this low price allows us to use Synplify. Then in one year, > > when the economy rebounds and everyone is spending again (yeah!), we can opt > > for a permanent license while still applying 50% of this year's license to > > the new product. > > We have Synplicity and it is the best synthesizer that we've run > > across. I am amazed at how inventive companies are to weather this economic > > downturn. > > Simon Ramirez, Consultant > > Synchronous Design, Inc. > > Oviedo, FL USA > > > > "Kurt" <kdu@quantum3d.com> wrote in message > > news:1683007b.0112101717.72f9819b@posting.google.com... > > > I heard that there is a $3995 special promotion for Synplicity's > > > Synplify? FPGA synthesis solution. What is the difference between this > > > special promotion and the 'full' version. > > > > > > Anybody knows? > > > > > Beware: node-locked => you can't run Synplify from the command line using a Tcl > script.Article: 37457
"Kurt" <kdu@quantum3d.com> wrote in message news:1683007b.0112110943.77b0bcf5@posting.google.com... > > http://www.synplicity.com/products/Xilinx.html Thanks for the link. "This offer is limited to one license per site and is valid until November 30, 2001" Doh! I wish they'd told me about this a few weeks ago.... MH.Article: 37458
This is a multi-part message in MIME format. --------------D5567662786AA4322AC90FB2 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit As mentioned in a previous post, there is a TCL/Tk script availible that assists with the compilation of the ModelSim libraries for PE and SE. For information as to where to obtain and how to use this script, consult the Xilinx support website at: http://support.xilinx.com/techdocs/2561.htm -- Brian Bernd Scheuermann wrote: > Hi, > > the MXE libraries of the latest IP core update #1 are precompiled for > ModelSIM Xilinx edition only. Do you know how to compile this update in > ModelSIM SE 5.5e? > > Cheers, > > Bernd > > e-mail: scheuermann@aifb.uni-karlsruhe.de --------------D5567662786AA4322AC90FB2 Content-Type: text/x-vcard; charset=us-ascii; name="brian.philofsky.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brian.philofsky.vcf" begin:vcard n:Philofsky;Brian x-mozilla-html:FALSE adr:;;;;;; version:2.1 email;internet:brian.philofsky@xilinx.com fn:Brian Philofsky end:vcard --------------D5567662786AA4322AC90FB2--Article: 37459
This is a multi-part message in MIME format. --------------C6E57DD077367ABCD468FD37 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit It is probably in your best interest just to use the DCM simulation model provided by Xilinx in your functional simulation. There is a simulation library called the UNISIM library that contains simulation models for all Xilinx primitives including the DCM. You must first compile this library for your simulator then you simply instantiate the DCM in your code and call for the library model form this UNISIM library. If you need more infomrtaion on using this library, I suggest you consult the Xilinx Synthesis and Simulation Design Guide within the Xilinx manuals either installed on your machine or on the Xilinx website: http://support.xilinx.com/support/library.htm If that does not fix the problem or suit you, then I suggest rather than inverting the clock in an assignment or using the 180 degree output from the DCM, that you invert it at the process/always statement: VHDL: if old_clk'event and old_clk = '0' Verilog: always @(negedge old_clk) That may fix your problem and may allow inversion at the CLB level thus saving you a global clock resource and possibly some power savings as well. -- Brian David Miller wrote: > Greetings, > > I apologise for the two dupes of my last message. I had some teething > problems with my news client. > > Does anyone have any suggestions about doing functional simulations of > designs containing DCM or DLLs? > > I am not doing anything real fancy with these DCMs, only clock > mirroring, deskewing and generation of an antiphase clock, so I can > model their behaviour with two assignment statements: > > new_clk <= old_clk; > new_clk_N <= not old_clk; > > The trouble with doing this is that each net will see the edge in > different a delta, so any net manipulated by both new_clk and old_clk > will not do the expected thing because one will always appear to be one > cycle behind the other, even when they aren't supposed to be. > > Short of doing timed simulation, which on a design of this size is > infeasible, are there any tricks that can be pulled to get around this > phenomenon? > > -- > David Miller, BCMS (Hons) | When something disturbs you, it isn't the > Endace Measurement Systems | thing that disturbs you; rather, it is > Mobile: +64-21-704-djm | your judgement of it, and you have the > Fax: +64-21-304-djm | power to change that. -- Marcus Aurelius --------------C6E57DD077367ABCD468FD37 Content-Type: text/x-vcard; charset=us-ascii; name="brian.philofsky.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brian.philofsky.vcf" begin:vcard n:Philofsky;Brian x-mozilla-html:FALSE adr:;;;;;; version:2.1 email;internet:brian.philofsky@xilinx.com fn:Brian Philofsky end:vcard --------------C6E57DD077367ABCD468FD37--Article: 37460
This is a multi-part message in MIME format. --------------22A5024A807C723BF3F1A418 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit As Utku mentioned, you are looking for the UNISIM library which contains all simulation modles for front-end (RTL) simulation of Xilinx primitives includeing the RAMB4_S1_S16. That library needs to be compiled for your simulator and then mapped and referenced in your HDL code to link the library model to your simulation netlist. As mentioned in a previous post, if you need more infomrtaion on using this library, I suggest you consult the Xilinx Synthesis and Simulation Design Guide within the Xilinx manuals either installed on your machine or on the Xilinx website: http://support.xilinx.com/support/library.htm There are also tutorials and application notes on this subject availible on the Xilinx site. It may be worth your while to grab the tutorial to learn more about Xilinx simulation. -- Brian Utku Ozcan wrote: > Gyunseog Yang wrote: > > > > Hi, averybody, > > > > I must use "ramb4_s1_s16" in my Xilinx vertexE based coding. > > But I don't have the file "ramb4_s1_s16.vhd". > > I have tried to modify the any single port RAMB4, but failed. > > > > Thanks. > > > > Gyunseog. > > If you have a Xilinx tool installed in your machine, > UNIX (Sun/HP) or Winxx whatever, there should be > RAMB4_* entity/architecture codes in unisim_VCOMP.vhd in > > $XILINX/vhdl/src/unisims (for RTL simulation) > $XILINX/vhdl/src/simprims (for gate-level simulation) > > In the case of Verilog, where you can use Verilog > models of Xilinx elements in your VHDL design (if you > have mixed-language simulator like Modelsim), then > RAMB4_* Verilog models are stored in separate files, > unlike VHDL, in > > $XILINX/verilog/src/unisims (for RTL simulation) > $XILINX/verilog/src/simprims (for gate-level simulation) > > If you have any Xilinx tools installed, you must have > these directories. Otherwise, your installation is > incomplete. Please go your CAD admin. > > Utku --------------22A5024A807C723BF3F1A418 Content-Type: text/x-vcard; charset=us-ascii; name="brian.philofsky.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brian.philofsky.vcf" begin:vcard n:Philofsky;Brian x-mozilla-html:FALSE adr:;;;;;; version:2.1 email;internet:brian.philofsky@xilinx.com fn:Brian Philofsky end:vcard --------------22A5024A807C723BF3F1A418--Article: 37461
I've dealt with the LUT placement issue at times by inserting a [logically] superfluous transparent latch (always enabled, such as with RESET--correct polarity selected) that I can easily control the placement of. In the architectures that support it, of course (such as 4000XL); there is usually only a small timing penalty going through the latch, which is more than made up for by the better routing. Jason T. Wright Ray Andraka wrote: > > My biggest beef with the Xilinx placer is when there is more than one level > of logic, the placer puts the second level a long distance away regardless > of timing constraints. The first level gets placed with the associated > flip-flop (I'm numbering in reverse order so that the output of the first > outputs to the flipflop) as it should. If you place the flip-=flops, then > as long as the combinatorial logic is only one level you wind up with a good > placement. Go to a second level, and you'll have to place the LUTs too > (which is a pain compared with using a regular expression). I think that is > the most greivous of the placer sins, but there are others. >Article: 37462
Is it possible to not read in the XNF files for synthesis? I haven't
used Foundation, but I have used Alliance; the back-end tools will read
in all relevant files (xnf, ngc, etc.) it can find (i.e., they are in
the right place.)
Hippolyte Lizard wrote:
>
> Often when I synthesize (Foundation 2.1i) the XNF files of macros I use
> from the XC4000E library get corrupted, and ports disappear. Driving me
> crazy! How do I prevent?
>
> Thanks
>
> HL
--
Jason T. Wright
The opinions I express are my own ...
unless otherwise indicated!
Article: 37463
Hello there,
I'm use Mentor Leonardo and Altera Max+PlusII.
Tell me, please, how to set
initial data for RAM?
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
entity RAM is
port(A : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
RW : in std_logic);
end RAM;
architecture behavior of RAM is
signal DD : std_logic_vector (7 downto 0);
begin
DO<=DD when (RW)='1' else "ZZZZZZZZ";
process (A,DI,RW)
subtype TMemItem is std_logic_vector(7 downto 0);
type TMemData is array(Integer range 0 to 255) of TMemItem;
variable Mem : TMemData :=
("00000000","00000000","00000000","00000000",
...
"10110100","11000011","11010010","11100001");
begin
if RW='1' then
DD<=Mem(CONV_UNSIGNED(A,A'Length));
else
Mem(CONV_UNSIGNED(A,A'Length)):=DI;
DD<="ZZZZZZZZ";
end if;
end process;
end behavior;
I needed synthesized VHDL description.
Leonardo says:
"W:/vhdl/BJCards.VHD",line 457: Warning, initial value for Mem is ignored
for synthesis.
But ACEX1 EP1K50QC208 supports initializing a memory. How to explain this
for Leonardo?
Article: 37464alco wrote: > > Hello, > > I have been using a 8051 controller to program a XC9536 cpld using the JTAG > interface. I have programmed several hundreds of units in the last couple of > years without any problems, but now programming the cpld by the 8051 fails > for more than half the units produced. The PCB's do not show shorts or open > connections or other production errors. With some care the cpld (while on > the pcb) was connected to a Multilinx programming device which succesfully > programs the cpld. > > The programming algorithm on the 8051 is based on Xilinx app notes XAPP058 > and XAPP067. The CPLD fails to generate the correct TDO output for > verification after a program or erase instruction. The scope shows > appropriate XRUNTEST idle times for these instructions (640us/1300ms). TCK > period is larger than 2us. > > On the scope I compared JTAG output from the 8051 and the multilinx device. > The only real difference is that the multilinx does not instruct the cpld to > return to Run/test/idle mode after update-IR (see figure 7 in XAPP058) for > the instructions 'isp enable', 'erase' and 'program', which are then > immediately followed by a SDR instruction. > > Questions: > > - Has anything changed recently in the JTAG interface for the xc9536 that > might cause a microcontroller to fail programming the cpld. Certainly sounds like something changed. Check the date codes / mask revs, of both the PLD and 8051. Ideas : On an error device that was successfully Multilinx programmed, can you run just the verify portion of the PGM in the 8051 ? That will check all JTAG shifter HW, but avoids PGM timing, and can help split the problem. Vary the Vcc, and Vary the 8051 XTAL.. -jgArticle: 37465
The additional timing through the latch is substantial. It is better to floorplan
it. The problem with usign the grpahical floorplanner for combinatorial luts is
that synthesis often changes the names. In critical stuff, we just instantiate a
lut or an fmapped version of the logic, which seems to be about the same amount of
work and no less confusing later when the design is revisited. It is the not so
critical stuff where I don't want to be mucking about with the code (to
instantiate luts or insert other implants) that would do fine as long as the
second layer of logic was at least somewhere reasonably close. As it is, the
automatic placement seems to put second layers of logic halfway across the chip,
even if there is a ton of open space and all the gozintas and gozoutas are all
locked down close to where it should go.
"Jason T. Wright" wrote:
> I've dealt with the LUT placement issue at times by inserting a
> [logically] superfluous transparent latch (always enabled, such as with
> RESET--correct polarity selected) that I can easily control the
> placement of. In the architectures that support it, of course (such as
> 4000XL); there is usually only a small timing penalty going through the
> latch, which is more than made up for by the better routing.
>
> Jason T. Wright
>
> Ray Andraka wrote:
> >
> > My biggest beef with the Xilinx placer is when there is more than one level
> > of logic, the placer puts the second level a long distance away regardless
> > of timing constraints. The first level gets placed with the associated
> > flip-flop (I'm numbering in reverse order so that the output of the first
> > outputs to the flipflop) as it should. If you place the flip-=flops, then
> > as long as the combinatorial logic is only one level you wind up with a good
> > placement. Go to a second level, and you'll have to place the LUTs too
> > (which is a pain compared with using a regular expression). I think that is
> > the most greivous of the placer sins, but there are others.
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 37466
"MH" <blahblah@blahblah.blah> wrote in message
news:3c165132$0$227$cc9e4d1f@news.dial.pipex.com...
> Thanks for the link.
>
> "This offer is limited to one license per site and is valid until November
30, 2001"
>
> Doh! I wish they'd told me about this a few weeks ago....
>
> MH.
Ha! I bet that if you call your friendly Synplicity sales rep tonight
at 2am, he will rush down and install the software for you in 1 femtosecond!
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL USA
Article: 37467Hi, I've recently run into the problem of getting crosstalk onto a clock input due to a layout problem. I know what to do to fix the layout problem (thanks to "High Speed Digital Design"), but I'm wondering how other people deal with crosstalk in their FPGAs. Here's my situation: I have several serial inputs to my FPGA. What I had been doing was use the serial clock to clock in the data, then with my master clock, shift this data into a shift register (this way, I get the data on the proper clock edge, but use the global clock to guarantee shift register function). The problem with this is that a glitch on the serial clock screws everything up. Presumably reducing the crosstalk will eliminate the glitch, but do those out there also design your serial inputs to reduce glitch clocking? A way to do this is to require that the serial clock be at a level for at least 2 master clock edges in order to be valid (faster master clock). Or is the right approach to just eliminate the glitching? Any opinions? Thanks, -robertArticle: 37468
--------------9B33CA47F699FC628C71576F Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Robert Abiad wrote: > Hi, > > I've recently run into the problem of getting crosstalk onto a clock > input due to a layout problem. <snip>Or is the right approach to just > eliminatethe glitching? Your first attempt should always be to eliminate the glitch if at all possible, even if it costs and hurts. If you fail, then as a band-aid you can use "dirty tricks" like described in http://www.xilinx.com/xcell/xl34/xl34_54.pdf Peter Alfke, Xilinx Applications --------------9B33CA47F699FC628C71576F Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <p>Robert Abiad wrote: <blockquote TYPE=CITE>Hi, <p>I've recently run into the problem of getting crosstalk onto a clock <br>input due to a layout problem. <snip>Or is the right approach to just eliminatethe glitching?</blockquote> Your first attempt should always be to eliminate the glitch if at all possible, even if it costs and hurts. <br>If you fail, then as a band-aid you can use "dirty tricks" like described in <p><u><A HREF="http://www.xilinx.com/xcell/xl34/xl34_54.pdf">http://www.xilinx.com/xcell/xl34/xl34_54.pdf</A></u> <p>Peter Alfke, Xilinx Applications</html> --------------9B33CA47F699FC628C71576F--Article: 37469
1) What frequency is your serial clock? 2) What frequency is your master clock? 3) Are the related to master clock source or are they asynchronous to each other? If answer 3 is asynchronous, you should look at my last 3 articles. Philip. On Tue, 11 Dec 2001 15:46:13 -0800, Robert Abiad <abiad@ssl.berkeley.deletethis.edu> wrote: >Hi, > >I've recently run into the problem of getting crosstalk onto a clock >input due to a layout problem. I know what to do to fix the layout >problem (thanks to "High Speed Digital Design"), but I'm wondering how >other people deal with crosstalk in their FPGAs. > >Here's my situation: > >I have several serial inputs to my FPGA. What I had been doing was use >the serial clock to clock in the data, then with my master clock, shift >this data into a shift register (this way, I get the data on the proper >clock edge, but use the global clock to guarantee shift register >function). The problem with this is that a glitch on the serial clock >screws everything up. Presumably reducing the crosstalk will eliminate >the glitch, but do those out there also design your serial inputs to >reduce glitch clocking? A way to do this is to require that the serial >clock be at a level for at least 2 master clock edges in order to be >valid (faster master clock). Or is the right approach to just eliminate >the glitching? > >Any opinions? > >Thanks, >-robert Philip Freidin FliptronicsArticle: 37470
I have seen this in Verilog, if you don't make the synplicity ignore any attached parameters to the DCM that are there for simulation. In Verilog my code looks like this: /* synthesis translate_off */ defparam dcm_0.CLKOUT_PHASE_SHIFT = "VARIABLE"; /* synthesis translate_on */ dcm_0 is the instance name of a dcm. Philip On Tue, 11 Dec 2001 12:37:31 -0500, "jakab tanko" <jtanko@ics-ltd.com> wrote: >Hi, > >This error message is driving me nuts: > >ERROR:NgdBuild:604 - logical block 'ddr_ctlr/clk_dll1/dll_u' with type > 'DCMZ0' is unexpanded. Symbol 'DCMZ0' is not supported in target >'virtex2'. > >I have a DCM component in my design (VHDL) and I use Synplify to generate >the netlist (edif) >for the Xilinx ISE. Somewhere along this path the DCM turns into DCMZ0 and >I get the error message from the ISE tool. >I searched xilinx answer records but got nowhere, did anybody >run into this? >Thanks, >jakab > Philip Freidin FliptronicsArticle: 37471
Litvinov wrote: > Hello there, > > I'm use Mentor Leonardo and Altera Max+PlusII. > > Tell me, please, how to set > initial data for RAM? > Don't do it. To be precise it is by far the best practice to make sure that during simulation startup all RAMs are initialised to unknowns since .... <snip> > I needed synthesized VHDL description. > Leonardo says: > "W:/vhdl/BJCards.VHD",line 457: Warning, initial value for Mem is ignored > for synthesis. > But ACEX1 EP1K50QC208 supports initializing a memory. How to explain this > for Leonardo? ... IMO This "feature" is very dangerous and using it will make the code highly non-portable. It also encourages s/w engineers to be sloppy & not initialise RAMs before using them leading to some really deep and hard to trace bugs later on.Article: 37472
Hi, I should have been more clear. I will certainly do what I can to eliminate the crosstalk (I'm confident I know what is causing it). My question is whether changing the layout is enough to inspire confidence. From Philip's response (which looks like a solution), it sounds like he never trusts that his clocks will be glitch free (is that fair Philip?). In general, do you always design so that external signals do not directly feed flip-flop clocks (provided that the timing allows this)? I've gotten away with driving FFs with all sorts of external signals before, but I've only recently been using parts that have edges fast enough to cause serious crosstalk and fast enough to respond to the resulting glitches. -robert Peter Alfke wrote: > > > Robert Abiad wrote: > > Hi, > > I've recently run into the problem of getting crosstalk onto a clock > input due to a layout problem. <snip>Or is the right approach to > just eliminatethe glitching? > > Your first attempt should always be to eliminate the glitch if at all > possible, even if it costs and hurts.Article: 37473
THe synthesizer is seeing generics on the DCM and doesn't know what to do with
them (as a result it thinks it is a different component). The Z) appended on
the end is done whenever there are more than one components with the same name
to resolve conflicts. You need to put the generics in the component
declaration inside a synthesis translate_on/off pragma to make the generics
invisible to the the synthesizer. If there are settings that are not default,
such as the clock_divide, then the generic sets the value for simulation only,
and for the synthesized block you need to add an attribute or a line in the
UCF file. Personally, I prefer doing it in the VHDL source so that the
information is all in one place.
jakab tanko wrote:
> Hi,
>
> This error message is driving me nuts:
>
> ERROR:NgdBuild:604 - logical block 'ddr_ctlr/clk_dll1/dll_u' with type
> 'DCMZ0' is unexpanded. Symbol 'DCMZ0' is not supported in target
> 'virtex2'.
>
> I have a DCM component in my design (VHDL) and I use Synplify to generate
> the netlist (edif)
> for the Xilinx ISE. Somewhere along this path the DCM turns into DCMZ0 and
> I get the error message from the ISE tool.
> I searched xilinx answer records but got nowhere, did anybody
> run into this?
> Thanks,
> jakab
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 37474Hello Does anyone have an idea as to what would be an adequate constraint to minimize the skew on the JTAG clock ? Xilinx's ILA Cores user guide tells us that when your design has already used all of the BUFG (4 in my xcv600) that you should place the JTAG clock on regular routing. They don't suggest a time value for an adequate constraint. -Dave Brown
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z