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we are having a similar problem. we need a Dual Port Ram for our design and were trying to instantiate one of the Block Rams available on the Virtex - E device using Verilog. Initially we just declared the required memory as an array of registers.something like reg [15:0] memory [255:0] ; The synthesizers (XST, FPGAexpress) are not inferring this as a RAM but as FFs Then we tried with the Xilinx Language template RAMB4_S16_S16, this gave a synthesis error. Last we tried with CorGen that gives an error when we hit the Generate button. Any suggestions ? adarsh kumar jain, Ray Andraka wrote: > I think he was looking for a low cost or free tool that would infer > one. If your tools do not support RAM inference, then you can always > instantiate the RAM primitive. I usually just instantiate the primitive > because it gives me more portability between tools and more flexibility > in describing what I want (and you don't have to rely on the tool for > doing the right thing, especially in regards to a dual ported memory).Article: 37552
Neil, A slight variation to the subject but... Why is there a MASK file for TDI, surely if it's don't care then the data is invalid therefore I can ignore the MASK anyway? The spec is not clear on this. Thanks, Dave "Neil Glenn Jacobson" <neil.jacobson@xilinx.com> wrote in message news:3C195790.B42DC5A8@xilinx.com... iMPACT SVF files are smaller than those generated by JTAGProgrammer because iMPACT makes use of several SVF language constructs that reduce the overall SVF file size, as follows: HIR, HDR, TIR, TDR commands are used to delineate static shift data related to devices surrounding the target device. The MASK and SMASK are not reproduced with each SDR making use of the SVF rule that previously specified MASK and SMASK apply when these values are unspecified. For more information on SVF please visit: http://www.asset-intertech.com/support/svf.html#access Guy-Armand wrote: Hi, When using webpack 3, I was able to create .svf files for CPLD devices. But now when selecting the "Generate Programming File" and entering the IMPACT window, I can choose between Boundary Scan, Slave Serial and Select Map. I have all these options but all the same the .svf file that is created is not the same as the one created by previous version of Webpack. The current file is only 553kb instead of 867kb. (I have no cable connected to my computer). Please could someone help me choosing the right options for creating a .svf file for xc9500 device programming? I am using a parrallel cable to download the .svf files to the board. Thanks for any hint. GuyArticle: 37553
Make sure your bitstream is configured properly. Most notably, make sure it is
not set up for JTAG
Falk Brunner wrote:
> "Philip Freidin" <philip@fliptronics.com> schrieb im Newsbeitrag
> news:0e0i1ugsb6ouidtrtc7an47use51ltifpb@4ax.com...
> > On Thu, 13 Dec 2001 18:23:08 +0100, "Falk Brunner" <Falk.Brunner@gmx.de>
> wrote:
> > >Dont mix well, Iam afraid. We have a small board with a XCS20XL. It is
> > >configured by a uC. Compiling it under Foundation 3.1 works fine, but
> > >compiling it using Foundation 4.1 does NOT work. DONE stays LOW, INIT
> stays
> > >HIGH (so no CRC error)
> > >Even very simple tests (route through and toggle-FF) dont work.
> > >I checked all Foundation settings, they should be the same.
> > >I checked the Xilinx website, nothing. :-((
> > >
> > >Any hints?
> >
> > Create the bitstreams in .RBT format and look at them. Although the guts
> of
>
> We use the MCS format, this is then converted into a C sourcefile.
> The MCS files from Foundatiopn 3.1/4.1 have exactly the same lenght. The
> first few hundred bytes are the same, and so are the last lines of bytes.
>
> > the bit streams will be different, the lengths should be identical, as
> > should the header bits, and the bits right at the end.
> >
> > Your problem sounds very much like the "I need to clock a few more ones in
> > at the end of the bitstream"
>
> Hmm??? I dont think so. I hooked up a frequency counter onto CCLK, with the
> working image, ther are somethig like 179xxx clocks, with the non working
> image there are around 20 cycles more, which is the normal behaviour of the
> loader routine.
>
> --
> MfG
> Falk
>
> >
> > Philip
> >
> > Philip Freidin
> > Fliptronics
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 37554Check the command line options that were used in order to generate the bit file with F3.1 vs. those used with F4.1. You may find your problem just there. YuryArticle: 37555
One doen not have to instantiate the I/O Buffers in HDL code. Generally it is a function of the synthesis tool to insert the appropriate I/O buffers. Ususally there is an option to do so. Quartus II in turn also has an option of mapping/or not the ports to appropriate I/O buffers. That option is utilized for incremental "synthesis" using Quartus II (which is P&R in Xilinx world). YuryArticle: 37556
XST won't infer a dual port RAM, and I don't believe express will either, which
is why you are getting FF's. Instantiate the RAMB4_S16_S16 directly from the
unisim library. Any generics have to be made invisible to the synthesizer
using translate_off/on pragmas (and you'll have to put matching attributes in
to pass the parameters to the netlist).
It might help for you to post the errors along with snippets of your code.
adarsh wrote:
> we are having a similar problem.
> we need a Dual Port Ram for our design and were trying to instantiate one
> of the Block Rams available on the Virtex - E device using Verilog.
> Initially we just declared the required memory as an array of
> registers.something like
>
> reg [15:0] memory [255:0] ;
> The synthesizers (XST, FPGAexpress) are not inferring this as a RAM but as
> FFs
>
> Then we tried with the Xilinx Language template RAMB4_S16_S16, this gave a
> synthesis error.
> Last we tried with CorGen that gives an error when we hit the Generate
> button.
>
> Any suggestions ?
>
> adarsh kumar jain,
>
> Ray Andraka wrote:
>
> > I think he was looking for a low cost or free tool that would infer
> > one. If your tools do not support RAM inference, then you can always
> > instantiate the RAM primitive. I usually just instantiate the primitive
> > because it gives me more portability between tools and more flexibility
> > in describing what I want (and you don't have to rely on the tool for
> > doing the right thing, especially in regards to a dual ported memory).
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 37557
Russell Shaw wrote:
>
> Hi all,
>
> I need a ram that has an input (write) data port, output (read)
> data port, write-address port, and read-address port. I need to
> write to a different part of ram that is currently being read.
> Are there any cheap/free tools that recognize a vhdl template
> for this function? I'm using an Acex 1k30 device.
From the code below, leo infers a dual port ram_dq_da
on an Acex 1k (or 20k) or Virtex device.
-- Mike Treseler
-------------------------------------------------------------------------------
-- Exemplar Infers ram_dq_da_inclock_out_clock_16_8_256 from this code
-- No exemplar libraries required, generic size
-- M. Treseler 11-29-2001
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_dpram is
generic (width : natural := 16;
add_length : natural := 8 -- 7 for 128x16
);
port ( rclk : in std_ulogic;
wclk : in std_ulogic;
data : in std_logic_vector(width-1 downto 0);
rd_adr : in std_logic_vector(add_length-1 downto 0);
wr_adr : in std_logic_vector(add_length-1 downto 0);
we : in std_ulogic;
q : out std_logic_vector(width-1 downto 0)
);
end sync_dpram;
architecture synth of sync_dpram is
constant mem_size : natural := 2**add_length;
type mem_type is array (mem_size-1 downto 0) of
std_logic_vector (width-1 downto 0);
signal mem : mem_type;
begin
ram_access : process (rclk, wclk)
begin
if rising_edge(wclk) then
if we = '1' then
mem(to_integer(unsigned(wr_adr))) <= data;
end if;
end if;
if rising_edge(rclk) then
q <= mem(to_integer(unsigned(rd_adr)));
end if;
end process ram_access;
Article: 37558Hi, I am using the DDS generated by CoreGen, it outputs two's complement value, is there a way to create it as just a regular representation (not "the complement"), maybe by accessing the file thanks ennyArticle: 37559
"MH" <blahblah@blahblah.blah> wrote in message
news:3c165132$0$227$cc9e4d1f@news.dial.pipex.com...
> Thanks for the link.
>
> "This offer is limited to one license per site and is valid until November
30, 2001"
>
> Doh! I wish they'd told me about this a few weeks ago....
>
> MH.
MH,
Did you check into this and is the special still going on? I'd like to
know, because things are always different in various parts of the
country/world. I'm in Florida, where are you?
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL USA
Article: 37560Hi All, Is there a way to check used xilinx components? I have something like 15 virtexe devices 1156 bga. Those components were removed from boards because of soldering problems. Most of them are reballed already. I want to reuse tem but only after I will check if they are ok. If you know of a place that can completely check them, Please let me know. Thank you ZoharArticle: 37561
The available inference options in the free leonardo are lpm_ram_dq, and lpm_ram_io. Lpm_ram_dq has *one* address port, and separate read and write data ports. Lpm_ram_io just has one data port for read and write. I think what can be infered/instantiated is a function of what's in the technology library. I really need lpm_ram_dp. The free maxplus2 has a wizard to infer one, but doesn't compile vhdl. Ray Andraka wrote: > > I think he was looking for a low cost or free tool that would infer > one. If your tools do not support RAM inference, then you can always > instantiate the RAM primitive. I usually just instantiate the primitive > because it gives me more portability between tools and more flexibility > in describing what I want (and you don't have to rely on the tool for > doing the right thing, especially in regards to a dual ported memory). > > Peter Alfke wrote: > > > You describe the need for a dual-ported RAM. Any dual-ported RAM > > should do your job, even the ones that are not "true dual-ported > > RAMs", i.e. the ones that have one read port and one write port. I > > do not know about ACEX, but all Xilinx BlockRAMs have always been > > fully symmetrical, i.e. true dual port RAMs where either port can > > read or write, independent of the other.. > > > > Peter Alfke > > ============================== > > Russell Shaw wrote: > > > > > Hi all, > > > > > > I need a ram that has an input (write) data port, output (read) > > > data port, write-address port, and read-address port. I need to > > > write to a different part of ram that is currently being read. > > > Are there any cheap/free tools that recognize a vhdl template > > > for this function? I'm using an Acex 1k30 device.Article: 37562
Thanks. Reading the data sheet again is one thing i forgot (so many things to look at :( ). Its running at 5MHz, so i'll try making a cycle-shared one at 10MHz using a 'normal' lpm_ram_dq. Ray Andraka wrote: > > I somehow missed that this was for Altera. The Acex and 10K (not 10KE) EABs > do not support dual port operation, as they only have one address port. They > have separated read and write data busses, but the address is shared. You are > sort of correct, only the limitation comes from the underlying architecture, > not the library. If you need dual port operation, your best bet is to upgrade > to a 10KE or 20K part, or use Xilinx SaprtanII or VIrtex or later families > which have true dual port RAMs. > > If you have a 2x clock available and timing permits it, you can also cobble a > dual port by alternating read/write cycles at 2x. In any event, even the > tools that can infer a dual port RAM won't help you here because the > underlying technology does not support it. > > Russell Shaw wrote: > > > The available inference options in the free leonardo are lpm_ram_dq, > > and lpm_ram_io. Lpm_ram_dq has *one* address port, and separate read > > and write data ports. Lpm_ram_io just has one data port for read and > > write. I think what can be infered/instantiated is a function of > > what's in the technology library. > > > > I really need lpm_ram_dp. The free maxplus2 has a wizard to infer > > one, but doesn't compile vhdl. > >...Article: 37563
Mike Treseler wrote:
>
> Russell Shaw wrote:
> >
> > Hi all,
> >
> > I need a ram that has an input (write) data port, output (read)
> > data port, write-address port, and read-address port. I need to
> > write to a different part of ram that is currently being read.
> > Are there any cheap/free tools that recognize a vhdl template
> > for this function? I'm using an Acex 1k30 device.
>
> From the code below, leo infers a dual port ram_dq_da
> on an Acex 1k (or 20k) or Virtex device.
>
> -- Mike Treseler
>
> -------------------------------------------------------------------------------
> -- Exemplar Infers ram_dq_da_inclock_out_clock_16_8_256 from this code
> -- No exemplar libraries required, generic size
> -- M. Treseler 11-29-2001
> -------------------------------------------------------------------------------
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
>
> entity sync_dpram is
> generic (width : natural := 16;
> add_length : natural := 8 -- 7 for 128x16
> );
>
> port ( rclk : in std_ulogic;
> wclk : in std_ulogic;
> data : in std_logic_vector(width-1 downto 0);
> rd_adr : in std_logic_vector(add_length-1 downto 0);
> wr_adr : in std_logic_vector(add_length-1 downto 0);
> we : in std_ulogic;
> q : out std_logic_vector(width-1 downto 0)
> );
> end sync_dpram;
>
> architecture synth of sync_dpram is
> constant mem_size : natural := 2**add_length;
> type mem_type is array (mem_size-1 downto 0) of
> std_logic_vector (width-1 downto 0);
> signal mem : mem_type;
> begin
>
> ram_access : process (rclk, wclk)
> begin
> if rising_edge(wclk) then
> if we = '1' then
> mem(to_integer(unsigned(wr_adr))) <= data;
> end if;
> end if;
> if rising_edge(rclk) then
> q <= mem(to_integer(unsigned(rd_adr)));
> end if;
>
> end process ram_access;
Thanks. I tried this code on its own (changed width to 8), but the
free leonardo has problems:
->_gc_read_init
->_gc_run_init
->set input_file_list { E:/AAProjs/Bugs/Leonardo/main.vhd }
E:/AAProjs/Bugs/Leonardo/main.vhd
->set part EP1K50FC256
EP1K50FC256
->set chip TRUE
->set macro FALSE
FALSE
->set optimize_for area
area
->set report brief
brief
->set -hierarchy auto
auto
->set maxdelay 0
0
->set hierarchy_auto TRUE
TRUE
->set hierarchy_preserve FALSE
FALSE
->set hierarchy_flatten FALSE
FALSE
->set output_file E:/AAProjs/Bugs/Leonardo/main.edf
E:/AAProjs/Bugs/Leonardo/main.edf
->set novendor_constraint_file FALSE
FALSE
->set target acex1
acex1
->_gc_read
-- Reading target technology acex1
Reading library file `D:\Exemplar\LeoSpec\OEM2001_1d_Altera_RC_24\\lib\acex1.syn`...
Library version = 4.5
Delays assume: Process=1
-- read -tech acex1 { E:/AAProjs/Bugs/Leonardo/main.vhd }
-- Reading file D:\Exemplar\LeoSpec\OEM2001_1d_Altera_RC_24\\data\standard.vhd for unit standard
-- Loading package standard into library std
-- Reading vhdl file E:/AAProjs/Bugs/Leonardo/main.vhd into library work
-- Reading file D:\Exemplar\LeoSpec\OEM2001_1d_Altera_RC_24\\data\std_1164.vhd for unit std_logic_1164
-- Loading package std_logic_1164 into library ieee
-- Reading file D:\Exemplar\LeoSpec\OEM2001_1d_Altera_RC_24\\data\numeric_std.vhd for unit numeric_std
-- Loading package NUMERIC_STD into library ieee
-- Loading entity sync_dpram into library work
-- Loading architecture synth of sync_dpram into library work
-- Compiling root entity sync_dpram(synth)
-- Pre Optimizing Design .work.sync_dpram_8_8.synth
-- Boundary optimization.
"E:/AAProjs/Bugs/Leonardo/main.vhd", line 34:Info, Inferred ram instance 'ix26409' of type
'ram_dq_da_inclock_outclock_8_8_256'
Info: Finished reading design
->_gc_run
-- Run Started On Sat Dec 15 13:00:48 AUS Eastern Daylight Time 2001
--
-- optimize -target acex1 -effort quick -chip -area -hierarchy=auto
Using default wire table: STD-1
Warning, Dual read ports not supported for FLEX/APEX/MERCURY RAMs; using default implementation.
Warning, using default ram implementation for ram_dq_da_inclock_outclock_8_8_256, run time can get large.
Assertion failed (0) File: <Z:/leo/leo_rls/iwa/2001_1d.24/src/modules/hier/detect/ram_inst.c> Line: <801>
Assertion failed (0) File: <Z:/leo/leo_rls/iwa/2001_1d.24/src/modules/hier/detect/ram_inst.c> Line: <801>
Assertion failed (0) File: <Z:/leo/leo_rls/iwa/2001_1d.24/src/modules/hier/detect/ram_inst.c> Line: <801>
Assertion failed (0) File: <Z:/leo/leo_rls/iwa/2001_1d.24/src/modules/hier/detect/ram_inst.c> Line: <801>
Assertion failed (0) File: <Z:/leo/leo_rls/iwa/2001_1d.24/src/modules/hier/detect/ram_inst.c> Line: <801>
Assertion failed (0) File: <Z:/leo/leo_rls/iwa/2001_1d.24/src/modules/hier/detect/ram_inst.c> Line: <801>
Assertion failed (0) File: <Z:/leo/leo_rls/iwa/2001_1d.24/src/modules/hier/detect/ram_inst.c> Line: <801>
Assertion failed (0) File: <Z:/leo/leo_rls/iwa/2001_1d.24/src/modules/hier/detect/ram_inst.c> Line: <801>
-- Start optimization for design .work.sync_dpram_8_8.synth
Using default wire table: STD-1
*********** At this point, leonardo is doing something with 25000 LUTs for a few minutes ***********
est est
Pass LCs Delay DFFs TRIs PIs POs --CPU--
min:sec
1 3767 15 2056 0 19 8 09:59
***********************************************
Device Utilization for EP1K50FC256
***********************************************
Resource Used Avail Utilization
-----------------------------------------------
IOs 35 186 18.82%
LCs 3798 2880 131.88%
DFFs 2056 2880 71.39%
Memory Bits 0 40960 0.00%
CARRYs 0 2880 0.00%
CASCADEs 1632 2880 56.67%
-----------------------------------------------
This design does not fit in the device specified!
Trying an alternate device ...
Info: Reset Device to EP1K100QC208
***********************************************
Using default wire table: STD-1
-- Start timing optimization for design .work.sync_dpram_8_8.synth
No critical paths to optimize at this level
*******************************************************
*******************************************************
Cell: sync_dpram_8_8 View: synth Library: work
Cell: sync_dpram_8_8 View: synth Library: work
*******************************************************
*******************************************************
Number of ports : 35
Number of nets : 6685
Number of instances : 6666
Number of references to this view : 0
Total accumulated area :
Number of CASCADEs : 1632
Number of DFFs : 2056
Number of LCs : 3798
Number of accumulated instances : 6666
***********************************************
Device Utilization for EP1K100QC208
***********************************************
Resource Used Avail Utilization
-----------------------------------------------
IOs 35 147 23.81%
LCs 3798 4992 76.08%
DFFs 2056 4992 41.19%
Memory Bits 0 49152 0.00%
CARRYs 0 4992 0.00%
CASCADEs 1632 4992 32.69%
-----------------------------------------------
Clock Frequency Report
Clock : Frequency
------------------------------------
rclk : 64.9 MHz
wclk : 120.6 MHz
Critical Path Report
Critical path #1, (unconstrained path)
NAME GATE ARRIVAL LOAD
------------------------------------------------------------------------------------------------
wr_adr(1)/ 0.00 0.00 up 2.59
nx31456/O F4_LUT 3.22 3.22 up 2.62
nx32837/O F4_LUT 1.86 5.08 up 1.26
nx32209/O CASCADE2 0.80 5.88 up 1.26
nx32840/O F4_LUT 1.86 7.74 up 1.26
NOT_ix26409_modgen_mux_264_nx470/O CASCADE2 0.80 8.54 up 1.26
nx32274/O F4_LUT 1.86 10.40 up 1.26
nx32845/O F4_LUT 1.86 12.26 up 1.26
nx32196/O CASCADE2 0.80 13.06 up 1.26
nx33787/O F4_LUT 1.86 14.92 up 1.26
ix26409_ix1332/D DFF 0.00 14.92 up 0.00
data arrival time 14.92
data required time not specified
------------------------------------------------------------------------------------------------
data required time not specified
data arrival time 14.92
----------
unconstrained path
------------------------------------------------------------------------------------------------
Info, Timing characterstics are preliminary
Info, Altera place and route software needs to be run to obtain accurate timing results
-- Design summary in file 'E:/AAProjs/Bugs/Leonardo/main.sum'
-- Saving the design database in E:/AAProjs/Bugs/Leonardo/main.xdb
-- Writing file E:/AAProjs/Bugs/Leonardo/main.xdb
-- Writing XDB version 1999.1
-- Applying renaming rule 'ALTERA' to database
Warning, Renaming will cause your database to change
-- Calling set_altera_eqn to set up writing Equations
-- write E:/AAProjs/Bugs/Leonardo/main.edf
-- Writing file E:/AAProjs/Bugs/Leonardo/main.edf
Info, About to call 'setacf' for generating/modifying ACF file
Info, 'setacf' done.
Info, Writing batch file 'E:/AAProjs/Bugs/Leonardo/main.tcl'
-- CPU time taken for this run was 691.39 sec
-- Run Successfully Ended On Sat Dec 15 13:12:19 AUS Eastern Daylight Time 2001
0
Info: Finished Synthesis run
Article: 37564
I somehow missed that this was for Altera. The Acex and 10K (not 10KE) EABs
do not support dual port operation, as they only have one address port. They
have separated read and write data busses, but the address is shared. You are
sort of correct, only the limitation comes from the underlying architecture,
not the library. If you need dual port operation, your best bet is to upgrade
to a 10KE or 20K part, or use Xilinx SaprtanII or VIrtex or later families
which have true dual port RAMs.
If you have a 2x clock available and timing permits it, you can also cobble a
dual port by alternating read/write cycles at 2x. In any event, even the
tools that can infer a dual port RAM won't help you here because the
underlying technology does not support it.
Russell Shaw wrote:
> The available inference options in the free leonardo are lpm_ram_dq,
> and lpm_ram_io. Lpm_ram_dq has *one* address port, and separate read
> and write data ports. Lpm_ram_io just has one data port for read and
> write. I think what can be infered/instantiated is a function of
> what's in the technology library.
>
> I really need lpm_ram_dp. The free maxplus2 has a wizard to infer
> one, but doesn't compile vhdl.
>
> Ray Andraka wrote:
> >
> > I think he was looking for a low cost or free tool that would infer
> > one. If your tools do not support RAM inference, then you can always
> > instantiate the RAM primitive. I usually just instantiate the primitive
> > because it gives me more portability between tools and more flexibility
> > in describing what I want (and you don't have to rely on the tool for
> > doing the right thing, especially in regards to a dual ported memory).
> >
> > Peter Alfke wrote:
> >
> > > You describe the need for a dual-ported RAM. Any dual-ported RAM
> > > should do your job, even the ones that are not "true dual-ported
> > > RAMs", i.e. the ones that have one read port and one write port. I
> > > do not know about ACEX, but all Xilinx BlockRAMs have always been
> > > fully symmetrical, i.e. true dual port RAMs where either port can
> > > read or write, independent of the other..
> > >
> > > Peter Alfke
> > > ==============================
> > > Russell Shaw wrote:
> > >
> > > > Hi all,
> > > >
> > > > I need a ram that has an input (write) data port, output (read)
> > > > data port, write-address port, and read-address port. I need to
> > > > write to a different part of ram that is currently being read.
> > > > Are there any cheap/free tools that recognize a vhdl template
> > > > for this function? I'm using an Acex 1k30 device.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 37565That's what happens when I carefully and deliberately refrain from bashing Altera for their inferior solution... Either be a gentleman or be forthcoming. What a choice! :-) Peter Alfke ===================================== Ray Andraka wrote: > I somehow missed that this was for Altera. The Acex and 10K (not 10KE) EABs > do not support dual port operation, as they only have one address port. They > have separated read and write data busses, but the address is shared.Article: 37566
I just looked at the acex 1k pdf, and it looks like the EAB *does* have separate read and write address and data ports (ie, full dual-port). "The ACEX 1K EAB can act in dual-port or single-port mode. When in dual-port mode, separate clocks may be used for EAB read and write sections, allowing the EAB to be written and read at different rates. It also has separate synchronous clock enable signals for the EAB read and write sections, which allow independent control of these sections." Russell Shaw wrote: > > Thanks. Reading the data sheet again is one thing i forgot (so many things > to look at :( ). Its running at 5MHz, so i'll try making a cycle-shared > one at 10MHz using a 'normal' lpm_ram_dq. > > Ray Andraka wrote: > > > > I somehow missed that this was for Altera. The Acex and 10K (not 10KE) EABs > > do not support dual port operation, as they only have one address port. They > > have separated read and write data busses, but the address is shared. You are > > sort of correct, only the limitation comes from the underlying architecture, > > not the library. If you need dual port operation, your best bet is to upgrade > > to a 10KE or 20K part, or use Xilinx SaprtanII or VIrtex or later families > > which have true dual port RAMs. > > > > If you have a 2x clock available and timing permits it, you can also cobble a > > dual port by alternating read/write cycles at 2x. In any event, even the > > tools that can infer a dual port RAM won't help you here because the > > underlying technology does not support it. > > > > Russell Shaw wrote: > > > > > The available inference options in the free leonardo are lpm_ram_dq, > > > and lpm_ram_io. Lpm_ram_dq has *one* address port, and separate read > > > and write data ports. Lpm_ram_io just has one data port for read and > > > write. I think what can be infered/instantiated is a function of > > > what's in the technology library. > > > > > > I really need lpm_ram_dp. The free maxplus2 has a wizard to infer > > > one, but doesn't compile vhdl. > > >...Article: 37567
Why is the xilinx 4005xl 3.3v device? what if i want to output signals to an external 5v device? is there something i can do to get around this problem?Article: 37568
Ok, I'll admit I'm not a fan of the PCB layout of the XSV boards, but I'm sure this was a design compromise. The PQ240/HQ240 package spans the most Virtex parts. The larger pin-count packages (all variations of BGA) are only available for the higher-density Virtex parts, and I'm guessing Xess wanted a multi-purpose platform. > I don't normally randomly post gripes about something unless it really > sucks and makes me very very angry. If something sucks that much, I might > want to warn people not to use it as well. Guess what? The XESS XSV-800 > with the Virtex XCV800 board really sux!! Don't buy it! > > I am working on a really simple design, for which I needed an 8-bit input > and a few pushbuttons + small amount of FlashROM. The XSV-800 has exactly > one bank of 8 DIP switches & 4-buttons & a FlashROM. Great I thought, this > solves my problem...NOT! The XSV's board schematics are publically available at Xess's website (http://www.xess.com) I suggest anyone wanting to buy the Xess board to download the PDF manual and review the schematics. They list which pins (of what devices) share I/Os. In my opinion, Xess has done an *excellent* job of documenting this. You can't use all devices on the XSV board simultaneously, but the schematics will tell you exactly which ones will work together and in what combination.Article: 37569
"Mohap" <NOSPAMamol_moh@hotmail.com> schrieb im Newsbeitrag news:3c1ba3be$1_2@nntp2.nac.net... > Why is the xilinx 4005xl 3.3v device? what if i want to output signals to an Because the mighty lord wanted it to be so ;-) > external 5v device? is there something i can do to get around this problem? When the 5V device has TTL switching thresholds, you can drive them with 3.3V CMOS outputs. -- MfG FalkArticle: 37570
Last year, I used Xilinx Foundation Express 3.3i, to develop
for a Virtex300 part. I recently went to Xilinx's hoomepage,
and found that the 'Foundation ISE' has replaced the older
Foundation (non-ISE.)
Does this mean :
1) goodbye old Windows 16-bit legacy code
(3.3i would crash on average, every 4-6 compiles, and
sometimes take down my NT4 workstation)
2) no more Synopsys FPGA-express for compiling Verilog/VHDL?
If so, what has replaced it?
From what I read on Xilinx's homepage, it looks like
'XST' (Xilinx Synthesis Technology) has replaced
FPGA-express. Is that the case?
3) easier installation of software?
I think I jar-jard my Xilinx 3.1i installation. It
seemed like you had to install those "service packs"
in exactly the correct order, otherwise the whole
package just wouldn't run right. And I really hated
how the service-packs left phantom entries in the
Windows registry (making uninstallation equally
confusing.)
Article: 37571
> Guessing that cache size has a first order effect on
> sim/compilation timing (!), are there any 'commodity' PCs
> which have better-than-average secondary/tertiary caches?
>
> Or are all the cache arrangements dictated by the chipset
> manufacturers, and effectively identical?
>
For the CPUs you mentioned, the L1 and L2 cache are located
on the CPU die. There is no provision for an external
(off-CPU) L3 cache, at least I don't think so.
The 'server' version of the Pentium3 1.13GHz and 1.26GHz
(both are designated 'Pentium III-S') both have 512K L2
cache. (L1 cache size is still 32K, as it has been since the
old Pentium/MMX days.)
The current .18micron Pentium3 and Pentium4's have 256K L2
cache. The upcoming .13micron Pentium4 ('Northwood') may
have a 512K L2-cache...I dont know.
> As I recall, Athlon primary cache size = 2x Duron, and
> similarly for P[3|4]/Celeron.
Actually, the Duron and Thunderbird (and Athlon XP/MP) have
the same L1-cache size, 128KB I think. The Duron series
(including the 1.0GHz+ 'Morgan' core) have a 64KB L2-cache,
while the Thunderbird and Athlon XP/MP have 256KB L2-cache.
...
Earlier, I posted my observations on NCverilog 3.2 performance,
Sun Blade1000 (2/750MHz) vs Pentium3-1.0GHz. In short,
the Blade1000 ran circles around the P3 for RTL/behavioral
simulations. This means anywhere from 1.2x to 2.0x faster.
These simulations had a memory footprint of about
250MB. The Pentium3 performed 'roughly' in the area of
our (old) Sun Ultra60 (2/360Mhz).
(For 'trivially' small RTL/behavioral simulations, the P3
was actually slightly faster than the Blade1000. I'm guessing
the simulator fit entirely in L2 cache of each platform, and
the P3's higher clock(MHz) wins.)
In back-SDF annotated gate-level simualtions (memory footprint
between 500MB and 760MB), the Pentium3 and Blade1000 were dead
even. Amazing..., considering the cost difference between
the P3 and Blade1000!
The Pentium3 was an ASUS P3V4X (Via 694X chipset), with 1GB of
CAS2 PC133 ECC Crucial SDRAM, running Redhat 7.0 with the
Linux 2.2.19 kernel. The Sun Blade1000 is a dual-CPU US3-750MHz,
running Solaris 8. I think it had 5GB ECC of whatever
mondo-expensive RAM the Blade1000 uses.
(We bought 4GB of that RAM from an aftermarket vendor,
www.dataram.com)
For other stuff, like Synopsys Design_Compiler, the Pentium3
was slightly faster than the Blade1000. (Note, I ran
Design-Compiler 2001.08 on the Linux x86 box, and 2000.11-SP1
on the Solaris.) This was for a medium-size ('300K ASIC gates')
Verilog compile, roughly 2hours.
Article: 37572Mohap wrote: > Why is the xilinx 4005xl 3.3v device? what if i want to output signals to an > external 5v device? is there something i can do to get around this problem? XC4005XL uses 3.3 V supply voltage because that cuts dynamic power consumption in half, compared to 5 V. Also, modern high-performance processes do not tolerate high voltages like 5 V. Today, 3.3 V is already obsolete, the most modern FPGAs use 1.5 V for the core logic, but retain 2.5 V tolerance on all outputs, 3.3 V on some. For new designs, 5 V is definitely out. It served us well from 1965 to 1995, for one third of the previous century, but its days are over. Rest In Peace ! Now to your problem: The XC4005 inputs tolerate 5 V, if you select this ( and thus disable the clamp diode to Vcc that is there because PCI demands it ). Now you can drive the inputs up to 5.5 V. The outputs can obviously not drive higher than their own Vcc, and 3.3 V may be high enough for driving 5 V logic with so-called TTL input thresholds of ~ 1.5 V. (Forget the 2.4 V spec for Voh, that's a 30-year old left-over from the days of bipolar TTL. What if you have to drive 5-V that has a CMOS input threshold of up to 3.5 V. Then you need a pull-up resistor to the 5 V, and you should configure the XC4005 output as "open collector" ( really: open drian ). That costs you speed, since you now have a 1 kilohm pull-up and a, say, 100 pF lad, which creates a 100 ns delay time constant. There is a simple and clever way around that, and I can send you the circuit description on Monday when I am back at work. Peter Alfke, Xilinx ApplicationsArticle: 37573
Why don't you use Virtex II? dottavio@ised.it (Antonio) wrote in message news:<fb35ea96.0112132356.7f43b3fe@posting.google.com>... > I'm preparing a QPSK modulator, > until now I arrange it for a VIRTEX 1000 -4 , but it seem that could > be impossible to use it at a maximum clock speed of 165MHz especially > 'cause I've to put in and out that speed and this seems not possible > (..or I'm wrong ??) I'm using less than 30% of VIRTEX 1000 so my > question is which FPGA is actually the one with best speed > performance, it could be not only Xilinx 'cause my scope is to verify > that there's actually a technology where my project could be > implemented. Thanks > > Antonio
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