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Thorsten Bunte wrote: > > the higher current is not a problem for cyclone devices only. You can find > this kind of behaviour at all kind of SRAM based FPGA. <snip> I am happy to report that we have solved this problem for the Virtex-II and all subsequent families. No more power-on surge currents in the newer Xilinx families ! Peter Alfke, Xilinx ApplicationsArticle: 53301
Interesting piece of semiconductor history: The General Manager and VP of the RCA Solid State Division, the guy in charge of the 4000-series COSMOS project, later joined Zilog, and in 1984 founded Xilinx, where he now is the Chairman of the Board. His name is Bernie Vonderschmitt. Peter Alfke ======================== Jim Granville wrote: > > Power consumption and noise immunity / RFI ? > > A 40106 can give much lower ICC when driven from slow edges than > HC/AHC devices. > A 4069 will give a lower current XTAL osc than a HCU04, at the lower > frequencies. > A 4541 is a good low power, low cost, long timebase wdog/timer device. > > Their low drive, and slow edges, plus ability to ignore narrow pulses > also make them good choices for interface aplications. > > -jgArticle: 53302
Hi, I was wondering if anybody had come accross this problem when using Xilinx FPGA's and if so do they know how to solve it. I have just recieved a PCB design back from FAB and We are having an issue with a short between the VCC and GND planes. This however only occurs when the Xilinx Spartan XL XCS30 is populated on the board, ie the short is finding it's way through the silicon of the FPGA. Immediately I suspected an error on the footprint of the FPGA but it was correct, then I thought maybe an IO pin which was externally pulled up or down was shorted to the opposite level internal to the chip. Ijn trying to determine this I lifted every pin except the PWR pins and the short still occurs, so I can categorically say that the short is iunternal betweent the two levels. My question is this. Is it possible that when an FPGA leaves the FAB it is configured in this way? Perhaps for ESD protection??? Does anyone know how to overcome this problem? PadraigArticle: 53303
Please investigate the nature of the "short". Is it resistive, i.e. current is proportional to voltage ( or is there a diode drop) ? What is the resistance? BTW: The FPGA cannot possibly come with a specific configuration from the factory, since the configuration is volatile, i.e. it disappears when you remove Vcc. Check the pin-out tables, check your Vcc polarity. Something as strange as what you report is usually the result of a very basic oversight. Peter Alfke, Xilinx Applications. ========================== Padraig FitzGerald wrote: > > Hi, > > I was wondering if anybody had come accross this problem when using > Xilinx FPGA's and if so do they know how to solve it. > > I have just recieved a PCB design back from FAB and We are having an > issue with a short between the VCC and GND planes. This however only > occurs when the Xilinx Spartan XL XCS30 is populated on the board, ie > the short is finding it's way through the silicon of the FPGA. > > Immediately I suspected an error on the footprint of the FPGA but it > was correct, then I thought maybe an IO pin which was externally > pulled up or down was shorted to the opposite level internal to the > chip. Ijn trying to determine this I lifted every pin except the PWR > pins and the short still occurs, so I can categorically say that the > short is iunternal betweent the two levels. > > My question is this. > > Is it possible that when an FPGA leaves the FAB it is configured in > this way? Perhaps for ESD protection??? Does anyone know how to > overcome this problem? > > PadraigArticle: 53304
24*X can be done with just one add:
(X<<4)+(X<<3).
25*X uses an additional add.
1/24 ~= 341/8192 = 101010101, => Z=((X<<2)+X), Y= Z<<4 +Z<<8 +X.
1/25 ~328/8192 = 101001000, well you get the idea
For minimum area, provided you can trade clock cycles for hardware, you
can do these adds with a bit serial adder at the cost of only a CLB or
two.
JDS wrote:
> Hi gurus,
>
> I'd like to have some advice in a way to implement a FPGA logic that
> may reuse some gates, and minimize the required space. I have to
> design two blocks with 2 outputs each:
>
> 1. Y1=25*X ; Y2=X/25
> 2. Y1=24*X ; Y2=X/24
>
> where X is 13 bits vector.
>
> I got an idea to implement those by mean of constant operation
> aproximation using JUST add & shift operations.
>
> I'd appreciate any help.
>
> JDS
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 53305Hi, I have a system divided in two parts. One is running at 256Fs and the other one at 64 Fs. Is it good practice to use feed the 256Fs clock into a counter and use the 2nd lsb to clock the second part of the circuit? In my digital system design class, we have always been told to NEVER clock components with anything else than the master clock, and use some logic to enable/disable those components to lower the clock rate. However, after searching in the newsgroup for clock divider, it seems everyone is using a counter as a clock divider. What is the best way to do it? Thanks DavidArticle: 53306
"David" <gretzteam@hotmail.com> schrieb im Newsbeitrag news:Ts5ba.21118$dN3.344629@weber.videotron.net... > Hi, > I have a system divided in two parts. One is running at 256Fs and the other > one at 64 Fs. Is it good practice to use feed the 256Fs clock into a counter > and use the 2nd lsb to clock the second part of the circuit? In my digital > system design class, we have always been told to NEVER clock components with > anything else than the master clock, and use some logic to enable/disable > those components to lower the clock rate. However, after searching in the > newsgroup for clock divider, it seems everyone is using a counter as a clock > divider. What is the best way to do it? Do it as you have been told. Use a clock enable, NO derived clock. -- MfG FalkArticle: 53307
Does anybody know if this type of 'constant function' from Verilog-2001 will
be supported in Synplify? I'm happy with Synplify's Verilog-2001 support so
far, but this feature would be nice.
-Kevin
module ram (address_bus, write, select, data);
parameter SIZE = 1024;
input [clogb2(SIZE)-1:0] address_bus;
...
function integer clogb2 (input integer depth);
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction
endmodule
Article: 53308
> Padraig FitzGerald <pfitzgerald@conwin.ie> wrote in message
news:ee7c445.-1@WebX.sUN8CHnE...
> Hi,
> I was wondering if anybody had come accross this problem when using Xilinx
FPGA's and if so do they know how to solve it.
> I have just recieved a PCB design back from FAB and We are having an issue
with a short between the VCC and GND planes. This however
> only occurs when the Xilinx Spartan XL XCS30 is populated on the board, ie
the short is finding it's way through the silicon of the
> FPGA.
> Immediately I suspected an error on the footprint of the FPGA but it was
correct, then I thought maybe an IO pin which was
> externally pulled up or down was shorted to the opposite level internal to
the chip. Ijn trying to determine this I lifted every pin
> except the PWR pins and the short still occurs, so I can categorically say
that the short is iunternal betweent the two levels.
^^^^^^^^^^^^^
.....or that you've connected one of the power pins to the wrong net, or
you've not been handling your
boards with proper ESD protection and the device has been damaged that way
or......
> My question is this.
> Is it possible that when an FPGA leaves the FAB it is configured in this
way? Perhaps for ESD protection??? Does anyone know how to
> overcome this problem?
Check _everything_ very carefully again, or even better get someone else to
check it all.
Nial.
Article: 53309The classical well-behaved method is to use only one (global) clock, and use a derived clock enable signal to make sure that the other part only operates on every fourth clock cycle. The price is slightly higher clock power consumption (provided you could lay out the circuit such that you don't run the fast clock all over the place). If you use a derived clock, then you end up with two slightly staggered time domains, which can bite you whenever there is data exchange between the two domains. ( The obvious loss of performance due to a late-clokced register driving data into an early-clocked one. The more devious case is the early-clocked register driving data into the late-clocked register, violating hold time requirements, and creating a race-condition mess.) Single clock synchronous is best in 99% of the cases... Peter Alfke, Xilinx Applications =========================== David wrote: > > Hi, > I have a system divided in two parts. One is running at 256Fs and the other > one at 64 Fs. Is it good practice to use feed the 256Fs clock into a counter > and use the 2nd lsb to clock the second part of the circuit? In my digital > system design class, we have always been told to NEVER clock components with > anything else than the master clock, and use some logic to enable/disable > those components to lower the clock rate. However, after searching in the > newsgroup for clock divider, it seems everyone is using a counter as a clock > divider. What is the best way to do it? > Thanks > DavidArticle: 53310
If you are using Xilinx, the DCM / DLL functions can be used as clock dividers. Other FPGA vendors have similar capability. This is probably the best way since these can guarantee a relationship between the two clocks (i.e. zero delay). Alternatively, use a counter to divide the faster clock, but use the output of the counter (with decode logic as required to produce an output which goes high for every 4th clock period) as an ENABLE to the logic in the slower section, such that it can only change state on every Nth clock edge. Obviously you can't use the output of a decoder directly as a clock since it will glitch. David wrote: > Hi, > I have a system divided in two parts. One is running at 256Fs and the other > one at 64 Fs. Is it good practice to use feed the 256Fs clock into a counter > and use the 2nd lsb to clock the second part of the circuit? In my digital > system design class, we have always been told to NEVER clock components with > anything else than the master clock, and use some logic to enable/disable > those components to lower the clock rate. However, after searching in the > newsgroup for clock divider, it seems everyone is using a counter as a clock > divider. What is the best way to do it? > Thanks > David > >Article: 53311
I'm sure this is a real newbie question, I am using an altera max7032A and I need a real cheap, very tiny clock to run some internal counters, it does need to be reasonably freq stable since I am counting time, KHz to low MHz is fine what is the easiest way , i would prefer not use use an external clock chip as it is big and almost as much as the 7032, can I just hang an external crystal, perhaps one of the tiny 32khz jobbies across two pins and build a little osc out of an internal inverting funtions, please explain how to do this, sorry if this question is dumb but I can't find any examples on the net CBArticle: 53312
Kurt, Answers follow in the text below: "Kurt" <famfam@sol.dk> wrote in message news:<taiaa.115064$Hl6.10488659@news010.worldonline.dk>... > Does the ByteBlasterMV download cable support the Cyclone EP1C6 configured > with 3.3V I/O? > Yes, the ByteBlasterMV download cable can be used to configure the Cyclone EP1C6 and other devices within the Cyclone device family. For more details, please see the answers to each of your questions below. Also, for diagrams of the various supported configuration schemes, you can refer to Application Note 250: Configuring Cyclone FPGAs. (http://www.altera.com/literature/an/an250.pdf) > For configuration through JTAG port? Yes, the ByteBlasterMV cable can be used to configure Cyclone devices via the JTAG port. > For SignalTAP (connected to JTAG port)? Yes, the ByteBlasterMV cable can be used to interface with a SignalTAP implementation running on a Cyclone device. > For configuration in AS mode? Active serial configuration of a Cyclone device is only supported via a serial configuration device. In this mode, the Cyclone device acts as the master, while the serial configuration device acts as the slave. None of the download cables can configure the cyclone devices in an active serial configuration mode. However, the ByteBlasterMV does support configuring Cyclone devices in the passive serial configuration mode. > For programming of serial config device (EPCS1S18)? No, the ByteBlasterMV download cable does not support programming a serial configuration device. This is because the ByteBlasterMV does not support the additional outputs required to drive the nCS pin of the serial configuration device and the nCE pin of the Cyclone device. In order to program the serial configuration device, the nCS of the serial configuration device must be driven low and the nCE pin of the Cyclone device must be driven high. The ByteBlaster II download cable supports these additional outputs on pins 6 and 8 of the cable. Sincerely, Greg Steinke gregs@altera.com Altera CorporationArticle: 53313
For a one-off design, you might get away with jsut using a crystal. For
something that needs to be reliable in production, you shouldn't do
that. The oscillator circuit you are talking about biases an inverter
into the linear region. For it to work properly over voltage, temp and
process, the inverter should be a single unbuffered stage. With an FPGA,
you have a multitude of stages, so you are not going to get a reliable
oscillator. What about a clock oscillator such as those made by eclipse,
fox, ecs and other crystal companies? There are a number of them that can
be had for under $3 in single quantities. Another option would be a
dallas semiconductor DS1073 which is an oscillator and programmable
divider in an 8 pin SOIC package, and I think those are dirt cheap.
CB wrote:
> I'm sure this is a real newbie question, I am using an altera
> max7032A and I need a real cheap, very tiny clock to run some internal
> counters, it does need to be reasonably freq stable since I am
> counting time, KHz to low MHz is fine
>
> what is the easiest way , i would prefer not use use an external
> clock chip as it is big and almost as much as the 7032, can I just
> hang an external crystal, perhaps one of the tiny 32khz jobbies across
> two pins and build a little osc out of an internal inverting funtions,
>
> please explain how to do this, sorry if this question is dumb but I
> can't find any examples on the net
>
> CB
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 53314Listen to the lessons from the digital system design class for most cases. If you have logic going between the two time domains, you would have different propagation delays for the two clock domains; what, then, determines valid data? If you use the enable every 4 clocks, the 64x frequency (assuming the 256x frequency is the "master") is the same clock domain as the 256x frequency. No fuss, no muss. "David" <gretzteam@hotmail.com> wrote in message news:Ts5ba.21118$dN3.344629@weber.videotron.net... > Hi, > I have a system divided in two parts. One is running at 256Fs and the other > one at 64 Fs. Is it good practice to use feed the 256Fs clock into a counter > and use the 2nd lsb to clock the second part of the circuit? In my digital > system design class, we have always been told to NEVER clock components with > anything else than the master clock, and use some logic to enable/disable > those components to lower the clock rate. However, after searching in the > newsgroup for clock divider, it seems everyone is using a counter as a clock > divider. What is the best way to do it? > Thanks > David > >Article: 53315
A few possibilities come to mind:
1) your part is rotated from the correct orientation,
2) You got the footprint upside-down, ie, the pin side view
of the chip got translated as the component side of the
board
3) You got the pin out wrong so that a ground pin is
connected to VCC or vice-versa
4) You are not getting proper registration of the part on
the board, or got a solder whisker between pins causing a
vcc to ground short
5) You have problems with your parts handling and damaged
part(s) with ESD.
6) Your power supply can't provide sufficient current to
power the device and as a result appears to be a short.
Padraig FitzGerald wrote:
> Hi,
>
> I was wondering if anybody had come accross this problem
> when using Xilinx FPGA's and if so do they know how to
> solve it.
>
> I have just recieved a PCB design back from FAB and We are
> having an issue with a short between the VCC and GND
> planes. This however only occurs when the Xilinx Spartan
> XL XCS30 is populated on the board, ie the short is
> finding it's way through the silicon of the FPGA.
>
> Immediately I suspected an error on the footprint of the
> FPGA but it was correct, then I thought maybe an IO pin
> which was externally pulled up or down was shorted to the
> opposite level internal to the chip. Ijn trying to
> determine this I lifted every pin except the PWR pins and
> the short still occurs, so I can categorically say that
> the short is iunternal betweent the two levels.
>
> My question is this.
>
> Is it possible that when an FPGA leaves the FAB it is
> configured in this way? Perhaps for ESD protection??? Does
> anyone know how to overcome this problem?
>
> Padraig
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
Article: 53316... Thanks in advance ...Article: 53317
CB wrote: > > I'm sure this is a real newbie question, I am using an altera > max7032A and I need a real cheap, very tiny clock to run some internal > counters, it does need to be reasonably freq stable since I am > counting time, KHz to low MHz is fine > > what is the easiest way , i would prefer not use use an external > clock chip as it is big and almost as much as the 7032, can I just > hang an external crystal, perhaps one of the tiny 32khz jobbies across > two pins and build a little osc out of an internal inverting funtions, > > please explain how to do this, sorry if this question is dumb but I > can't find any examples on the net CPLDs have too much gain to make reliable oscillators, and 32Khz need special low-drive amplifiers to get the required phase shifts. CPLDs also have a min dV/dT for reliable clocking, so do not like low freq ( < 10MHz) sine drives. So, you need an external OSC, tho if you've chosen a MAX7032, power is not high on your list. Is size matters more than price, Maxim and Linear (?) make SOT23 resistor-set oscillators, with reasonable accuracy. Next would be to use tiny-logic gates (SOT23-5), of 74HC1GU04 for the OSC, and 74HC1G14 for the schmitt buffer. Or, you can use a 4060 (SO16), which can use a XTAL, and includes ripple counters, and can maybe save some cpld resource. Between 32KHz and low MHz, you can find Ceramic Resonators are easier to source than xtals. -jgArticle: 53318
Peter Alfke wrote: > Interesting piece of semiconductor history: > > The General Manager and VP of the RCA Solid State Division, the guy in > charge of the 4000-series COSMOS project, later joined Zilog, and in > 1984 founded Xilinx, where he now is the Chairman of the Board. > His name is Bernie Vonderschmitt. > > Peter Alfke Peter, As you know, that is the logic family I was talking about. In fact I have in my hands a COSMOS data book from RCA dated 1980. I still access the apnotes in it occasionally. There are some things in those apnotes that I just cannot find elsewhere. Theron > > ======================== > Jim Granville wrote: > > > > Power consumption and noise immunity / RFI ? > > > > A 40106 can give much lower ICC when driven from slow edges than > > HC/AHC devices. > > A 4069 will give a lower current XTAL osc than a HCU04, at the lower > > frequencies. > > A 4541 is a good low power, low cost, long timebase wdog/timer device. > > > > Their low drive, and slow edges, plus ability to ignore narrow pulses > > also make them good choices for interface aplications. > > > > -jgArticle: 53319
They are rated for up to 24 mA. Ralph Mason wrote: > "Bob" <nimby1_not_spmmm@earthlink.net> wrote in message > news:JNsaa.9090$gF3.920217@newsread1.prod.itd.earthlink.net... > > David, > > > > Typically, I use a 33ohm series/150ohm to ground as the divider network -- > > when I need to go from LVTTL (3.3V) down to LVCMOS25 (2.5V). The output > > impedance of my clock driver, along with the 33/150 divider, gets close to > > the characteristic impedance of the clock trace (50ohms). > > Isn't 18mA allot of current to expect a logic line to source? > > RalphArticle: 53320
Looks like this is it. All meat, not too much fluff. All the truth you can stomach. Delivered to your screen. And fast, too...:-) Peter Alfke =============== Joe wrote: > > ... Thanks in advance ...Article: 53321
Hi, I am using a SpartanIIE device (300k gates). There are 4 DLLs inside the chip and it really seems to do what I want. However, I can't find a way to use them. I'm using the ISE webpack, and the architecture wizard only generates vhdl code for virtex device. I only need a 'divide by 4' DLL but there is no tutorial anywhere on how to use them. Thank you very much David "Alan Raphael" <alraphael@yahoo.com> wrote in message news:3E6CF56B.8080302@yahoo.com... > If you are using Xilinx, the DCM / DLL functions can be used as clock dividers. > Other FPGA vendors have similar capability. This is probably the best way since > these can guarantee a relationship between the two clocks (i.e. zero delay). > > Alternatively, use a counter to divide the faster clock, but use the output of the > counter (with decode logic as required to produce an output which goes high for > every 4th clock period) as an ENABLE to the logic in the slower section, such that > it can only change state on every Nth clock edge. Obviously you can't use the > output of a decoder directly as a clock since it will glitch. > > David wrote: > > Hi, > > I have a system divided in two parts. One is running at 256Fs and the other > > one at 64 Fs. Is it good practice to use feed the 256Fs clock into a counter > > and use the 2nd lsb to clock the second part of the circuit? In my digital > > system design class, we have always been told to NEVER clock components with > > anything else than the master clock, and use some logic to enable/disable > > those components to lower the clock rate. However, after searching in the > > newsgroup for clock divider, it seems everyone is using a counter as a clock > > divider. What is the best way to do it? > > Thanks > > David > > > > >Article: 53322
Does anyone have experience with Synplicity's new Identify tool and can describe how it compares to Chipscope on integration into the flow, debug features, how many resources it takes to look at the same thing, etc., general satisfaction rating? Thanks.Article: 53323
Hi Joe,
There is Xilinx's XCELL journal at
http://www.xilinx.com/publications/xcellonline/index.htm if you wish to read
it online.
There are also yearly conf. proceedings from FPGA if your interest is
the research side of things:
http://portal.acm.org/browse_dl.cfm?linked=1&part=series&idx=SERIES100&coll=
portal&dl=ACM&CFID=8614677&CFTOKEN=23469739
There are also other proceedings that may be relevant. A search on
google will aid in locating them.
Alex
"Joe" <Joe@pacbell.net> wrote in message
news:3E6D0679.71C524BF@pacbell.net...
> ... Thanks in advance ...
>
Article: 53324In article <b4ja0r$1jrq$1@nserve1.acs.ucalgary.ca>, Alex Carreira <aycarrei@shaw.ca> wrote: >Hi Joe, > > There is Xilinx's XCELL journal at >http://www.xilinx.com/publications/xcellonline/index.htm if you wish to read >it online. > > There are also yearly conf. proceedings from FPGA if your interest is >the research side of things: >http://portal.acm.org/browse_dl.cfm?linked=1&part=series&idx=SERIES100&coll= >portal&dl=ACM&CFID=8614677&CFTOKEN=23469739 > > There are also other proceedings that may be relevant. A search on >google will aid in locating them. FCCM: (IEEE Symposium on Field-Programmable Custom Computing Machines) FPL: (International Conference on Field Programmable Logic and Applications) -- Nicholas C. Weaver nweaver@cs.berkeley.edu
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