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Hi all,
Please help me . I am sure the following statements will be inferred as
latches and will cause me trouble.during testing.
IF(dcnt >= 1) THEN
dcnt <= dcnt - "0001" ;
END IF;
But I want to keep the values unchanged in "dcnt" if the condition is
false. how can I do this without inferring a latch..
thanks
Lijo
Article: 53876"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3E81399C.647F6927@yahoo.com... > geeko wrote: > > > > What is the difference between he Typical gates and Maximum System gates > > specifications (snip) > I have not looked at the actual terms you are asking about, but my best > guess is that one tells you the capacity of the FPGA and the other is a > best estimate of how many of those gates are used by a typical design > that fits in the part. Of course the number of gates in the design > depends entirely on the details of how the design fits the chip. If > your design optimally uses the features of the chip you can see a much > higher gate count in the same chip as another design which just doesn't > make good use of the chip features. > > So in the real world, gates are not a good way to measure a chip. You > will do much better to fit your design to the chip and see how well it > fits. Or at least do a preliminary job of estimating by trying to > "guesstimate" the details of how your design will fit in the chip. I don't think the problem is so much different than processor speed benchmarks. Some people will calculate the maximum possible rate of instruction execution and claim that as a speed, when no real problem would ever do that. -- glenArticle: 53877
Lijo wrote:
> Hi all,
>
> Please help me . I am sure the following statements will be inferred as
> latches and will cause me trouble.during testing.
>
> IF(dcnt >= 1) THEN
> dcnt <= dcnt - "0001" ;
> END IF;
>
> But I want to keep the values unchanged in "dcnt" if the condition is
> false. how can I do this without inferring a latch..
>
>
> thanks
> Lijo
>
>
>
>
Put your statement in a synchronous process, like
no_latch:process(CLOCK,RESET)
begin
if (RESET='1') then
dcnt <= SOME_RESET_VALUE;
elsif (CLOCK'event and CLOCK='1') then
IF(dcnt >= 1) THEN
dcnt <= dcnt - "0001" ;
END IF;
end if;
end process;
That gives you a D-FlipFlop with asynchrounous reset (which you can omit if you
don't need it) and enable signal.
HTH
Jens
Article: 53878> But I want to keep the values unchanged in "dcnt" if the condition is > false. how can I do this without inferring a latch.. Erm.. how exactly did you plan to 'hold' a value without using a flipflop, latch, or other memory component? Or would a flipflip be ok? Regards, Pieter HulshoffArticle: 53879
Frey <kay.hammermueller@rz.tu-ilmenau.de> writes: > Hello everybody! > > The following problems occured when using the Max Plus II software. > I program files in VHDL. I did not find out how to successfully assign > default values for variables or signals in an architecture part, so that > > these values are valid when starting the design. > I tried out the following construct: > > ... > variable xyz : integer range 0 to 3 := 3; > ... > > But always on start the value of "xyz" is 0. > That's the trouble with the way the synthesisers work - they treat signal/variable initialisations as 'simulation-only' features - despite the fact that FPGAs can implement that functionality through configuration setup. You'll need to set xyz to 3 in a reset clause of the appropriate process to work around this. > Another problem appeared when attempting to create a user library. > > I wrote a function. I did it the same way Altera did in their libraries, > > for example in their ieee-library: > I saved the package into one .vhd file and the package body > into another one. > Both were saved into the path ../vhdl93/ownlib/ . > Obviously the library was compiled successfully. > In the VHDL-file I wanted to use that function in I declared: > > Library ieee; > use ieee.std_logic_1164.all; > library ownlib; > use xyz.all; > ... > > But when compiling the file, Altera always printed an error message that > > said: Can't open VHDL "ownlib". > > Can anyone explain, how to successfully use my own library? > I don;t know if Maxplus2 can do user libraries other than "work", try doing: library work; use work.xyz.all; HTH, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 53880
I'm working on a design for the SpartanII architecture. Everything worked fine and I was able to simulate, synthesize, translate and work with the design. because of performance issues I had to use the CLKDLLs (standard design from Xilinx/ask Sparty) to quadruple (x4) the clock. From the moment I instanciated the DLLs I encounter error messages on pins that I am sure that they are correct: ERROR:NgdBuild:455 - logical net 'spdsel' has multiple drivers ERROR:NgdBuild:466 - input pad net 'spdsel' has illegal connection Also, when I try to constraint the two DLL's used to certain locations, the translator exits on the lines with the constrains. He tells me that the DLLs i instanciated can not be found. Does anyone have any idea how to get this issues solved? I really apreciate your help, ChrisArticle: 53881
Hello Lijo,
If you have coded this piece of code, sensitive to the clock
edge, then flip flops will be inferred for this counter. So you need no
worry about any latch inference. If you have coded the same as a
combinatorial logic, then register this value with respect to the clock
and then use the registered value for the else condition. By this way,
you can avoid latch getting inferred.
Anbudan,
Anand~
"Lijo" <lijo_eceNOSPAM@hotmail.com> wrote in message
news:b5rdek$29j72m$1@ID-159866.news.dfncis.de
> Hi all,
>
> Please help me . I am sure the following statements will be inferred as
> latches and will cause me trouble.during testing.
>
> IF(dcnt >= 1) THEN
> dcnt <= dcnt - "0001" ;
> END IF;
>
> But I want to keep the values unchanged in "dcnt" if the condition is
> false. how can I do this without inferring a latch..
>
>
> thanks
> Lijo
--
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG
Article: 53882Thanks a lot, I'm going to try that out... Martin Thompson wrote: > Frey <kay.hammermueller@rz.tu-ilmenau.de> writes: > > > Hello everybody! > > > > The following problems occured when using the Max Plus II software. > > I program files in VHDL. I did not find out how to successfully assign > > default values for variables or signals in an architecture part, so that > > > > these values are valid when starting the design. > > I tried out the following construct: > > > > ... > > variable xyz : integer range 0 to 3 := 3; > > ... > > > > But always on start the value of "xyz" is 0. > > > > That's the trouble with the way the synthesisers work - they treat > signal/variable initialisations as 'simulation-only' features - > despite the fact that FPGAs can implement that functionality through > configuration setup. > > You'll need to set xyz to 3 in a reset clause of the appropriate > process to work around this. > > > Another problem appeared when attempting to create a user library. > > > > I wrote a function. I did it the same way Altera did in their libraries, > > > > for example in their ieee-library: > > I saved the package into one .vhd file and the package body > > into another one. > > Both were saved into the path ../vhdl93/ownlib/ . > > Obviously the library was compiled successfully. > > In the VHDL-file I wanted to use that function in I declared: > > > > Library ieee; > > use ieee.std_logic_1164.all; > > library ownlib; > > use xyz.all; > > ... > > > > But when compiling the file, Altera always printed an error message that > > > > said: Can't open VHDL "ownlib". > > > > Can anyone explain, how to successfully use my own library? > > > > I don;t know if Maxplus2 can do user libraries other than "work", try > doing: > library work; > use work.xyz.all; > > HTH, > > Martin > > -- > martin.j.thompson@trw.com > TRW Conekt, Solihull, UK > http://www.trw.com/conektArticle: 53883
Hi folks, does anyone have the schematics of Xilinx Virtex/VirtexE prototype board ??? Or of other proto board for Virtex/Spartan ??? Thanks !! -- Mauro FioriniArticle: 53884
Hello, I have a few question regarding a possible future V2Pro board design, and I am especially concerned with the SI issues and PCB feasibilty/complexity/cost. Since we have very little knowledge in the PCB/SI fields, we would like to contract a company to actually design the PCB. However, we are still at a very early stage of the design, and I would therfore like to know wether our idea is actually feasible or not*. We want to design a board base on the XC2VP7 device on a high-pin out package (having all of the 396 I/O pins available to the user). The specificity of the design is that we would like to connect the FPGA to eight DDR SDRAM DIMM modules, to get a 256 bit wide datapath (all modules would/could share the same address/control signal) with several GB of RAM memory. Question : Does this makes sense ? Is it such a design feasible (I imagine that such a design would put a lot of pressure on the I/O pins, with 80% of the pins using high speed signals with high toggle rate). * this is for an academic research project Tank you for your help StevenArticle: 53885
tom1@launchbird.com (Tom Hawkins) wrote in message news:<833030c0.0303251313.35d4773@posting.google.com>... > already5chosen@yahoo.com (Michael S) wrote in message > > > > > > In the first version, our butterfly adders [and subtractors] > > > simply truncated any overflow and when our client began running > > > data sets on the design, they immediately complained about the amount of > > > distortion produced. We guessed it might be attributed to overflows, > > > so we dropped in a limiting adder and were surprised by how much > > > this cleaned up the output. > > > > > > -Tom > > > > I am much more conservative than you, Tom, in my arithmetical beliefs. > > I wouldn't even consider the FFT implementation witch can overflow or > > saturate in the middle. > > I agree letting the butterflies roll over was a mistake, but > you still have to make a decision. After each FFT rank you can > either clip the result or sign extend the result by 1 > and drop the least significant bit. Either way, you loose information. > > If the spectrum is fairly flat, then it makes sense to clip because > the information is kept in the least significant bits. > But if you're expecting large spikes in the frequency domain > then it is wise to shift and drop the LSB. > This point is far from obvious to me. > Choosing which ranks to clip and which ones to shift really depends on the > frequency content of the data -- some ranks are more prone to > overflow than others. > > Of course there is a third option: grow the precision by 1 bit for > each rank. In this case the only lost incurred is from the > twiddle factor multiplication. This is a viable option if the > input data has low precision and the FFT is fairly small. > But for high precision and large point FFTs, this approach is > not practical. > > Assuming we had infinite logic we could double the precision after > each multiply and then add 1 bit for each adder. Then we wouldn't > loose anything! ;-) > > -Tom For general-purpose fix-point Radix2 FFT in hardware (exotic beast, isn't it ?) would probably go with something like this: 1. Do classic 4Mul+6Add Radix2 butterfly. Assuming N-bit precision, save full N+1 bit results of the +/- calculation. 2. In parallel with saving the results detect the overflow over N bits. Accumulate the overflow detection for the entire pass. 3. Use the accumulated overflow detection to chose between x, and x/2 as an input for the next stage. The additional hardware required for the block-floating-point approach like this is very moderate. Relatively to scaling down on every stage you need only one additional 2-way mux per multiplier. Relatively to scaling down on every 2nd stage - no additional HW at all, unless you count tiny overflow detector as a HW. The improvement over more simple approaches is probably not big in most cases, but at least it looks like the error performance of this solution is more analyzable than the alternatives.Article: 53886
> > So in the real world, gates are not a good way to measure a chip. You > > will do much better to fit your design to the chip and see how well it > > fits. Or at least do a preliminary job of estimating by trying to > > "guesstimate" the details of how your design will fit in the chip. > > I don't think the problem is so much different than processor speed > benchmarks. Some people will calculate the maximum possible rate of > instruction execution and claim that as a speed, when no real problem would > ever do that. It should also be noted that these numbers usually include an unexpected factor of two: A 2-input AND gate counts as two equivalant gates, a 3-input and counts as three, and so on. (Apperently someone decided that it would be to complicated to call a 3-input gate 1.5 eqivalent gates.) This nomenclature does not come from marketing but from academia and is related to the literal count metric for circuit size. A Flip-Flop typically counts as 6 gates. And some vendors count a 4kBit Block-RAM as 4096 Flip-FLops. Kolja SulimmaArticle: 53887
sderien@liacs.nl (sderien@liacs.nl) wrote in message news:<e072bb64.0303260216.21f29697@posting.google.com>... > Hello, > > I have a few question regarding a possible future V2Pro board design, > and I am especially concerned with the SI issues and PCB > feasibilty/complexity/cost. > > Since we have very little knowledge in the PCB/SI fields, we would like to > contract a company to actually design the PCB. However, we are still at > a very early stage of the design, and I would therfore like to know wether > our idea is actually feasible or not*. > > We want to design a board base on the XC2VP7 device on a high-pin out > package (having all of the 396 I/O pins available to the user). The > specificity of the design is that we would like to connect the FPGA to > eight DDR SDRAM DIMM modules, to get a 256 bit wide datapath > (all modules would/could share the same address/control signal) with > several GB of RAM memory. > > Question : Does this makes sense ? Is it such a design feasible (I > imagine that such a design would put a lot of pressure on the > I/O pins, with 80% of the pins using high speed signals with > high toggle rate). > > * this is for an academic research project Howdy Steven, You don't mention a clock rate for the RAM, or a data throughput requirement for the FPGA in general, so it is difficult to gauge how challenging a design this would be. Clock periods and how many levels of logic you can fit into that clock period tends to be the limiting factor of FPGAs. To answer your concern, I would not spend any time worring about the I/O pins themselves - there is no problem with fully utilizings the I/Os. I think the challenge is going to be feeding one extremely wide bus (we're talking internal to the FPGA) *TO* the I/O blocks. Doing DDR, it is effectively a 512 bit wide bus as you approach the I/O blocks - and that is just for one direction. Add the other direction, and you may have the chance for some pretty long routes - and introduce the possibility of not meeting your clock period requirement, depending on what that is. I'm definitely not saying you can't do it - I'm just making a prediction on where a trouble spot might be. Good luck, MarcArticle: 53888
Hi, I want to program an Altera EPC1 with a home-made circuit and the parallel port. Does anyone know the programming algorithm of the EPC1 to do it? I know that EPC1 need 10 volts into Vccp and 6.5 volts into Vcc, but I don´t know the handshake of the pins DATA,DCLK,CS and nOE. Thanks in advanced.Article: 53889
Steven, Go to our SI central web page. Go through the 10 point checklist (even if you haven't started yet --- especially because you haven't started yet!). http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Signal%20Integrity Buy a SI analysis tool. Get Hspice (as it is the only simulator as of today supported for the MGT SI kit). Note: Mentor ICX and Cadence SpectraQuest both support dual use simulations (simulate the MGT part with your Hspice license). Hyperlynx is my favorite for quick and easy "what if" runs. Run the SI analysis for your wide buses, MGTs, in fact, for every signal in a "what if" mode (guessing at trace lengths, etc). Don't forget the configuration signals! Correct all observed problems. Note carefully the SSO guidelines. Use the absolute weakest and slowest IO driver you can to do the job. If you get close to the SSO guideline limits, then you can expect the design to be even more challenging (as the next section becomes a real challenge). For the SSO guideline table, we have assumed BEST bypassing and power distribution, and less than 200 mV P-P ground bounce. Read app note xapp623. Realize that you will have to follow the BEST practices exactly as described for this application (no reduction in bypass caps, etc.). http://www.xilinx.com/xapp/xapp623.pdf Read the tech Xclusives on slack and jitter, pcb layout, IBIS, etc. http://www.xilinx.com/support/techxclusives/techX-home.htm Good luck, this is a 9 out 10 for a challenging design. Once you have a layout, please ftp it to our ftp site (look up "ftp site" in the support.xilinx.com for instructions). We are happy to evaluate layouts and offer comments to customers (and institutions) when we have the time to do so. For customers, please open a case and request your layout to be examined for SI and PDS issues. For institutions (schools and universities) please notify me at austin@xilinx.com (note that I can not make this a high priority item, and note thatthe University program has its own support structure that may provide a much faster response - http://www.xilinx.com/univ/index.htm ) Austin "sderien@liacs.nl" wrote: > Hello, > > I have a few question regarding a possible future V2Pro board design, > and I am especially concerned with the SI issues and PCB > feasibilty/complexity/cost. > > Since we have very little knowledge in the PCB/SI fields, we would like to > contract a company to actually design the PCB. However, we are still at > a very early stage of the design, and I would therfore like to know wether > our idea is actually feasible or not*. > > We want to design a board base on the XC2VP7 device on a high-pin out > package (having all of the 396 I/O pins available to the user). The > specificity of the design is that we would like to connect the FPGA to > eight DDR SDRAM DIMM modules, to get a 256 bit wide datapath > (all modules would/could share the same address/control signal) with > several GB of RAM memory. > > Question : Does this makes sense ? Is it such a design feasible (I > imagine that such a design would put a lot of pressure on the > I/O pins, with 80% of the pins using high speed signals with > high toggle rate). > > * this is for an academic research project > > Tank you for your help > > StevenArticle: 53890
johnjakson@yahoo.com (john jakson) wrote in message > Of course thats obvious for most smaller & medium size chips where the > lost yield would be <1%. But I see no practical reason why for very > high value parts ie super size chips, more work couldn't be expended > to break off the top & bottom rows and vertical saw the separated rows > by hand. You'd break too many in the process, which nullifies the advantage. Besides, you can't just nilly willy offset the rows against each other as you need to overlap the scribelines in certain well-defined ways. Xilinx doesn't operate fabs last I looked and the foundries certainly don't like if you're trying to play on their turf. They'd rather give you 10% off on the wafer price... Same thing for the dicing, which is typically done in a packaging center. Good luck trying to instantiate the procedure you propose and get even an estimate on backend yield. > Still doesn't explain why 1 die located off xy grid. There is none off grid. I see two shots that have a process monitor inset middle left and right and another inset lower left and upper right, possibly with a different design. What you mistake for an offset chip is simply an area where there is nothing. This is clearly a development wafer, with two or three different reticles used for it and the map not really optimized in other ways as well. Production wafers would presumably look quite a bit different. > Is it necessary to use the same final process for $10 parts v parts > that could be worth several thousand $. Yes, if there is no other process that delivers the same result. Also, since a large part of the product cost already is in the package (and the rest in the test), you really don't want to make that step even more costly than it already is. Ten percent of ten percent of the product cost just doesn't justify taking many risks. Achim.Article: 53891
Marc Randolph wrote:
> sderien@liacs.nl (sderien@liacs.nl) wrote in message news:<e072bb64.0303260216.21f29697@posting.google.com>...
> > Hello,
> >
> > I have a few question regarding a possible future V2Pro board design,
> > and I am especially concerned with the SI issues and PCB
> > feasibilty/complexity/cost.
> >
> > Since we have very little knowledge in the PCB/SI fields, we would like to
> > contract a company to actually design the PCB. However, we are still at
> > a very early stage of the design, and I would therfore like to know wether
> > our idea is actually feasible or not*.
> >
> > We want to design a board base on the XC2VP7 device on a high-pin out
> > package (having all of the 396 I/O pins available to the user). The
> > specificity of the design is that we would like to connect the FPGA to
> > eight DDR SDRAM DIMM modules, to get a 256 bit wide datapath
> > (all modules would/could share the same address/control signal) with
> > several GB of RAM memory.
> >
> > Question : Does this makes sense ? Is it such a design feasible (I
> > imagine that such a design would put a lot of pressure on the
> > I/O pins, with 80% of the pins using high speed signals with
> > high toggle rate).
> >
> > * this is for an academic research project
>
> Howdy Steven,
>
> You don't mention a clock rate for the RAM, or a data throughput
> requirement for the FPGA in general, so it is difficult to gauge how
> challenging a design this would be. Clock periods and how many levels
> of logic you can fit into that clock period tends to be the limiting
> factor of FPGAs.
>
> To answer your concern, I would not spend any time worring about the
> I/O pins themselves - there is no problem with fully utilizings the
> I/Os.
>
> I think the challenge is going to be feeding one extremely wide bus
> (we're talking internal to the FPGA) *TO* the I/O blocks. Doing DDR,
> it is effectively a 512 bit wide bus as you approach the I/O blocks -
> and that is just for one direction. Add the other direction, and you
> may have the chance for some pretty long routes - and introduce the
> possibility of not meeting your clock period requirement, depending on
> what that is.
>
> I'm definitely not saying you can't do it - I'm just making a
> prediction on where a trouble spot might be.
>
> Good luck,
>
> Marc
Hi,
I would tend to disagree with Marc on one issue. Utilizing all the pins depends on the drive level and the
drive speed. Xilinx specifies the number of simutaneous switching outputs per bank depending on the speed and
drive level and also the output signal type. I would check that out before you commit to much effort to the
design. Also, routing that many i/o pins could be a little tight especially when you are routing 100% of the
pins. It certainly will increase the number of layers (and cost). You will want to be very careful in selecting
a PCboard fab house. See the hardware user guide for more info. Also see Answer Record # 13572.
I would definately agree on the internal routing issues he mentioned. However, I have no experience with this
specific type of project.
Theron Hicks
Article: 53892In article <3E81D568.6D7D0B32@egr.msu.edu>, Theron Hicks <hicksthe@egr.msu.edu> wrote: > I would definately agree on the internal routing issues he >mentioned. However, I have no experience with this >specific type of project. Routing 512 bit signals in an FPGA is nothing, really. In fact, probably want to make it 1024 and slow the internal toggle rate. In a Spartan II for my AES datapath benchmark, the subkey generation (a 128 bit datapath, half going left, half going right, meeting back in the middle) fit in the pitch of 1 BlockRAM. Routing 2x or 4x data to and from all pins is not a big deal, those parts have a LOT of wires, especially if you floorplan it. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 53893
That is weird, and I am sure Marketing ( for all its other foibles) is not responsible for this stupidity. I also do not believe that this silly method is part of FPGA gate counting. When I was involved, we reduced everything to 2-input gates, and a 2-XOR became 4 gates. Peter Alfke ========================= Kolja Sulimma wrote: > A 2-input AND gate counts as two equivalant gates, a 3-input and > counts as three, and so on. > (Apperently someone decided that it would be to complicated to call a > 3-input gate 1.5 eqivalent gates.) > > This nomenclature does not come from marketing but from academia and > is related to the literal count metric for circuit size. > >Article: 53894
Hello Franz, We've found the easiest way to start your debugging from the beginning of main using GDB is to put a small conditionally compiled "while (spin == 1);" statement right up at the top of main. This will stop your software here when the board is reset, and give you time to fire up GDB. You can then change the spin variable in GDB and go on with your debugging. If you try to restart while GDB is connected, there can be problems because the bootloader does some memory map manipulation that will likely confuse the debugger. The elf file you load into GDB does not match the context of the board until the bootloader finishes, so it's not until that point that you'll want to load the elf file. Using the spin-loop mentioned above allows the bootloader to finish booting the board, then lets you start GDB and load the elf file before the real software on the board starts running. Hope this helps. Regards, -Nathan Knight Altera Corp. Franz Hollerer <nospam@nospam.org> wrote in message news:<newscache$s59bch$gp41$1@news.sil.at>... > Hi, > > I now found that I can use the gdb to interrupt the already > downloaded an running hello example and go from this point step by step. > > If I set a breakpoint at main() and restart the program gdb says: > > > Error: You can't do that without a process to debug. > > What does this message mean? How can I use the gdb to restart > the program to allow debuging from the very begin of the program? > > Best regards, > Franz Hollerer > > > Franz Hollerer wrote: > > Hi, > > > > I try to experiment with the "hello" example described in the > > Altera Excalibur EPXA1 Development Kit - Getting Started User Guide. > > > > I want to use the GNUPro Debugger to debug the program. I can > > start the debugger as described in the document, but setting > > breakpoints, single steps etc. does not work. > > > > Are there some restrictions for using the gdb? e.g. Ram, Flash? > > > > Best regards, > > Franz > >Article: 53895
"Mike Treseler" <tres@fluke.com> ha scritto nel messaggio news:3E80D1B4.7000306@fluke.com... > The style problem is that the output port is never driven. > No output, no gates. No, it wasn't this (I read the registers somewhere else, I haven't copied the entire code in the previous message). In fact, if I read/write the array by accessing the whole row instead of the single bit, the code works: signal one_bit: std_logic; signal one_row: std_logic_vector(7 downto 0); [...] type mem is array (15 downto 0) of std_logic_vector(7 downto 0); [...] variable memoria: mem; variable index_write_word: integer; variable index_write_bit: integer; [...] memoria(index_write_word)(index_write_bit) := one_bit; -- NO! memoria(index_write_word) := one_row; -- YES! Another user told me via e-mail that it is a known bug of XST, which isn't able to index a portion of an array with a integer number/range. I'm using ISE 4.x, but he said that the problem is there even with 5.x versions. -- LorenzoArticle: 53896
"Lijo" <lijo_eceNOSPAM@hotmail.com> wrote in message news:b5rdek$29j72m$1@ID-159866.news.dfncis.de... > Hi all, > > Please help me . I am sure the following statements will be inferred as > latches and will cause me trouble.during testing. > > IF(dcnt >= 1) THEN > dcnt <= dcnt - "0001" ; > END IF; > > But I want to keep the values unchanged in "dcnt" if the condition is > false. how can I do this without inferring a latch.. Describe what you do expect it to do, and someone might suggest something. Since you are storing back into dcnt, I don't think there is any other way. If you store into a different variable, it could infer a MUX instead. I prefer to write structural model Verilog, where this problem doesn't occur. -- glenArticle: 53897
"Brad Smallridge" <bsmallridge@dslextreme.com> writes: > I just built a board with a 39K100. > Are there any Cypress users in this discussion group? I've used their older 37256 and 37512 parts, and was reasonably happy with them.Article: 53898
Austin Lesea <Austin.Lesea@xilinx.com> wrote: >> Always fun to listen to the chatter, >> All of this was considered when we implemented 3des. >> No one has broken it yet, so go ahead and have fun! nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) writes: > And probably nobody has used it in a system where there is a >$100k > payout if you can break this particular form of security, Actually, if you can break 3DES you can get a ***MUCH*** larger payout than that. The banking industry uses 3DES for their transactions. So the incentive to develop an effective means of breaking 3DES is quite high. Either no one has done it yet, or they're keeping quiet.Article: 53899
"¼Õ±â¿µ" <elcielo0@hitel.net> writes: > I want. > SMC34c60 - www.smsc.com And how much are you prepared to spend on it?
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