Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 53375

Article: 53375
Subject: Development boards with optics
From: "Patrick MacGregor" <patrickmacgregor@comcast.net>
Date: Wed, 12 Mar 2003 08:51:19 -0500
Links: << >>  << T >>  << A >>
I'm looking for FPGA development boards with optics availble.  I could use
both telecom (OC3/12/48) and datacom (GbE) front-ends.  Does anyone know
vendors who sell this type of thing?



Article: 53376
Subject: Re: comp.arch.fpga : VCC shorted to GND within FPGA???
From: "Jeff Cunningham" <jcc@sover.net>
Date: Wed, 12 Mar 2003 09:02:19 -0500
Links: << >>  << T >>  << A >>

If you have multiple boards and are willing to risk one, hook a 20 amp
low voltage power supply between VCC and GND. Follow the smoke to where
the short is. I've used this to find solder bridge type shorts and
internal layer shorts on prototypes (not recommended in production, for
obvious reasons). If you are lucky, you'll apply power, hear a pop as
the short is vaporized, and it will start working normally. If the
xilinx melts it probably means you got the pinout wrong. When the short
opens, you'll get the full power supply voltage on the rails, so don't
use a supply that exceeds the part's absolute max rating for VCC.

JC




Article: 53377
Subject: footprints
From: Mike Hubert <mph@xiphos.ca>
Date: Wed, 12 Mar 2003 14:17:47 GMT
Links: << >>  << T >>  << A >>
Hi,

I am about to get started on the design of a board containing two Xilinx 
FPGAs: a Virtex II, and a VirtexII Pro, both in FG256 packages.

I am looking for a footprint source for these components... may it be a 
friendly individual, or a company. I checked with ECS and they don't have 
them. I know designing them myself wouldn't be too much of a pain but the 
fact of the matter is that we are extremely pressed for time and have to 
save every minute I can!

Any tips would be greatly appreciated.

Thanks

Mike Hubert
Xiphos Technologies Inc.

Montreal, Canada

Article: 53378
Subject: Re: Cyclone power up problem
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 12 Mar 2003 08:12:27 -0800
Links: << >>  << T >>  << A >>
Jim,

Answers below.

Austin

Jim Granville wrote:

> Austin Lesea wrote:
> >
> > Jim,
> >
> > We have also seen sensitivities at specific hot temperatures.
>
> By this I presume you are saying the I_StartMAX vs Temp curve is not
> monotonic,
> but can have one (or more?) peaks ?

It just peaks at different temps on different lot devices.

>
>
> > Unless you are willing to test every temp, on every part......very scarey.
> >
> > In order to have a spec that results in 100% power on success, it takes a lot of
> > work.
> >
> > We know.  Been there, done that.  Don't want to ever go there again.
>
> OK, so we take from this (and other comments) that the very-newest
> Xilinx devices have reduced the problem - but there are still
> design starts with older families. You may have the luxury
> of never going there again, field designers are not so lucky :)

Well, not exactly true, the 12" production material for Virtex E, and Spartan IIE has
30% (worst case -- usually closer to 80%) LESS current required to power on from
Vccint, and has no current requirement if Vcco is before Vccint.  These two changes to
this material have resulted in a total drop in any customer issues in new designs to
zero in the last 6 months.  We still require that one follows the data sheet
(obviously).

>
>
> So, I still believe models that allows designers to see the differences
> in families, and get a handle on the numbers, is a good idea.
> Yes, even for the very newest Xilinx devices.
>
> Has anyone tried to model this ?

Peak current is of no consequence if you use a linear current regulator, and do not
use a current foldback or trip regulator (unless the foldback or trip is delayed by 20
ms).  If you supply the datasheet minimum current number, it is guaranteed to start
up.

The simple model for the startup is a forward baised diode that stays there for ~
3ms.  If you can pump 5 amperes into it, it will "take it" (and clean out and power on
much faster).  If you supply the minimum current in the data sheet, it will take that
as well, and also power up cleanly.  So a diode, and time switch that stays closed to
the diode for 3 ms is a good model.  I don't think that has helped, has it?  Maybve it
has, as now you can see why a trip or foldback regulator can not be used.

TI has a web page for powering FPGAs
(http://focus.ti.com/docs/apps/catalog/resources/appnoteabstract.jhtml?abstractName=slva086)

Micrel has a web page (http://www.micrel.com/_Xtra/Xilinx/Xilinx.shtml#virtex),

Summit Micro has applications notes for Virtex/Spartan
(http://www.summitmicro.com/tech_support/notes/note31/note31-01.htm)

and so on, and so forth.

A Search on Google for "powering virtex e" yields a numebr of useful hits.



>
>
> -jg


Article: 53379
Subject: Re: footprints
From: John Larkin <John.Larkin>
Date: Wed, 12 Mar 2003 08:26:14 -0800
Links: << >>  << T >>  << A >>
On Wed, 12 Mar 2003 14:17:47 GMT, Mike Hubert <mph@xiphos.ca> wrote:

>Hi,
>
>I am about to get started on the design of a board containing two Xilinx 
>FPGAs: a Virtex II, and a VirtexII Pro, both in FG256 packages.
>
>I am looking for a footprint source for these components... may it be a 
>friendly individual, or a company. I checked with ECS and they don't have 
>them. I know designing them myself wouldn't be too much of a pain but the 
>fact of the matter is that we are extremely pressed for time and have to 
>save every minute I can!
>
>Any tips would be greatly appreciated.
>
>Thanks
>
>Mike Hubert
>Xiphos Technologies Inc.
>
>Montreal, Canada

What do you mean by 'footprint source'? If you want the CAD layout,
what file format?

John


Article: 53380
Subject: Re: RESET --- Synchronous Vs Asynchronous
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 12 Mar 2003 08:34:48 -0800
Links: << >>  << T >>  << A >>


LIJO wrote:
,
> which reset is better synchronous or asynchronous

Synchronous is better if:
the chip offers this feature and you can afford the potential loss of
other input variables,
and
you can afford to wait for the reset action to be delayed until after
the next clock edge.

These conditions are often not met. That's why there are so many
asynchronous resets.

Peter Alfke, Xilinx Applications

Article: 53381
Subject: Re: RESET --- Synchronous Vs Asynchronous
From: Pieter Hulshoff <phulshof@xs4all.nl>
Date: Wed, 12 Mar 2003 17:35:16 +0100
Links: << >>  << T >>  << A >>
> which reset is better synchronous or asynchronous

Depends on your application, but I personally avoid asynchronous resets like the 
plague. At least synchronize the thing properly before you use it in your block 
or you'll be bughunting for a long time.

Regards,

Pieter Hulshoff

Article: 53382
Subject: Re: FPGA new problems.
From: spam_hater_7@email.com (Spam Hater 7)
Date: 12 Mar 2003 09:04:06 -0800
Links: << >>  << T >>  << A >>
Two problems:
1) wait20msCounter is never getting reloaded.  (little problem)
2) functionSetState is set in more than one always block.  (big problem)

FWIW, this is a Verilog question, not an FPGA question.

SH

javaguy11111@yahoo.com (db) wrote in message news:<903bda3b.0303111645.452b1203@posting.google.com>...
> Not sure if this should go to comp.arch.fpga or comp.lang.verilog
> 
> I am new to working with Verilog and FPGA's. I recent bought a board
> from Digilent. So far I have managed to do fairly simple things like
> get leds to flash on the IO board when a button on the io board is
> pressed.  I have also
> been working through some online tutorials. I thought I was ready to
> tackle getting the LCD display up an running. However I have run into
> a complete brick wall.
> 
> I am trying to initialize the LCD display, which is several steps, but
> I can not even get past the first step.
>  
> Basically I am running into an error saying 
> 
> WARNING:Xst:524 - All outputs of the instance <clockDiv> of the block
> <ClockDiv> are unconnected in block <LCDMod>. This instance will be
> removed from the design along with all underlying logic.
> 
> When I try to look at the schematic, there is nothing there.
> Everything has been optimized away!
> 
> ClockDiv is just a divide by counter to step the clkIn from 50Mhz to
> 1Mhz.  intClk is being referenced. I am running into several other
> issues, but maybe if I can understand why Xst thinks intClk is not
> being used, I can understand the other problems. The Xilinx answer
> database was of little help.
> 
> Is it my imagination or does Verilog in the tutorials bear little
> resemblence to Verilog when applied to FPGA's?
> 
> Thanks in advance for any suggestions.
> 
> module LCDMod(clkIn,lcdReady,reset);
> //Assuming clockDiv instance is 1Mhz
> parameter wait20ms=20000;
> parameter wait1ms=1000;
> parameter wait37us=37;
> parameter wait1p52ms=1520;	//Wait 1.52 milliseconds
> 
> input clkIn,reset;
> output lcdReady;  //Will be true when lcd is ready to use
> reg wait20msState,functionSetState;
> reg [15:0] wait20msCounter;
> reg lcdReadyBuffer;
> 
> wire intClk;   //I have tried this commented and not commented out.
>                // Same problem
> ClockDiv #(50) clockDiv (clkIn,intClk);
> 
> //Wait 20ms state
> always @(posedge intClk or posedge reset)
> begin
> 	if(reset) begin
> 		wait20msState=1;
> 		wait20msCounter=wait20ms;
> 	end
> 	else if(wait20msState) begin
> 		if(wait20msCounter==0)begin
> 			wait20msState=0;
> 			functionSetState=1;
> 		end
> 		else begin
> 			wait20msCounter=wait20msCounter-1;
> 		end
> 	end
> 
> end
> 
> //Function set state
> always @(posedge intClk or posedge reset)
> begin
> 	if(reset) begin
> 		functionSetState=0;
> 	end
> 	else begin
> 		functionSetState=1;
> 	end
> end
> 
> 
> endmodule

Article: 53383
Subject: Re: Cyclone power up problem
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Wed, 12 Mar 2003 17:05:03 GMT
Links: << >>  << T >>  << A >>
>
> But since you mention the diode feed forward solution, I would like to see
the
> scope shots, as it is quite clever.  It might be something we consider
adding to
> xapp451.

Here it is: http://www.jopdesign.com/cyclone/powerup.jsp

Comments are welcome

Martin Schoeberl

>
> austin@xilinx.com
>
> Austin
>
> Martin Schoeberl wrote:
>
> > Hello Thorsten,
> >
> > > Xilinx provides a nice app note which describes you problem (Power on
> > surge)
> > > and gives an advices how to deal with it.
> > > Xilinx app notes 450 (Power-On requirements for the Spartan II and
Spartan
> > > IIe famlies)
> > > and 451 (Power Assist circuits for the Spartan II and Spartan IIe
> > families)
> > >
> > Thanks for the information. These app notes describe the problem in
detail.
> > Would be nice if these information is available for the Altera FPGAs.
> >
> > Just Power Assist circuits look for me like a little work around. I've
found
> > a solution ('work around') for my board: Adding some 'charge' from the
3.3V
> > over two diodes to the 1.5V to help the drop-down regulator to start up.
> >
> > If there is interest in some oscilloscop pictures about the problem and
an
> > equivilant circuit to test your power supply for Cyclone devices I can
write
> > a summary on my web site.
> >
> > Martin
> >
> > > "Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag
> > > news:TP5aa.79536$AV5.998926@news.chello.at...
> > > > I've built a board with the Cyclone from Altera. First board was ok,
but
> > > on
> > > > some of the following there was a problem with startup of the
Cyclon.
> > > >
> > > > For the core voltage (1.5V) I use a drop-down regulator from Linear
> > > > Technology (LTC3405) as described in the app. note (AN257). But the
core
> > > > voltage did not reach the 1.5V. The regulator stopped at 0.5 - 0.8
V. I
> > > > examined the problem by building an extern regulator.
> > > >
> > > > Starting the regulator without load and than attaching the VCCINT
pins
> > > from
> > > > the FPGA leads to a successfull start. The output capacitor (4u7)
> > supplies
> > > > enough initial current.
> > > >
> > > > Measuring the current during startup yields to following results:
> > > > First few us the Cyclone needs about 0.7A! Falling down to 200 mA
and
> > > > staying there for about 15 us (I think for internal startup). After
that
> > > it
> > > > dropps to a few mA.
> > > > The LCT3405 is a 300 mA regulator with a peak current of about 650
mA.
> > It
> > > > can not deliver this peak current during it's own start.
> > > >
> > > > Just wanted to tell this story (of hidden problems of a new family)
for
> > > > others who want to work with this new (still exciting) FPGAs to not
run
> > > into
> > > > the same troubles.
> > > >
> > > > Martin Schoeberl
> > > >
> > > >
> > >
> > >
>



Article: 53384
Subject: Re: footprints
From: Mike Hubert <mph@xiphos.ca>
Date: Wed, 12 Mar 2003 17:08:00 GMT
Links: << >>  << T >>  << A >>
John Larkin <John.Larkin> wrote in
news:4rnu6v0dj3kjlpmegovi7fb2o88g3roeop@4ax.com: 

> 
> What do you mean by 'footprint source'? If you want the CAD layout,
> what file format?
> 
> John
> 
>

By source I mean someone who can kindly pass it along to me, or a company 
from which I can purchase it.

I use Orcad Layout, so if you're offering me a footprint, you could send me  
a library file, that'd be awesome. I could potentially also deal with 
Protel format...

mph@xiphos.ca

THANKS!!!

Mike.
 


Article: 53385
Subject: Re: DRC/ LVS
From: alexg@ottawa.com (Alexander Gnusin)
Date: 12 Mar 2003 09:18:36 -0800
Links: << >>  << T >>  << A >>
"LIJO" <lijo_eceNOSPAM@hotmail.com> wrote in message news:<b4muk5$21iq8e$2@ID-159866.news.dfncis.de>...
> hi,
> can anyone tell me
> What is design Rule Check and Layout vs schematic
> 
> thanks
> Lijo

DRC (design rule check) is validation of numerous geometrical
constraints as between different layout layers, as within the same
layer. These constrains use technology parameter lambda for unit
length (name of technology is usually the same as this parameter).
For example, width of polysilicon line is not less than 2*lambda etc.

LVS is verification that your layout topology functionally matches
original  schematics used to build this layout. During this stage,
tools extract schematics from the given layout and topologically
compare it with original schematics.

Regards,
Alexander

Article: 53386
Subject: Re: DRC/ LVS
From: Muzaffer Kal <kal@dspia.com>
Date: Wed, 12 Mar 2003 17:20:11 GMT
Links: << >>  << T >>  << A >>
On Wed, 12 Mar 2003 15:04:36 +0530, "LIJO"
<lijo_eceNOSPAM@hotmail.com> wrote:

>hi,
>can anyone tell me
>What is design Rule Check and Layout vs schematic
>
>thanks
>Lijo
>

In IC design DRC is used to check whether your layout is conforming
with all the rules the foundry issued with respect to widths,
distances etc of all the individual layers in the layout i.e. minimum
metal widths, metal to metal distances, poly to nwell distances etc.
LVS is used to compare your schematic against the layout by extracting
devices from the layout (by using the device recognition and
connectivity rules) and checking each layout device for a
corresponding schematic device and assuring that they are also
similarly connected.

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

Article: 53387
Subject: Re: Cyclone power up problem
From: "Jonathan Bromley" <jonathan.bromley@doulos.co.uk>
Date: Wed, 12 Mar 2003 17:31:38 -0000
Links: << >>  << T >>  << A >>
"Martin Schoeberl" <martin.schoeberl@chello.at wrote:
> Here it is: http://www.jopdesign.com/cyclone/powerup.jsp

Very nice.

One thing that's fairly clear is that the transient response
of your LT3405 regulator is not brilliant - in the last-but-one
oscillograph the regulator is hanging around for over 2us
before it even begins to respond to the load transient.
That's not bad for a 1MHz switcher, but not good enough.

I wonder if your 2-diode-and-resistor arrangement could be
replaced with some crude but fast linear regulator, arranged
to source about 0.1V less than the switcher, so that it's
doing no work at all in the "normal" case but holds up the
supply to about 1.3-1.4V during startup?  Its efficiency
would not be a concern, since it would be "off" during
normal operation.  And its output transistor could be
quite small (as long as it has a low UceSAT) because it's
dissipating power for only a few milliseconds.

Time to get out the napkins and pencil again :-)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Article: 53388
Subject: Re: RESET --- Synchronous Vs Asynchronous
From: Mike Treseler <tres@fluke.com>
Date: Wed, 12 Mar 2003 09:44:50 -0800
Links: << >>  << T >>  << A >>
LIJO wrote:

> which reset is better synchronous or asynchronous

Asynch reset/preset is directly supported in FPGAs
and has the advantage of sure recovery
of critical outputs from a panic state.

An synchronous deactivation of the reset pulse
is cleanest.

Consider handling "illegal" register values
gracefully in your logic rather the depending on reset values.


     -- Mike Treseler


Article: 53389
Subject: TEMPERATURE constraint in UCF
From: Utku Ozcan <utku.ozcan@netas.com.tr.spamela>
Date: Wed, 12 Mar 2003 20:06:08 +0200
Links: << >>  << T >>  << A >>

We have design targetted to a XCS30-4-PQ240C which fails during
heat tests. Product is being tested at -20 degrees but our commercial
FPGA is heated with special equipment to +20 degrees on package
surface.

The point is that the design fails during this testcase, and we wonder
whether it is of a good practice to emulate this test with TEMPERATURE
constraint in UCF file. We would like to hear the experiences around.

Utku



Article: 53390
Subject: Modular Design: Dangerous warnings..
From: "Eduardo Wenzel Brião" <briao@inf.pucrs.br>
Date: Wed, 12 Mar 2003 10:22:02 -0800
Links: << >>  << T >>  << A >>

Hi 
I developed a small project using Virtex II XC2V1000fg456-4 model. This project is made with 
two modules (one reconfigurable and one fixed) that using two displays of FPGA. 
There is only one communication signal between the modules. 
This communication signal is the clock. According XAPP290, 
 I can use a CLOCK signal shared with two or more modules without using bus macros. 
I can perform all the Modular Design flow and it generated the total and partial 
bitstreams. But when I download the bitstream generated by Final Assembly Phase 
of the Modular Design, it doesn´t work right. The bar leds of FPGA became caothic. 
So, It was happening some warnings on the NGDBuild Software on the Initial Budgeting 
Phase of Modular Design. They are showed below: 

Line command: ngdbuild -p xc2v1000fg456-4 -modular initial myTop.edf -aul 

Checking timing specifications ... 
WARNING:XdmHelpers:625 - No instances driven from signal "clk" are valid for 
   inclusion in TNM group "clk". A TNM property on a pin or signal marks only 
   the flip-flops, latches and/or RAMs which are directly or indirectly driven 
   by that pin or signal. 

WARNING:XdmHelpers:644 - No appropriate elements were found for the TNM group 
   "clk". This group has been removed from the design. 
WARNING:XdmHelpers:807 - The period specification "TS_clk" was removed because 
   the "clk" group was removed. 

When I execute the NGDBUILD tool on the Active Module Implementation Phase on 
the Modular Design Flow, it happens one warning too: 

Line command: ngdbuild -p xc2v1000fg456-4 -modular module -active MyModule 
..\..\Top\Initial\MyTop.ngo 

WARNING:NgdBuild:479 - The input pad net 'clk' is driving one or more clock 
   loads that should only use a dedicated clock buffer. This could result 
   in large clock skews on this net. Check whether the correct type of BUF 
   is being used to drive the clock buffer. 

And finally, when MAP tool is executed, it issues some warnings: 

Line command: map -pr b myTop.ngd myTop.ncd myTop.pcf 

WARNING:MapLib:328 - Block "NameBlock" is not a recognized logical block. The mapper will 
   continue to process the design but there may be design problems if this block 
   does not get trimmed. 
WARNING:DesignRules:575 - Netcheck: The clock signal clk_int is not driven by a 
   GCLK which is not allowed for modules in partial reconfiguration mode. 

Could someone help me, just telling me some tips to avoid these warnings? 

Eduardo Wenzel Brião 
briao@inf.pucrs.br 
Catholic University of Rio Grande do Sul State 
Porto Alegre City 
Brazil 






Article: 53391
Subject: Re: Cyclone power up problem
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Thu, 13 Mar 2003 07:29:35 +1300
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
<snip> 
> The simple model for the startup is a forward baised diode that stays there for ~
> 3ms.  If you can pump 5 amperes into it, it will "take it" (and clean out and power on
> much faster).  If you supply the minimum current in the data sheet, it will take that
> as well, and also power up cleanly.  So a diode, and time switch that stays closed to
> the diode for 3 ms is a good model.  I don't think that has helped, has it?  Maybve it
> has, as now you can see why a trip or foldback regulator can not be used.

 Yes it has helped * - and you could add that the time-switch has a
current
threshold as well.
 One interesting behaviour of this effect seems to be that it behaves in
a
charge-related manner ( more current == less time ) ONLY above a certain
current threshold: below that threshold, and it is possible to never
start up.
 Correct ?

* Flyback SMPS, with primary current limiting, can deliver higher
currents 
at lower voltages - and info on the load-line of the FPGA (as above) 
can help design this.
 Some supplies foldback differently, and just where the IV curve 
goes depends on the FPGA load line.

-jg

Article: 53392
Subject: PCI parity question
From: "CC Nguyen" <>
Date: Wed, 12 Mar 2003 10:45:07 -0800
Links: << >>  << T >>  << A >>
Hi all, 
I am newbie to PCI, please help me to clarify this. 

For my understand from PCI spec, the parity is calculated by counting "The number of '1's on AD[31:0], C/BE[3:0], and PAR equals an even number" then PAR =1, else PAR =0. 

Here's my assumption, the PAR is a function of itself ( previous state of PAR, I assume the calculation takes 1 clock ) 

If the above assumption is correct, this is what I think it will happen: 

1)During a "write data phase", if AD[31:0] and C/BE[3:0] are constants then PAR will toggle every data cycle. Is that true? 

2)During address phase, the PAR may be floating ( there's no previous PAR ) then how can we calculate the address parity? 


Article: 53393
Subject: Re: Cyclone power up problem
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Thu, 13 Mar 2003 07:55:51 +1300
Links: << >>  << T >>  << A >>
Martin Schoeberl wrote:
> 
> >
> > But since you mention the diode feed forward solution, I would like to see
> the
> > scope shots, as it is quite clever.  It might be something we consider
> adding to
> > xapp451.
> 
> Here it is: http://www.jopdesign.com/cyclone/powerup.jsp
> 
> Comments are welcome

 Interesting results.
one comment : 0.75 ohms is relatively high, as a current sniffer, and
will change the circuit behaviour.
It would be interesting to see Vcc/Icc on the same graph

Working from the dipping-Vcc plot,  i = CdV/dT gives for
Assume 5uF ( usually > label ), and 0.6V / 3uS gives 
appx 1A from the Cap, and appx 0 from the SMPS, as it has not yet woken
up :)

 You can also 'make' a 1+fractional diode out of a transistor and two
resistors, 
as a Vbe multiplier, (and get some Ron slope control from the Hfe ) 
so that should you find 2.3 Diode drops is ideal, it can be be simply
arranged.

-jg

Article: 53394
Subject: Re: Cyclone power up problem
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 12 Mar 2003 11:35:46 -0800
Links: << >>  << T >>  << A >>
Jim,

By the way, since this discussion is about something I am familiar with, none of this
information should be applied to any other non-Xilinx FPGA product.

See below,

Austin

Jim Granville wrote:

> Austin Lesea wrote:
> <snip>
> > The simple model for the startup is a forward baised diode that stays there for ~
> > 3ms.  If you can pump 5 amperes into it, it will "take it" (and clean out and power on
> > much faster).  If you supply the minimum current in the data sheet, it will take that
> > as well, and also power up cleanly.  So a diode, and time switch that stays closed to
> > the diode for 3 ms is a good model.  I don't think that has helped, has it?  Maybve it
> > has, as now you can see why a trip or foldback regulator can not be used.
>
>  Yes it has helped * - and you could add that the time-switch has a
> current
> threshold as well.
>  One interesting behaviour of this effect seems to be that it behaves in
> a
> charge-related manner ( more current == less time ) ONLY above a certain
> current threshold: below that threshold, and it is possible to never
> start up.

Yup.

>
>  Correct ?

Charge is a good way to look at it, yes.

>
>
> * Flyback SMPS, with primary current limiting, can deliver higher
> currents
> at lower voltages - and info on the load-line of the FPGA (as above)
> can help design this.
>  Some supplies foldback differently, and just where the IV curve
> goes depends on the FPGA load line.

Since this is at 0.7 volts (approx) it usually means that it trips the "short circuit"
detect of the regulator.  Since this threshold is uncontrolled in most switchers, it is not
predictable.

>
>
> -jg


Article: 53395
Subject: Buying memory for FPGA...
From: zumbita00@yahoo.es (Pepito Perez)
Date: 12 Mar 2003 11:38:08 -0800
Links: << >>  << T >>  << A >>
Hello,

    I bought while ago two FPGA from Altera, they are called APEX and
ACEX, their distributor sent me both FPGA, but... they came without
memory, i have talked to them and they said they could sell me memory,
and it is almost as expensive as FPGA. They gave me this prices:

EPC1PC8 or EPC2LC20    for EP1K50,(ACEX)
EPC2LC20               for EP1K100.(APEX)

EPC2LC20.Altera
-price 21,59 eu.
- This one is JTAG programable.

EPC1PC8.Altera.
-price 7,12 eu.

Are this good prices ? Add sending and taxes...its in euro, almost
like dollar.

Anyways, it's the first time i buy this things, i don't know if they
are being nice or being too smart...what do you think ?

Could I use another memory for my FPGA ? What tipe would you recommend
me ?

Thank you !

Article: 53396
Subject: Re: PCI parity question
From: Kevin Brace <kev0inbrac1eusen2et@ho3tmail.c4om>
Date: Wed, 12 Mar 2003 14:00:19 -0600
Links: << >>  << T >>  << A >>


CC Nguyen wrote:
> 
> Hi all,
> I am newbie to PCI, please help me to clarify this.
> 
> For my understand from PCI spec, the parity is calculated by counting
> "The number of '1's on AD[31:0], C/BE[3:0], and PAR equals an even
> number" then PAR =1, else PAR =0.
> 

        In 32-bit PCI, parity is calculated by XORing AD[31:0] and
C/BE#[3:0].
Nope, PAR is 0 if there are even number of bits that are 1.



> Here's my assumption, the PAR is a function of itself ( previous state
> of PAR, I assume the calculation takes 1 clock )
> 
> If the above assumption is correct, this is what I think it will
> happen:
> 
> 1)During a "write data phase", if AD[31:0] and C/BE[3:0] are constants
> then PAR will toggle every data cycle. Is that true?
> 

        No.
I will assume that "AD[31:0] and C/BE[3:0] are constants" means the
target is inserting wait states.
If so, PAR will remain the same for the duration of the cycle, since
once IRDY# is asserted, AD[31:0] must remain constant until TRDY#
assertion is detected (C/BE#[3:0] will remain constant even when IRDY#
is being deasserted.).
Of course, PAR is always delayed by one clock cycle . . .


> 2)During address phase, the PAR may be floating ( there's no previous
> PAR ) then how can we calculate the address parity?

        PAR of AD[31:0] and C/BE#[3:0] during the address phase will be
available one cycle after the address phase.
Your device should be able to calculate the parity of AD[31:0] and
C/BE#[3:0] easily by registering the these inputs, and then calculate
the parity from these registers.
During the next clock cycle when PAR becomes valid, compare PAR with the
parity of the registered inputs (registered AD[31:0] and C/BE#[3:0]) to
see if an address parity error has occurred.


Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)

Article: 53397
Subject: Re: PCI specification
From: Kevin Brace <kev0inbrac1eusen2et@ho3tmail.c4om>
Date: Wed, 12 Mar 2003 14:02:30 -0600
Links: << >>  << T >>  << A >>


praveen wrote:
> 
> Hello Mr. Kevin,
> I am very greatful for your feedback. I actually have to give a
> seminar about PCI specification to my BOSS, so those question. Sir i
> need your support in design my PCI target core. I am starting
> configuration code from tomorrow.I have one more doubt
> 
> A buffer is required in the target PCI which i am design. If
> prefetching is used how many byte should i prefetch ? Is it length of
> my buffer? Should i prefetch during burst read?
> 
> Thanking in advance
> waiting for your reply
> praveen


Praveen,

I personally won't want to prefetch anything (I find it somewhat
risky.), but the number the DWORDs (32-bit) you want to prefetch is
something the user will decide.


Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)

Article: 53398
Subject: Re: Cyclone power up problem
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Wed, 12 Mar 2003 20:24:43 GMT
Links: << >>  << T >>  << A >>
> >
> > Here it is: http://www.jopdesign.com/cyclone/powerup.jsp
> >
> > Comments are welcome
>
>  Interesting results.
> one comment : 0.75 ohms is relatively high, as a current sniffer, and
> will change the circuit behaviour.

That was just one laying around. And may aim was not to bo very accurate.
Just wanted to see the 'trend'.

> It would be interesting to see Vcc/Icc on the same graph

Will continue to work on this supply. Than I can show you more graphs.
>
> Working from the dipping-Vcc plot,  i = CdV/dT gives for
> Assume 5uF ( usually > label ), and 0.6V / 3uS gives
> appx 1A from the Cap, and appx 0 from the SMPS, as it has not yet woken
> up :)
That was also my first calculation: Before the regulator starts reloading
the cap it drops about 0.4V in 3 us.
>
>  You can also 'make' a 1+fractional diode out of a transistor and two
> resistors,
> as a Vbe multiplier, (and get some Ron slope control from the Hfe )
> so that should you find 2.3 Diode drops is ideal, it can be be simply
> arranged.

Can you explain this a little bit for me?

Martin




Article: 53399
Subject: Re: Cyclone power up problem
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Wed, 12 Mar 2003 20:32:32 GMT
Links: << >>  << T >>  << A >>
> "Martin Schoeberl" <martin.schoeberl@chello.at wrote:
> > Here it is: http://www.jopdesign.com/cyclone/powerup.jsp
>
> Very nice.
>
> One thing that's fairly clear is that the transient response
> of your LT3405 regulator is not brilliant - in the last-but-one
> oscillograph the regulator is hanging around for over 2us
> before it even begins to respond to the load transient.
> That's not bad for a 1MHz switcher, but not good enough.

I don't expect such a transient in normal operation of the FPGA. Should I?

> I wonder if your 2-diode-and-resistor arrangement could be
> replaced with some crude but fast linear regulator, arranged
> to source about 0.1V less than the switcher, so that it's
> doing no work at all in the "normal" case but holds up the
> supply to about 1.3-1.4V during startup?  Its efficiency
> would not be a concern, since it would be "off" during
> normal operation.  And its output transistor could be
> quite small (as long as it has a low UceSAT) because it's
> dissipating power for only a few milliseconds.

Good idea. Do you mean something like LM317 (or one of its successor like
xx1117)? I don't know if these linear regulators have problems with the
reverse voltage. And it's a little bit more space and price (but not so
much).


Martin





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search