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You have choices. The complex number is expressed as two real numbers,
one of which has an implied multiplier of j. You can store the pair in
upper and lower half of a location, in separate memories, or in adjacent
words. In the case the the FFT, the coefficients are sines and cosines,
so you can use a single dual port memory and access it simultaneously from
both ports at the proper addresses to get the sine and cosine of the
current twiddle angle.
Hari wrote:
> Hi,
> How can store complex numbers into ROM.I am using Core generator to
> design my ROM.Also ,the values are to be loaded into ROM after
> calculation.I am need it for FFT transform, and the ROM stores the
> coefficients.Thanx.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 53501
If you go the route Peter is suggesting, you can get finer granularity by using
the carry chain as the delay element. Just watch the routing delays leading to it
to make sure they are all matched. In order for any scheme like this to be
reliable, you need some feedback mechanism to adjust the delays to match the
operating environment. Should you do something like this, your best bet would be
to generate a new skewed clock. This is not a trivial design however.
Peter Alfke wrote:
> Igor,
> SpartanIIE is like Virtex-E, so it just has a DLL, no phase adjustment.
> When you concatenate delays, you must assume >2-to-1 error over temp,
> voltage and processing. So you only chance is to servo-control this in
> some way. To measure the artificial delay and adjust it to be a certain
> portion of something stable, like a clock period.
> That's effectively ( among other tricks ) what we do in the DCM in Virtex-II.
> So, put your creative hat on and think about how to build something
> accurate out of non-precise ingredients ( but with good short-time
> stability ).
>
> Peter Alfke
>
> Igor Orlovich wrote:
> >
> > I guess this is one case where I have no choice- I have no say in what
> > another system does and the interface has been rigid for years, so I am
> > stuck with trying to match the specs
> >
> > Noddy wrote:
> >
> > > From my meagre knowledge of FPGA designs, adding delays to any signals is
> > > bad, bad, bad (a case could probably be argued for use in asynchronous
> > > systems, but I'm not the one to argue it)... what you need is more
> > > handshaking between the two systems. What about doubling your clock speed,
> > > or double edge triggering?
> > >
> > > adrian
> > >
> > >
> > >
> > > Igor Orlovich <igoro@hotmail.com> wrote in message
> > > news:sJRba.8853$Gk2.5234@twister.nyroc.rr.com...
> > >> I have a project which need sto interface to a system with fairly rigid
> > >> timing specs. As a result I need to delay my signals coming that way a
> > >> certain number of nS whiich is not a multiple of any clock I have in the
> > >> chip. Is there any way I can add some propagation delay/gate delay and
> > >> not have it optimized out by the XST tools. Or alternatively, is there a
> > >> way
> > > to
> > >> specify not only the max delay between signals, but also the min one?
> > >> Thanks for any suggestions
> > >>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 53502
You also have the option of using the 90,180 or 270 degree clocks out of the
DLL, which may be easier on your timing (these provide edges at all the places
you would have edges with a 2x clock. The 90 and 270 go away for the high speed
DLL and the DLL has a minimum input frequency, so you need to check the data
sheet carefully to make sure it will all work in your application.
I
Igor Orlovich wrote:
> Ray, that's it- that's the answer I was looking for!
> I can simply take my slow clock, run it through DLL, and use 2X or 4X of it
> to register my signals, effectively delaying them by that time. Or I can
> take 2X clock and use both edges to clock the signals out.. And since this
> derived clock will be synchronous to the first clock, my delays will be
> consistent. Thanks for the idea!
> Igor
>
> Ray Andraka wrote:
>
> > You could use the clock DLLs to get a 4x clock in the 2E. Since you are
> > dealing with apparently vintage hardware, that should give you enough
> > flexibility to get
> > around the hold time requirement. The spartan2E only has a DLL, not a DCM
> > so
> > you don't have the same amount of flexibility. You could also use a
> > purpose made delay line or clock skew buffer (such as a Cypress roboclock)
> > outside of the chip in extreme cases to generate a skewed clock if you
> > can't work out a
> > synchronous solution within the FPGA. Don't be tempted into using gates
> > for delay, the min and max times are spread far enough apart that about
> > all you can
> > guarantee is that it will not be reliable when you go to production. This
> > is true regardless if you've taken the extra step to hand route them to
> > guarantee the routing delays are equal (I don't advocate that either
> > except where absolutely necessary...lets just say out of well over 100
> > high performance FPGA designs, I can count on one hand the times I've
> > needed to do any hand routing)
> >
> > Igor Orlovich wrote:
> >
> >> Is there anything similar in Spartan IIE?
> >> This is again that same much discussed in this ng problem of another
> >> system requiring the data to show up so many nanoseconds after the clock
> >> edge. I did try creating a delay block by sticking a bunch of inverters
> >> with keep attributes set, but I can't seem to get the same delay among
> >> different
> >> instances. I presume creating a netslist macro is a solution, but am not
> >> sure how that is done.
> >>
> >> Peter Alfke wrote:
> >>
> >> > In Virtex-II you can specify a clock delay of n/256 of the clock period
> >> > ( limited to a granularity of ~50 picoseconds ). That solves your
> >> > problem. For most other delays the ratio between max and min is >2,
> >> > which makes any compensation attempts pretty useless.
> >> >
> >> > Peter Alfke, Xilinx Applications
> >> > =====================
> >> > Igor Orlovich wrote:
> >> >>
> >> >> I have a project which need sto interface to a system with fairly
> >> >> rigid timing specs. As a result I need to delay my signals coming that
> >> >> way a certain number of nS whiich is not a multiple of any clock I
> >> >> have in the chip. Is there any way I can add some propagation
> >> >> delay/gate delay and not have it optimized out by the XST tools. Or
> >> >> alternatively, is there a way to specify not only the max delay
> >> >> between signals, but also the min one? Thanks for any suggestions
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 53503In article <60e37826.0303131024.77a1fe15@posting.google.com>, santa19992000@yahoo.com says... > Guys, > > what is FPGA?. Also what is the difference between FPGA, CPLD and > ASIC?. Especially the functionality diff between ASIC and FPGA?. > Thanks in advance. > Field Programmable Gate Array Configurable (??) Programmable Logic Device These types of devices are "programmable" or "configurable". These days it may be more marketing then technical but FPGA's are layed out in arrays and developed the name. You stumped me on ASIC I know that is a silicon chip that has been designed for a specific function. It is not "programmable" or "configurable". Before FPGA's were cheap and small enough the only option for an inexpensive design was for an ASIC to be designed. -- Dan Henne DAN.nospam@HVWTECH.COM HVW Technologies Inc. www.HVWTech.comArticle: 53504
Hey y'all. Sorry me again, looking for footprints. I feel I kind of have to justify myself: don't get me wrong, I love dsesigning my own footprints. But I have to have the next rev of our main product out for Tuesday, so I'm trying to cut corners wherever I can. Thanks to Mark Chun for supplying me with the VirtexII/VirtexIIP FG256 footprint!! Now would anyone happene to have any of the following BGA footprints: Actel APA075, FG144I package AMD AM29LV640ML101RPCI, FBGA64 / LAA 064 package Samsung K4M56323LD, 90FPGA package Thanks guys!! Mike Hubert Xiphos Technologies Inc.Article: 53505
Louis, there is nothing wrong with your approach if you: 1. distribute the slow 20 MHz clock on global lines (skew and hold-time issues are equally important at 20 MHz as they are at 160 MHz. They can even bite you at 10 kHz) 2. Watch the data transfer between the two clock domains very carefully. Since your 20 MHz is the derived clock, assume that its edge is significantly later than the 160 MHz edge that created it. That can lead to unreliable race conditions when you transfer from the fast to the slow domain. Using the opposite 160 MHz edge would be nice, but then you have to watch the prop delay... Peter Alfke ----------------------------- louis wrote: > > "Peter Alfke" <peter@xilinx.com> news:3E6CF17F.D49C95E1@xilinx.com... > > > > The classical well-behaved method is to use only one (global) clock, and > > use a derived clock enable signal to make sure that the other part only > > operates on every fourth clock cycle. > > The price is slightly higher clock power consumption (provided you could > > lay out the circuit such that you don't run the fast clock all over the place). > > > > If you use a derived clock, then you end up with two slightly staggered > > time domains, which can bite you whenever there is data exchange between > > the two domains. ( The obvious loss of performance due to a late-clokced > > register driving data into an early-clocked one. The more devious case > > is the early-clocked register driving data into the late-clocked > > register, violating hold time requirements, and creating a > > race-condition mess.) > > > > Single clock synchronous is best in 99% of the cases... > > > > Peter Alfke, Xilinx Applications > > I would like to adopt single clock for the whole design. However, > it's hard to leverage the whole Spartan IIE to run at the high speed, > for example, 160M. I thought it'd be difficult to meet the timing constraint > for the entire chip with the clock-enable mechanism. > So I designed my high speed interface module at 160M, and the others > at 20M (1/8). The 20M was derived by counter. > Do you have any other suggestion?Article: 53506
Has anyone tried LogicLock'ing an Altera SOPC Builder slave or master, so that it's LogicLock properties are maintained when it placed via the Builder (obviously it would have to be a floating lock, as more than one slave/master might be placed)? Is it possible? -- PeteArticle: 53509
Hi - If you can get your footprints for free, that's great. But if you anticipate needing more footprints in the future and have some bucks to spend, you may want to consider SMT Plus (www.smtplus.com). Bob Perlman Cambrian Design Works On Fri, 14 Mar 2003 16:49:19 GMT, Mike Hubert <mph@xiphos.ca> wrote: >Hey y'all. > >Sorry me again, looking for footprints. I feel I kind of have to justify >myself: don't get me wrong, I love dsesigning my own footprints. But I have >to have the next rev of our main product out for Tuesday, so I'm trying to >cut corners wherever I can. > >Thanks to Mark Chun for supplying me with the VirtexII/VirtexIIP FG256 >footprint!! > >Now would anyone happene to have any of the following BGA footprints: > >Actel APA075, FG144I package >AMD AM29LV640ML101RPCI, FBGA64 / LAA 064 package >Samsung K4M56323LD, 90FPGA package > > >Thanks guys!! > >Mike Hubert >Xiphos Technologies Inc.Article: 53510
Josh Pfrimmer wrote: > Just your standard DFF, with asynchronous clear, right? Maybe. Let's see the entity and the rest of the architecture. > every time I do this, synthesize and simulate, I get the same result: Consider the reverse order: simulate then synthesize. -- Mike TreselerArticle: 53511
FPGAs - are either SRAM or Antifuse technology based. Xilinx, Altera main contenders for SRAM, Actel and Quicklogic for Antifuse. SRAM based FPGAs have many advantages and are popular over antifuse, proven by the revenues of Xilinx and Altera relative to Actel and Quicklogic. CPLDs - 'Complex Programmable Logic Devices' were earlier called EPLDs too. Nowadays are all flash based. Major players, Xilinx, Altera and Lattice. Both FPGAs and CPLDs are re-programmable. SRAM based FPGA needs power-up configuration through external memory. CPLDs, being flash based, do not need it. Antifuse FPGAs are all one time programmable. CPLDs are low cost and high performance devices more suitable for extensive combinatorial logic integration, glue logic implementation etc. Some of today's CPLDs (like the CoolRunner-II of Xilinx) support multiple I/O standards at extremely low power, opening up some additional applications to use them in. Density is measured in number of MacroCells, where typically one Macrocell equals a Flip-Flop and combinatorial circuit. FPGAs are typically used for register intensive designs. The basic logic is implemented using Look-Up-Tables (LUTs) and registers. Density measurement of FPGAs is in terms of number of LUTs and registers available. Nowadays lot of additional hardware resources are available within the FPGA - dedicated multipliers, carry-logic, clock-management circuitry, global clock buffers, and even Processors and Multi-Gigabit Transceivers. Multiple I/O standards (20+ different types) are supported. All these have had the FPGA evolve from basic digital logic implementation devices to complete system design and integration using FPGA as the platform. ASICs, FPGAs, CPLDs all perform the same function, i.e. user's application. The difference lies in the fact that FPGAs and CPLDs are 're-programmable' , whereas ASICs are made-to-order for a specific application. FPGAs and CPLDs are ICs bought off-the-shelf and 'programmed' for a particular application. ASICs have a longer development cycle, are expensive to build, and are mostly built for extremely high-volume cost sensitive applications. With the changing market conditions, ASICs are becoming less attractive for many applications, though still ASIC market is much bigger than the Programmable Logic market, and it will need quite some time for programmable logic to catch up with ASIC world revenues. "Dan" <dan@nospam.hvwtech.com> wrote in message news:MPG.18dbaf6c7aa5b0a98969b@news.telusplanet.net... > In article <60e37826.0303131024.77a1fe15@posting.google.com>, > santa19992000@yahoo.com says... > > Guys, > > > > what is FPGA?. Also what is the difference between FPGA, CPLD and > > ASIC?. Especially the functionality diff between ASIC and FPGA?. > > Thanks in advance. > > > Field Programmable Gate Array > Configurable (??) Programmable Logic Device > > These types of devices are "programmable" or "configurable". These days > it may be more marketing then technical but FPGA's are layed out in > arrays and developed the name. > > You stumped me on ASIC I know that is a silicon chip that has been > designed for a specific function. It is not "programmable" or > "configurable". Before FPGA's were cheap and small enough the only > option for an inexpensive design was for an ASIC to be designed. > > > > > > -- > Dan Henne > DAN.nospam@HVWTECH.COM > HVW Technologies Inc. > www.HVWTech.comArticle: 53512
I would like to thank all for their good ideas and help. I've tested some of the suggested ideas and wrote a little summary with some osci plots. You can find them at: http://www.jopdesign.com/cyclone/powerup.jsp Regards, Martin SchoeberlArticle: 53513
"Jim Wu" <jimwu88NOOOSPAM@yahoo.com> wrote in message news:<NA1aa.29610$8f7.6246@nwrdny02.gnilink.net>... > If you want to program FPGAs via JTAG, you would need download cable and > software from FPGA vendors. > > If you want to do PCB interconnection test via JTAG, you would probably have > to get test SW and HW from JTAG test equipment vendors. > > Jim Wu > jimwu88NOOOOOSPAM@yahoo.com (remove capital letters) > > "Prakash" <isro@ureach.com> wrote in message > news:790976aa.0303062246.4092c707@posting.google.com... > > Hi > > Anybody is using JTAG/BIST in > > boards.I'm new to this and want to > > know how to use it.Any material/example > > other than Mic.Smith(ASIC). This not true. You may have vendor independent options. Intellitech has a unique solution for configuring programmable logic devices. It is called SystemBIST embedded test and configuration processor. The SystemBIST processor enables in-the-field self-testable and reconfigurable products. It will replace the existing method of configuring your FPGAs and give you an easy way to upgrade the boards in the field. The embedded self-test capabilities of SystemBIST are gained for free, giving you and your customers the ability to apply all boundary-scan tests throughout the product's life cycle. You may find more information on our Web site here: (http://www.intellitech.com). Regards Turgut Abacioglu, Regional Manager Intellitech Canada 555 Legget Drive PH:613-271-2344 Tower A, Suite 304 FX:613-271-2340 Ottawa, ON K2K 2X3 turgut@intellitech.com http://www.intellitech.com/Article: 53514
ldoolitt@recycle.lbl.gov (Larry Doolittle) wrote in message news:<slrnb6hgj5.hlt.ldoolitt@recycle.lbl.gov>... > On Fri, 07 Mar 2003 13:59:09 GMT, Jim Wu <jimwu88NOOOSPAM@yahoo.com> wrote: > >If you want to program FPGAs via JTAG, you would need download cable and > >software from FPGA vendors. > > False. There are plenty of vendor-free ways to program FPGAs by JTAG. > People who are in the habit of using decent paid-for, supported, time-saving, > flexible and relevant commercial software/hardware are, of course, free > to continue doing so. Everyone also needs to understand that this approach > is not the only path, and in many cases it doesn't exist. Actual knowledge > of how to solve the problem is sometimes essesntial, and such knowledge is > not the exclusive province of large companies. > > - Larry Yes, Intellitech has a unique solution for configuring programmable logic devices. It is called SystemBIST embedded test and configuration processor. The SystemBIST processor enables in-the-field self-testable and reconfigurable products. It will replace the existing method of configuring your FPGAs and give you an easy way to upgrade the boards in the field. The embedded self-test capabilities of SystemBIST are gained for free, giving you and your customers the ability to apply all boundary-scan tests throughout the product's life cycle. You may find more information on our Web site here: (http://www.intellitech.com). Turgut Abacioglu, Regional Manager Intellitech Canada 555 Legget Drive PH:613-271-2344 Tower A, Suite 304 FX:613-271-2340 Ottawa, ON K2K 2X3 turgut@intellitech.com http://www.intellitech.com/Article: 53515
Dan wrote:
>
> You stumped me on ASIC I know that is a silicon chip that has been
> designed for a specific function. It is not "programmable" or
> "configurable". Before FPGA's were cheap and small enough the only
> option for an inexpensive design was for an ASIC to be designed.
Application Specific Integrated Circuit. Not truly custom (we didn't
get down to the transistor level, just gate level). 15+ years ago I led
a team which designed an ~27,000 gate ASIC (the largest that company had
attempted at the time)along with several card designs. We used Personal
Daisys for schematic entry and saw a lot of the "steaming coffee
cup"--Daisy's equivalent of the hourglass/watch face.
Simulation was also a real bottleneck. We had a special PC outfitted
with a large hard-drive and a hardware accelerator just to simulate a
_small_ portion of the data on some of the functional blocks. We also
did simulation at the vendor's (LSI Logic) Dallas office. The data that
in real time took ~0.167 sec to process required about 20 minutes of
simulation at their office, and even there we wound up having to split
the ASIC into two halves--we couldn't simulate it as one functional unit.
Despite the obstacles, the BEGAL (Bandwidth Expander Gate-Array Logic)
was completed in 9 months with 100% functional first silicon (we
actually used the engineering samples on our production cards). That
was a _good_ team.
-=Dave=-
Article: 53516
After some recent reports of success on this newsgroup, I decided
to try the WebPACK/WINE combination again. I can make the GUI work,
and the Verilog syntheis and translate steps work, but the process
crashes at the map step:
Release 5.1i - Map F.23
Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Using target part "2s150pq208-5".
FATAL_ERROR:Map:Portability/export/Port_Main.h:126:1.22 - This application has
discovered an exceptional condition ...
I'll set up a WebCase for this issue as soon as my account is permitted
to do so. I would be thrilled if anyone in or out of Xilinx can help
me though this problem. My system is:
Red Hat 7.3 with all the updates applied
Wine-20030219
ISE WebPACK 5.2i (WebPACK_51_fcfull_i.exe)
ISE service pack 3 (5_1_03i_pc.exe)
I configured Wine to emulate win2k, and copied the Xilinx-supplied
DLLs from config/redist/w2k to a place where Wine could find them.
For MSVCRT.DLL, that also means overriding the Wine builtin dll.
Uwe Bonnes has been very helpful getting me this far.
- Larry
Article: 53518Ray Andraka <ray@andraka.com> wrote in message news:<3E71389F.11D6C693@andraka.com>... > 1) Depends on whta metric you use. If average latency is what is > important, then use the average. If peak latency is important, you use > that. Be aware that average latency may be data dependent, so make sure > your data set is representative. In this case, you'll probably need both > numbers: average to determine the average performance of the system and > max to make sure the system can handle a worst case scenario. It may take > a sizeable effort to determine what a realistic worst case is in the > context of your system. I guess that I will require to do create a test harness code to determine by backannotation, the data dependent performances. > > 2) This is usually accomplished with matching delays if the amount of data > in both paths is similar. If it is just one or two samples that need to > be passed around a process thta is producing many samples, then you hold > it in a register (but that is not the usual case). The clock frequency > should match the clock frequency of your process data path, and the > latency should match the data path latency. Normally in hardware DSP the > latency is deterministic, and it is easiest if you try to balance the > latency through all sub paths so that the outputs come at a fixed time. > If they are variable or non-deterministic, you should consider putting a > FIFO in the bypass path. > If I not misunderstood: Main block has two (2) input paths, #1 the 'process path' which contains a t1 delay processing, and #2 the 'data path' which has minimum t2 delay. Then I have to balance those 'data-path' sub paths considering their latencies (assuming register chained, or FIFO rate matching); and on the 'process path', (assuming register boundaries delimited) its delay will determine the MAIN clock frequency. Then, Which kind of FIFO configuration will be the more appropriate: the I/O only, with limit flags, and/or pointer based? And How do I determine its depth? Finally, Which is the best way to code it in VHDL: using LUTs/RAMs (technology specific) or by a more general mean (based of F/Fs)? > JDS wrote: > > > Hi everybody, > > > > I may have two (2) dummy questions, but I'd like to see how far are my > > thoughts on that. > > > > 1. How do I can measure the performance of DSP block if its processing > > time varies depending of the data itselft? By instantiation of a known > > time response circuit in parallel, i.e., a counter with a strobe > > signal and stop signal coming from the DSP block after it finishes the > > crunching. Can it be used? > > > > 2. Another case: Having two (2) input path to a main logic block; one > > of them is having a secundary combinational logic; and the secundary > > path (or input) does not have any logic at all. How do I synchronize > > the inputs of the main block? Without clock-gating, maybe with many > > pipeline registers on the empty path. Then, how do I determine the > > right number of registers and their clock frecuency. What is the right > > approach? > > > > Again, many thanks friends, and Ray thanks to take from your valuable > > time to allure our lay questions. > > > > JDS > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 53519
ok.. whole file, then:
-----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity flop is port (
clk : in std_logic;
rst : in std_logic;
din : in std_logic;
dout : out std_logic);
end flop;
architecture flop_arch of flop is
begin
process (clk, rst) is
begin
if rst = '1' then
d_out <= '0';
elsif rising_edge(clk) then
d_out <= din;
end if;
end process;
end architecture;
---------------------------------------------
I add this file to a brand new (no other sources) project, analyze source,
and click the simulate button. This is the simplest reduction of the
problem... it first arose when I noticed that one of my students program
counter (an 8-bit register, with input from a multiplexor) was not
responding to the reset signal. I've been through several variations on
his, and other machines in the lab... and gotten this result.
Occasionally, I get an OFD instead of the IFD.
When I tried to put simple logic between the input and output ports (din
was anded with din2, output was dout anded with dout2) , I actually got it
to instantiate an FDCE, but the CLR pin on the FDCE was unconnected, so it
STILL didn't respond to reset.
What kills me is that it looks exactly like the code I've ALWAYS used to
make registers with asynchronous reset. I'm assuming there's some option
in foundation 4.1i that's responsible, but I can't find it.
Thanks... JP
"Mike Treseler" <tres@fluke.com> wrote in message
news:3E721994.4020500@fluke.com...
> Josh Pfrimmer wrote:
>
> > Just your standard DFF, with asynchronous clear, right?
>
>
> Maybe. Let's see the entity and the rest of the architecture.
>
>
> > every time I do this, synthesize and simulate, I get the same result:
>
>
>
>
> Consider the reverse order: simulate then synthesize.
>
> -- Mike Treseler
>
Article: 53520Larry, Windows 2000 dll's on WINE were not compatible with 5.1i. You can find the information on this in the "Configuring WINE for Xilinx" section of the 5.1i Release and Installation Guide. Both your Red Hat and Wine versions are newer than those supported for the 5.1i release, but I have not heard of any major issues with them, so I doubt they are the problem. I agree you are very close, and if needed, our support engineers will be able to help you sort out your dll issues. Roy White Larry Doolittle wrote: > After some recent reports of success on this newsgroup, I decided > to try the WebPACK/WINE combination again. I can make the GUI work, > and the Verilog syntheis and translate steps work, but the process > crashes at the map step: > > Release 5.1i - Map F.23 > Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. > Using target part "2s150pq208-5". > FATAL_ERROR:Map:Portability/export/Port_Main.h:126:1.22 - This application has > discovered an exceptional condition ... > > I'll set up a WebCase for this issue as soon as my account is permitted > to do so. I would be thrilled if anyone in or out of Xilinx can help > me though this problem. My system is: > Red Hat 7.3 with all the updates applied > Wine-20030219 > ISE WebPACK 5.2i (WebPACK_51_fcfull_i.exe) > ISE service pack 3 (5_1_03i_pc.exe) > I configured Wine to emulate win2k, and copied the Xilinx-supplied > DLLs from config/redist/w2k to a place where Wine could find them. > For MSVCRT.DLL, that also means overriding the Wine builtin dll. > > Uwe Bonnes has been very helpful getting me this far. > > - LarryArticle: 53521
Josh Pfrimmer wrote:
> ok.. whole file, then:
>
> -----------------------------------------------------
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_unsigned.all;
>
> entity flop is port (
> clk : in std_logic;
> rst : in std_logic;
> din : in std_logic;
> dout : out std_logic);
> end flop;
>
> architecture flop_arch of flop is
> begin
> process (clk, rst) is
> begin
> if rst = '1' then
> d_out <= '0';
> elsif rising_edge(clk) then
> d_out <= din;
> end if;
> end process;
> end architecture;
> ---------------------------------------------
Is that dout or d_out?
Consider doing at least a "vcom flop.vhd" before synthesizing.
-- Mike Treseler
Article: 53522I bought Altera, i did it from arrow, and that is overseas... khimbittle@cliftonREMOVEsystems.com (KB) wrote in message news:<3e70c758.11529204@news.compuserve.com>... > hello folks ... being more of a xlinix user of recent years and not > purchasing altera we are considering using altera for some new designs > ... but I see the altera website lists only arrow under US > distribution ... so does this mean EVERYONE buys ALL of their altera > parts from arrow ? or am I missing something ... it seems the single > distributor model would be a reason NOT to move to altera since I am > sure the only reason we ( small company ) get good pricing on xilinx > is because there are three big local distributors in town ( plus > internet distributors ) who all carry xilinx ... and I think we get > good pricing because of this .. mmmm any thoughts, thanks KBArticle: 53523
Larry Doolittle wrote: > ... My system is: > Red Hat 7.3 with all the updates applied > Wine-20030219 > ISE WebPACK 5.2i (WebPACK_51_fcfull_i.exe) > ISE service pack 3 (5_1_03i_pc.exe) Hmm, that service pack filename is exactly the same as the one for ISE5.1. I wonder if it is really the same file? By the way, you might mention where you got the Wine version being used. For what it is worth, I run ISE5.1sp3 on Redhat 7.3, with current CVS Wine. > I configured Wine to emulate win2k, and copied the Xilinx-supplied > DLLs from config/redist/w2k to a place where Wine could find them. > For MSVCRT.DLL, that also means overriding the Wine builtin dll. > I am a little puzzled by that. At least when installing ISE, it automatically installs the DLLs. I assume Webpack does the same. Where did "config/redist/w2k" come from? In any case, did you try the NT40 DLLs instead of the Win2K ones? If I were doing it, I would blow away all the native DLLs and the Webpack directory, reconfigure Wine for nt40 rather then win2k, and reinstall the Xilinx software. Xilinx seems to have fixed whatever used to cause the software to take an hour or so to install :-) Afterwards, maybe check to see that it installed a few native DLLs, including msvcrt. -- My real email is akamail.com@dclark (or something like that).Article: 53524
On Fri, 14 Mar 2003 16:16:58 -0700, Roy White <whiter@xilinx.com> wrote:
>
>Windows 2000 dll's on WINE were not compatible with 5.1i. You can find the
>information on this in the "Configuring WINE for Xilinx" section of the 5.1i
>Release and Installation Guide.
Doh! I had read this once, but ingored it this week.
>Both your Red Hat and Wine versions are newer
>than those supported for the 5.1i release, but I have not heard of any major
>issues with them, so I doubt they are the problem.
Assuming I use Windows NT configuration, how will I know when
I find the right samlib.dll, netapi32.dll, and netrap.dll?
Wine includes a builtin netapi32.dll, is that OK? Shall I
try www.dll-files.com for the other two? Why didn't Xilinx
include these files in the kit? Do the Xilinx-supplied w2k
DLLs in config/redist/w2k work with Wine in NT emulation mode?
>I agree you are very close, and if needed, our support engineers will be
>able to help you sort out your dll issues.
I hope so, just as soon as I am cleared to open a WebCase.
- Larry
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