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I am trying to learn CUPL. I think I've downloaded everything from the Atmel website, and googled for more, and I'm still fairly mystified by the examples. What I think is missing (other than half my brain) is a "language reference" for CUPL. If there is such a thing, I would appreciate a pointer. TIA, George -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 100,000 Newsgroups - 19 Different Servers! =-----Article: 61726
John,
I did something similar to this in a Spartan II. I was searching
through a 2^7-1 PRBS pattern (at the output of a SERDES, data bus is
10-bits wide) for the longest string of zeros. Granted the longest
string of zeros in a 2^7-1 PRBS pattern is 6, the idea could be
extrapolated to longer strings like 9 in a 65-bit wide bus.
Here's an example of what I did for searching for 6 zeros in a row.
You'll notice that in my casez statement, I'm actually searching for 6
ones in a row. This is because the BERT that I was using inverted
it's output PRBS pattern.
always @(posedge clock1)
begin
casez (datasi[9:0])
10'b???111111? : Q[9:0] = {datasi[9:8],7'b1111111,datasi[0]};
default : Q[9:0] = datasi[9:0];
endcase
end
Once you find the string that you're looking for, you can do what ever
you'd like.
Hope this helps,
Jeremy
johnhandwork@mail.com (John_H) wrote in message news:<6c803f5f.0310060552.267dc963@posting.google.com>...
> "Morten Leikvoll" <m-leik@online.nospam> wrote in message news:<5z9gb.28389$os2.397003@news2.e.nsc.no>...
> > I just started reading this thread.. Am I correct if you really want to
> > detect 9 EQUAL bits in a row from a stream?
> > Could you not do this just with a 4bits counter and a comparator/zero
> > detector?
>
> Correct, I need "equal" bits, either 9'h000 or 9'h1ff, starting from
> 0, 8, 16, ... 56.
>
> The input is 65 bits per clock with a fast clock, output from BlockRAM
> which was loaded at full width.
>
> Counters require more than one clock.
Article: 61727"Christos" <chris_saturnNOSPAM@hotmail.com> wrote in message news:<bm3agi$gr9$1@sunnews.cern.ch>... > Hi all, > > In the vector waveform file that I am creating to enter the inputs for my > simulation I can also enter the outputs and the registers that I would like > to be recorded. > There using the node finder I can enter some combinatorial signals that I > would like to observe. > But after the simulation those signals have been omitted and the warning has > been given : > "Warning: Ignored node in vector source file. Can't find corresponding node > name CFCstatus in design." > > So, can someone please explain me how I can check those internal signals? > For example the output of a lpm_compare block which feeds an input of a > counter without inserting in the middle a output pin? (you don't have to use > this example of course). > > I thing it doesn't make any difference the version but I am using Quartus II > 3.0. > > Thanks, > Christos Hi Christos, To preserve a combinatorial node through synthesis, place and route, you should do one of the following: a) If it is a BDF (schematic file) or TDF (AHDL file), feed the signal that you are interested in observing into a LCELL primitive, and give the LCELL primitive an interesting name, so that you can find it when you choose the Post Compilation filter in the node finder. You should feed the output of the LCELL to where the signal wof interes was previously connected. b) If you are using VHDL or Verilog, consider using the keep pragma/keyword. Its usage is described in the online help. Search for "keep". The Verilog help panel is shown below: ------------------- keep usage in Verilog ----------------------------------- A Verilog HDL language directive that directs Analysis & Synthesis to keep a particular wire intact. You can use this language directive to keep a combinational logic node so you can observe the node during simulation or with the SignalTap® II Logic Analyzer. You cannot use this language directive for nodes that have no fan-out. To use the keep language directive, you can specify the keep language directive in a comment that is on the same line as the register you want Analysis & Synthesis to preserve. In the comment, precede the language directive with the synthesis keyword. For example, in the following code, the comment /* synthesis preserve */ directs Analysis & Synthesis to not minimize the keep_wire register: wire keep_wire /* synthesis keep */; ------------------------------------------------------------------------------- You would search for keep_wire in the Mode Finder. Hope this helps. - Subroto Datta Altera Corp.Article: 61728
Martin Euredjian wrote: > > The following code: > > module PROBLEM > ( > input wire CLK, > input wire [9:0] A, > input wire [9:0] B, > output reg [9:0] OUT > ); > wire [9:0] xor2; > XOR2 XOR2_0 (.O(xor2[0]), .I0(A[0]), .I1(B[0])); > XOR2 XOR2_1 (.O(xor2[1]), .I0(A[1]), .I1(B[1])); > XOR2 XOR2_2 (.O(xor2[2]), .I0(A[2]), .I1(B[2])); > XOR2 XOR2_3 (.O(xor2[3]), .I0(A[3]), .I1(B[3])); > XOR2 XOR2_4 (.O(xor2[4]), .I0(A[4]), .I1(B[4])); > XOR2 XOR2_5 (.O(xor2[5]), .I0(A[5]), .I1(B[5])); > XOR2 XOR2_6 (.O(xor2[6]), .I0(A[6]), .I1(B[6])); > XOR2 XOR2_7 (.O(xor2[7]), .I0(A[7]), .I1(B[7])); > XOR2 XOR2_8 (.O(xor2[8]), .I0(A[8]), .I1(B[8])); > XOR2 XOR2_9 (.O(xor2[9]), .I0(A[9]), .I1(B[9])); > > always @(posedge CLK) OUT <= xor2; > > endmodule > > ... produces interesting results. The tools run without a hitch, no error, > and no reports of logic being optimized out. However, if you look at the > end-product in the Floorplanner the LUTs that are supposed to be there are > nowhere to be found. Then, it gets interesting, go over to FPGA Editor and > every bit of logic is there as you would expect. What gives? > > This excercise started out as an attempt to build an RLOC'd parameterized > adder. Logic would not show-up in the Floorplanner so, eventually, I > reduced it to just an XOR clocking out to see what was wrong. > > Using ISE6.1i, SP1. Device is XC2V1000-FG456 > > ...this is turning out to be one hell of a frustrating week! You say the LUTs are not there. How about the registers? You might want to open a case for this with Xilinx. It can be an uphill battle trying to get them to understand what you are doing and why. But certainly the problem itself is not difficult to convey. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61729
I'm afraid I'm lost. The example you give shows a single alignment for a
6-ones check. There are 10 total alignments that can apply. Once detected,
there doesn't seem to be an indication THAT the detection occurred except
that one of the bits from the SERDES is now a one (by definition of your
pattern, it would have been a zero).
Were you suggesting that, in general, a casez might produce good results
from the synthesizer for run detection?
"Jeremy Webb" <jeremywebb@ieee.org> wrote in message
news:4d807c8a.0310091158.5a0ba215@posting.google.com...
> John,
>
> I did something similar to this in a Spartan II. I was searching
> through a 2^7-1 PRBS pattern (at the output of a SERDES, data bus is
> 10-bits wide) for the longest string of zeros. Granted the longest
> string of zeros in a 2^7-1 PRBS pattern is 6, the idea could be
> extrapolated to longer strings like 9 in a 65-bit wide bus.
>
> Here's an example of what I did for searching for 6 zeros in a row.
> You'll notice that in my casez statement, I'm actually searching for 6
> ones in a row. This is because the BERT that I was using inverted
> it's output PRBS pattern.
>
> always @(posedge clock1)
> begin
> casez (datasi[9:0])
> 10'b???111111? : Q[9:0] = {datasi[9:8],7'b1111111,datasi[0]};
> default : Q[9:0] = datasi[9:0];
> endcase
> end
>
> Once you find the string that you're looking for, you can do what ever
> you'd like.
>
> Hope this helps,
>
> Jeremy
>
> johnhandwork@mail.com (John_H) wrote in message
news:<6c803f5f.0310060552.267dc963@posting.google.com>...
> > "Morten Leikvoll" <m-leik@online.nospam> wrote in message
news:<5z9gb.28389$os2.397003@news2.e.nsc.no>...
> > > I just started reading this thread.. Am I correct if you really want
to
> > > detect 9 EQUAL bits in a row from a stream?
> > > Could you not do this just with a 4bits counter and a comparator/zero
> > > detector?
> >
> > Correct, I need "equal" bits, either 9'h000 or 9'h1ff, starting from
> > 0, 8, 16, ... 56.
> >
> > The input is 65 bits per clock with a fast clock, output from BlockRAM
> > which was loaded at full width.
> >
> > Counters require more than one clock.
Article: 61730"Barry Brown" <barry_brown@agilent.com> wrote in message news:1065716279.409531@cswreg.cos.agilent.com... > Cannot answer your question, but thought I would bring to your attention > Xilinx XAPP636, "Optimal Pipelining of I/O Ports of the Virtex-II > Multiplier", in case you have not seen it. Yes, I have, thanks. I show that I downloaded it back in December '02. Re-studied it a few days ago. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 61731
"rickman" wrote: > You say the LUTs are not there. How about the registers? Sorry, I should have mentioned that, yes, the registers are there. Floorplanner shows no input to the registers at all, just the output rubberbanding to the corresponding IOB. FPGA Editor shows all logic connected per the HDL description. The bummer here is that I'm trying to create some pretty complex RPM's and Floorplanner is a nice way to see how things are laying out. Unless someone tells me that I'm missing something in my sample code, I guess I'll have to use FPGA Editor. > You might want to open a case for this with Xilinx. It can be an uphill > battle trying to get them to understand what you are doing and why. But > certainly the problem itself is not difficult to convey. They've been pretty good to me in the past...but, then again, I've only put in a couple or so simple cases. I'll typically get myself to the point of absolute frustration before either posting on the newsgroup or seeking other help (like using the Force, which should not be done lightly). :-) -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 61732
I wonder if using FMAP might make a difference here? The trouble is... I couldn't figure out how to define a simple two-input XOR gate from both the Libraries Guide and Constraints Guide (MAP) entries. Can anyone point me to detailed documentation on the subject? Thanks, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:0rahb.13220$BQ7.7883@newssvr25.news.prodigy.com... > The following code: > > module PROBLEM > ( > input wire CLK, > input wire [9:0] A, > input wire [9:0] B, > output reg [9:0] OUT > ); > wire [9:0] xor2; > XOR2 XOR2_0 (.O(xor2[0]), .I0(A[0]), .I1(B[0])); > XOR2 XOR2_1 (.O(xor2[1]), .I0(A[1]), .I1(B[1])); > XOR2 XOR2_2 (.O(xor2[2]), .I0(A[2]), .I1(B[2])); > XOR2 XOR2_3 (.O(xor2[3]), .I0(A[3]), .I1(B[3])); > XOR2 XOR2_4 (.O(xor2[4]), .I0(A[4]), .I1(B[4])); > XOR2 XOR2_5 (.O(xor2[5]), .I0(A[5]), .I1(B[5])); > XOR2 XOR2_6 (.O(xor2[6]), .I0(A[6]), .I1(B[6])); > XOR2 XOR2_7 (.O(xor2[7]), .I0(A[7]), .I1(B[7])); > XOR2 XOR2_8 (.O(xor2[8]), .I0(A[8]), .I1(B[8])); > XOR2 XOR2_9 (.O(xor2[9]), .I0(A[9]), .I1(B[9])); > > always @(posedge CLK) OUT <= xor2; > > endmodule > > > ... produces interesting results. The tools run without a hitch, no error, > and no reports of logic being optimized out. However, if you look at the > end-product in the Floorplanner the LUTs that are supposed to be there are > nowhere to be found. Then, it gets interesting, go over to FPGA Editor and > every bit of logic is there as you would expect. What gives? > > This excercise started out as an attempt to build an RLOC'd parameterized > adder. Logic would not show-up in the Floorplanner so, eventually, I > reduced it to just an XOR clocking out to see what was wrong. > > Using ISE6.1i, SP1. Device is XC2V1000-FG456 > > ...this is turning out to be one hell of a frustrating week! > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > > > > > > >Article: 61733
FWIW, you need to put those registers in those spots around the multipliers in
order to achieve the data sheet max performance.
Martin Euredjian wrote:
> "Barry Brown" <barry_brown@agilent.com> wrote in message
> news:1065716279.409531@cswreg.cos.agilent.com...
> > Cannot answer your question, but thought I would bring to your attention
> > Xilinx XAPP636, "Optimal Pipelining of I/O Ports of the Virtex-II
> > Multiplier", in case you have not seen it.
>
> Yes, I have, thanks. I show that I downloaded it back in December '02.
> Re-studied it a few days ago.
>
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Martin Euredjian
>
> To send private email:
> 0_0_0_0_@pacbell.net
> where
> "0_0_0_0_" = "martineu"
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61734
Bzzzt. The 'pipeline' register in the multiplier is in the middle. the setup
and clock to Q of the 'pipelined' multiplier is substantial. In order to get
the data sheet max performance, you need to add CLB registers to the
multiplier I/O AND you need to place them in the slices where there are direct
connects to the multiplier. If you do this, and as long as you don't have
'stepping 0' parts, the embedded multipliers can be clocked faster than an 18
bit carry chain. The advantage of in the fabric multipliers is that you can
make them whatever size you need, and put them where they are convenient
rather than being restricted to the mult/bram columns. In the fabric, you can
also take advantage of cases where you have multiple clocks per sample to
reduce the size of the multiplier. I look at the FPGA sort of like a bin of
different Legos (tm). You use what you have in the box to the best advantage
for your particular project. Sometimes there are more multipliers than you
need, so you can use them for things like shifters or muxes if you get real
cute about it. Other times, there are not enough, so you pick and choose what
goes where.
Ken wrote:
> <snip>
>
> > 3: Use of the BlockRAMs. Since the BlockRAMs and multipliers share
> > interconnect, there are limits on when they can be used
> > simultaneously.
> >
> > 4: Pipelined, throughput-optimized performance. The fixed multipliers
> > are unpipelined or single-stage, a LUT multiplier can be much more
> > finely pipelined (higher thorughput).
>
> Ok - it is my understanding that there are registers just before and just
> after the dedicated multipliers that can be used to speed them up.
>
> But what you are saying is that the LUT multipliers will have a higher max
> MHz when both solutions are as pipelined as they can be?
>
> Thanks for your time,
>
> Ken
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61735
I haven;t seen this particular problem. There is a problem with the outputs of
srl16's not rubberbanding, but the logic is still there. DO you lose the logic
in the hierarchical display as well, or is it jsut missing out of the RPM when
you try to place it. How about in the placed (grey background) view after you
run PAR? Unfortunately, with floorplanner bugs, the best you'll usually get out
of Xilinx is an acknowledgement that there is a problem and a promise that it
will get addressed in the 'next major release'. Floorplanner still seems to be a
very low priority with respect to other parts of the Xilinx tool suite.
Martin Euredjian wrote:
> "rickman" wrote:
>
> > You say the LUTs are not there. How about the registers?
>
> Sorry, I should have mentioned that, yes, the registers are there.
> Floorplanner shows no input to the registers at all, just the output
> rubberbanding to the corresponding IOB. FPGA Editor shows all logic
> connected per the HDL description.
>
> The bummer here is that I'm trying to create some pretty complex RPM's and
> Floorplanner is a nice way to see how things are laying out. Unless someone
> tells me that I'm missing something in my sample code, I guess I'll have to
> use FPGA Editor.
>
> > You might want to open a case for this with Xilinx. It can be an uphill
> > battle trying to get them to understand what you are doing and why. But
> > certainly the problem itself is not difficult to convey.
>
> They've been pretty good to me in the past...but, then again, I've only put
> in a couple or so simple cases. I'll typically get myself to the point of
> absolute frustration before either posting on the newsgroup or seeking other
> help (like using the Force, which should not be done lightly). :-)
>
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Martin Euredjian
>
> To send private email:
> 0_0_0_0_@pacbell.net
> where
> "0_0_0_0_" = "martineu"
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61736
I would like to split a pci-x133 bus into 2 parallel pci-66 busses.
Has anyone done this? I'm not afraid to purchase the Xilinx pci-x
core and halfbridge IP but just looking for some wisdom.
|--------|
| |<----- pci-66 ----->
<---pcix133--->| bridge |
| |<----- pci-66 ----->
|--------|
chad.
Article: 61737Vazquez wrote: > Why does QuartusII not synthesize it as a RAM structure using > the memory bits of Cyclone? see pg. 50 http://www.altera.com/literature/an/an238.pdf -- Mike TreselerArticle: 61738
"Subroto Datta" <sdatta@altera.com> wrote in message news:<hKdhb.11831$PT5.10267@newssvr32.news.prodigy.com>... > Hi Christian, > > The Hardware information is stored separately from the cdf, as it is a > function of the programmer not the chain. However your suggestion to have > multiple HW profiles is a good one, and I will pass it on. > > - Subroto Datta > Altera Corp. > > "Christian Kramer" <RemoveThis_chr_kramer@web.de> wrote in message > news:bm33hk$3vj$1@news.uni-stuttgart.de... > > Hi! > > > > I am using three CPLDs in my design. Each one has its own JTAG > > connector, an I have three Byteblasters connected to LPT1-LPT3 on my PC. > > Is there any way to save the configuration, which hardware is to be used > > for programming in the .cdf-file for each design? > > > > When I reopen the .cdf-files the programming-hardware is always the last > > one used - even if it was used in an different project. > > > > Thanks, > > Christian > > > > Hi Christian, If using the command line (DOS prompt) is possible you can try using the command line quartus programmer as follows: quartus_pgm --cable=ByteBlasterMV[LPT1] lpt1.cdf quartus_pgm --cable=ByteBlasterMV[LPT2] lpt2.cdf quartus_pgm --cable=ByteBlasterMV[LPT3] lpt3.cdf Hope this helps. - Subroto Datta Altera Corp.Article: 61739
Hi Martin, The floorplanner only shows logic that can be floorplanned. The problem is the use of the XOR2 which is a primitive element in the Xilinx Library. This XOR2 element can not be constrained in the UCF file because it is not a LUT it is just logic. If the XOR2 gate was not instantiated then XST would generate a LUT which could be constrained and viewed in the floorplanner. After the map phase it is mapped to a LUT (thus why you see it in the fpga editor), but this is too late to add constraints to. If you add a new definition for the XOR2 to your design, I believe this will fix your problem. You may eventually want to change the name of the XOR2 module in order to avoid confusion with the library primitive. module XOR2 ( output O, input I0, input I1 )/* synthesis attribute lut_map of XOR2 is yes*/; assign O = I0 ^ I1; endmodule // XOR2 - Tom Branca - XilinxArticle: 61740
Hi, Logically, what you described can be built with three PCI-X to PCI-X bridges. You can take bridge #1 from PCI-X 133 to PCI-X 66. On that PCI-X 66 bus segment, you put bridge #2a and #2b, both of which bridge from PCI-X 66 to PCI 66. So, you can actually go buy three of these ASSPs and build exactly what you want. I wouldn't want to turn you away from a Xilinx solution. A Xilinx solution could be a one-chip solution, offer lower latency, and provide you with the opportunity to customize your design in a way you cannot with ASSPs. However, you would want to carefully weigh the benefits with the downsides -- you will need to put in some design effort. Another thing to consider is cost, which will be a function of the size of your final design. Good luck, Eric Chad Bearden wrote: > > I would like to split a pci-x133 bus into 2 parallel pci-66 busses. > Has anyone done this? I'm not afraid to purchase the Xilinx pci-x > core and halfbridge IP but just looking for some wisdom. > > |--------| > | |<----- pci-66 -----> > <---pcix133--->| bridge | > | |<----- pci-66 -----> > |--------| > chadArticle: 61741
The mapped luts will show up in the floorplanner, but not as part of an
RPM. If the LUTs get optimized by the mapper, for example if one of the
inputs is tied to a constant, the remapped LUT will be put in the
primitives bin at the top level of the hierarchy in the floorplanner
rather than with the hierarchical component where they originally were
unless they are part of an RPM. Run place and route and then open the
floorplanner, and look at the placed view. You should see all the logic
there. If you then select the luts that are 'dissappearing', then the
branch in the hierarchy view will have a box around it and you should be
able to push down to find that particular lut. I'm sure you will find it
in the primitives bin somewhere, most likely at the top level. If you
want it to be part of the RPM you need to either use instantiated luts or
FMAP components (which generally get optimized out by synthesis tools).
Some synthesis tools, such as synplify have attributes you can put on
components to force them into a LUT, and those components will accept an
RLOC. When I read your problem statement, I thought you were saying that
that logic was not showing up in the floorplanner at all.
Tom Branca wrote:
> Hi Martin,
> The floorplanner only shows logic that can be floorplanned. The
> problem is the use of the XOR2 which is a primitive element in the
> Xilinx Library. This XOR2 element can not be constrained in the UCF
> file because it is not a LUT it is just logic. If the XOR2 gate was
> not instantiated then XST would generate a LUT which could be
> constrained and viewed in the floorplanner. After the map phase it is
> mapped to a LUT (thus why you see it in the fpga editor), but this is
> too late to add constraints to.
>
> If you add a new definition for the XOR2 to your design, I believe
> this will fix your problem. You may eventually want to change the name
> of the XOR2 module in order to avoid confusion with the library
> primitive.
>
> module XOR2
> (
> output O,
> input I0,
> input I1
> )/* synthesis attribute lut_map of XOR2 is yes*/;
> assign O = I0 ^ I1;
> endmodule // XOR2
>
> - Tom Branca
> - Xilinx
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61742
What tool are you using?
Martin Euredjian wrote:
> I wonder if using FMAP might make a difference here? The trouble is... I
> couldn't figure out how to define a simple two-input XOR gate from both the
> Libraries Guide and Constraints Guide (MAP) entries. Can anyone point me to
> detailed documentation on the subject?
>
> Thanks,
>
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Martin Euredjian
>
> To send private email:
> 0_0_0_0_@pacbell.net
> where
> "0_0_0_0_" = "martineu"
>
> "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
> news:0rahb.13220$BQ7.7883@newssvr25.news.prodigy.com...
> > The following code:
> >
> > module PROBLEM
> > (
> > input wire CLK,
> > input wire [9:0] A,
> > input wire [9:0] B,
> > output reg [9:0] OUT
> > );
> > wire [9:0] xor2;
> > XOR2 XOR2_0 (.O(xor2[0]), .I0(A[0]), .I1(B[0]));
> > XOR2 XOR2_1 (.O(xor2[1]), .I0(A[1]), .I1(B[1]));
> > XOR2 XOR2_2 (.O(xor2[2]), .I0(A[2]), .I1(B[2]));
> > XOR2 XOR2_3 (.O(xor2[3]), .I0(A[3]), .I1(B[3]));
> > XOR2 XOR2_4 (.O(xor2[4]), .I0(A[4]), .I1(B[4]));
> > XOR2 XOR2_5 (.O(xor2[5]), .I0(A[5]), .I1(B[5]));
> > XOR2 XOR2_6 (.O(xor2[6]), .I0(A[6]), .I1(B[6]));
> > XOR2 XOR2_7 (.O(xor2[7]), .I0(A[7]), .I1(B[7]));
> > XOR2 XOR2_8 (.O(xor2[8]), .I0(A[8]), .I1(B[8]));
> > XOR2 XOR2_9 (.O(xor2[9]), .I0(A[9]), .I1(B[9]));
> >
> > always @(posedge CLK) OUT <= xor2;
> >
> > endmodule
> >
> >
> > ... produces interesting results. The tools run without a hitch, no
> error,
> > and no reports of logic being optimized out. However, if you look at the
> > end-product in the Floorplanner the LUTs that are supposed to be there are
> > nowhere to be found. Then, it gets interesting, go over to FPGA Editor
> and
> > every bit of logic is there as you would expect. What gives?
> >
> > This excercise started out as an attempt to build an RLOC'd parameterized
> > adder. Logic would not show-up in the Floorplanner so, eventually, I
> > reduced it to just an XOR clocking out to see what was wrong.
> >
> > Using ISE6.1i, SP1. Device is XC2V1000-FG456
> >
> > ...this is turning out to be one hell of a frustrating week!
> >
> >
> > --
> > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > Martin Euredjian
> >
> > To send private email:
> > 0_0_0_0_@pacbell.net
> > where
> > "0_0_0_0_" = "martineu"
> >
> >
> >
> >
> >
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61743Followup to: <906428f5.0310091342.3bb90eb3@posting.google.com> By author: chadb@beardendesigns.com (Chad Bearden) In newsgroup: comp.arch.fpga > > I would like to split a pci-x133 bus into 2 parallel pci-66 busses. > Has anyone done this? I'm not afraid to purchase the Xilinx pci-x > core and halfbridge IP but just looking for some wisdom. > > |--------| > | |<----- pci-66 -----> > <---pcix133--->| bridge | > | |<----- pci-66 -----> > |--------| > If you're looking for an existing silicon solution I believe you could do it with two Tundra Tsi310 parts. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 61744
"Ray Andraka" wrote: > What tool are you using? ISE6.1i / XST -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 61745
arkaitz wrote: > Thanks a lot. > > But, I don't understand how can I execute an "elf" file that affects > only to the internal registers of MicroBlaze enabling the timer, > interrupts, etc. but when I create a "hello world" program which > contains only a "print" code-line it doesn't work. don't forget you need to link your executable in "executable" mode, not xmdstub. then, once you run make (or generate from the xps), in the directory <myproject>/microblaze0/code will be a file executable.elf - that's the one you run objcopy over. > Have you done a flash programmer. How have done it? Via XMD or Serial? i started with xmd-based routines (they are still up on my website somewhere, i think under downloads), but now that uclinux is pretty much done, and i have network support i copy new images directly over the network into the flash, just using standard linux tools (NFS mounting, dd, MTD flash drivers and so on). For small systems this might not me an option. http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux Regards, John > > Thanks again. > > John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<bm30hp$fto$1@bunyip.cc.uq.edu.au>... > >>arkaitz wrote: >> >>>Thanks John, >>> >>>Now, where can I find some information related to the "elf" extension >>>file? If I'm not wrong it's used in Linux, isn't it? >> >>Yes - it's the standard object file format used by Gnu-based compilers (GCC) >> >> >>>Just another question: I've been looking to the MicroBlaze's manual >>>but I haven't found anything about "mb-objcopy". Is it in the manual? >> >>No - it's just part of the gnu tools distributed in EDK. Get a login on >>a linux box and do "man objcopy" - mb-objcopy is just the cross-platform >>version. mb-objcopy --help will probably tell you something too. >> >>www.gnu.org has an excellent documentation section - lots and lots of >>details about the linkers and compilers and so on - since mb-gcc and >>friends are direct descendants, 99.99% of that info is still highly >>relevant and useful. >> >>Regards, >> >>John -- Dr John Williams, Research Fellow, Reconfigurable Computing, School of ITEE University of Queensland, Brisbane, Australia Ph : (07) 3365 8305Article: 61746
"Ray Andraka" wrote: > When I read your problem statement, I thought you were saying that > that logic was not showing up in the floorplanner at all. That's correct. The LUT's are not showing up at all, anywhere, graphically or otherwise. I just doubled checked that. The Design Hierahchy window shows the IOB's, CLK, DFF's and that's it. Being that it's so short I'll type the contents of the Design Hierarchy window below: PROBLEM "PROBLEM" [31 IOBs, 10 DFFs, 1 BUFG] |_ CLK_BUFGP [BUFGP] O:CLK_BUFGP I:CLK |_ OUT_9 [DFF] Q:OUT_9 D:xor2<9> C:CLK_BUFGP |_ OUT_8 [DFF] Q:OUT_8 D:xor2<8> C:CLK_BUFGP |_ OUT_7 [DFF] Q:OUT_7 D:xor2<7> C:CLK_BUFGP |_ OUT_6 [DFF] Q:OUT_6 D:xor2<6> C:CLK_BUFGP |_ OUT_5 [DFF] Q:OUT_5 D:xor2<5> C:CLK_BUFGP |_ OUT_4 [DFF] Q:OUT_4 D:xor2<4> C:CLK_BUFGP |_ OUT_3 [DFF] Q:OUT_3 D:xor2<3> C:CLK_BUFGP |_ OUT_2 [DFF] Q:OUT_2 D:xor2<2> C:CLK_BUFGP |_ OUT_1 [DFF] Q:OUT_1 D:xor2<1> C:CLK_BUFGP |_ OUT_0 [DFF] Q:OUT_0 D:xor2<0> C:CLK_BUFGP |_ OUT<9> [IOB] O1:xor2<9> OTCLK1:CLK_BUFGP ... weird! |_ OUT<8> [IOB] O1:xor2<8> OTCLK1:CLK_BUFGP ... |_ OUT<7> [IOB] O1:xor2<7> OTCLK1:CLK_BUFGP ... |_ OUT<6> [IOB] O1:xor2<6> OTCLK1:CLK_BUFGP ... |_ OUT<5> [IOB] O1:xor2<5> OTCLK1:CLK_BUFGP ... |_ OUT<4> [IOB] O1:xor2<4> OTCLK1:CLK_BUFGP ... |_ OUT<3> [IOB] O1:xor2<3> OTCLK1:CLK_BUFGP ... |_ OUT<2> [IOB] O1:xor2<2> OTCLK1:CLK_BUFGP ... |_ OUT<1> [IOB] O1:xor2<1> OTCLK1:CLK_BUFGP ... |_ OUT<0> [IOB] O1:xor2<0> OTCLK1:CLK_BUFGP ... |_ CLK [IOB] I:CLK_BUFGP/IBUFG |_ B<9> [IOB]I:B_9_IBUF |_ B<8> [IOB]I:B_8_IBUF |_ B<7> [IOB]I:B_7_IBUF |_ B<6> [IOB]I:B_6_IBUF |_ B<5> [IOB]I:B_5_IBUF |_ B<4> [IOB]I:B_4_IBUF |_ B<3> [IOB]I:B_3_IBUF |_ B<2> [IOB]I:B_2_IBUF |_ B<1> [IOB]I:B_1_IBUF |_ B<0> [IOB]I:B_0_IBUF |_ A<9> [IOB]I:A_9_IBUF |_ A<8> [IOB]I:A_8_IBUF |_ A<7> [IOB]I:A_7_IBUF |_ A<6> [IOB]I:A_6_IBUF |_ A<5> [IOB]I:A_5_IBUF |_ A<4> [IOB]I:A_4_IBUF |_ A<3> [IOB]I:A_3_IBUF |_ A<2> [IOB]I:A_2_IBUF |_ A<1> [IOB]I:A_1_IBUF |_ A<0> [IOB]I:A_0_IBUF This is what's in the FPGA Editor's "List 1" window when set to "All Components": Name Site Type #Pins Hilited A<0> C12 IOB 1 15 A<1> C10 IOB 1 15 A<2> E11 IOB 1 15 A<3> B13 IOB 1 15 A<4> C11 IOB 1 15 A<5> F10 IOB 1 15 A<6> A7 IOB 1 15 A<7> K21 IOB 1 15 A<8> E15 IOB 1 15 A<9> L5 IOB 1 15 B<0> A13 IOB 1 15 B<1> B10 IOB 1 15 B<2> D10 IOB 1 15 B<3> A11 IOB 1 15 B<4> D11 IOB 1 15 B<5> F12 IOB 1 15 B<6> B7 IOB 1 15 B<7> K22 IOB 1 15 B<8> B16 IOB 1 15 B<9> L4 IOB 1 15 CLK D12 IOB 1 15 CLK_BUFGP/BUFG BUFGMUX0S BUFGMUX 3 15 OUT<0> B12 IOB 2 15 OUT<1> F11 IOB 2 15 OUT<2> E12 IOB 2 15 OUT<3> B11 IOB 2 15 OUT<4> F13 IOB 2 15 OUT<5> A10 IOB 2 15 OUT<6> A8 IOB 2 15 OUT<7> K20 IOB 2 15 OUT<8> F14 IOB 2 15 OUT<9> C8 IOB 2 15 PWR_VCC_0 VCC_X19Y1 VCC 1 15 xor2<0> SLICE_X34Y78 SLICE 3 15 xor2<1> SLICE_X26Y79 SLICE 3 15 xor2<2> SLICE_X28Y79 SLICE 3 15 xor2<3> SLICE_X31Y79 SLICE 3 15 xor2<4> SLICE_X30Y78 SLICE 3 15 xor2<5> SLICE_X26Y78 SLICE 3 15 xor2<6> SLICE_X12Y78 SLICE 3 15 xor2<7> SLICE_X62Y46 SLICE 3 15 xor2<8> SLICE_X49Y79 SLICE 3 15 xor2<9> SLICE_X0Y42 SLICE 3 15 Clearly one knows about the LUT's and the other does not. Furthermore, the Floorplanner is showing the outputs coming out of non-existant "xor2" entities. I guess the good news is that the FPGA Editor tells it like it is. (?) -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 61747
Jonathan Bromley wrote: > To improve performance, caches can have N-way associativity - in > other words, you have more than one cache slot associated with > each cache index. This means you have to compare addresses, but > typically only 2 or 4 rather than the full 32. You can generally > do this with parallel, single-cycle logic. > > If indexing on the bottom few bits of address doesn't > suit your requirement, you can use a more sophisticated > address mapping - perhaps some kind of hash function. It > doesn't matter, as long as the function is repeatable and > distributes addresses onto cache slots in a suitable way. > You would then need to store the whole address in the cache. An auxiliary victim cache could work well in distributed RAM.Article: 61748
Ray Andraka wrote: > I'd rather use a function or procedure within the HDL so that the > boolean expression is in the code and is used directly to generate > the init value. Not possible for the HDL which is not a complete programming language ;-)Article: 61749
"Tom Branca" wrote: > If you add a new definition for the XOR2 to your design, I believe > this will fix your problem. You may eventually want to change the name > of the XOR2 module in order to avoid confusion with the library > primitive. > > module XOR2 > ( > output O, > input I0, > input I1 > )/* synthesis attribute lut_map of XOR2 is yes*/; > assign O = I0 ^ I1; > endmodule // XOR2 > > - Tom Branca > - Xilinx That did it. Here's what I defined for XST: //synthesis attribute LUT_MAP of myXOR2 is YES; module myXOR2 ( output O, input I0, input I1 ); assign O = I0 ^ I1; endmodule Many thanks! -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"
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