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Hello sirs/friends, I didnot understand how will i pipeline parity checker. Can please tell in detail. how will i find parity, whether xor all 36 bits in one shot or is there any efficient way of finding the parity? should i have parity generator and parity generator as separate module. what is function of dataflow logic in PCI core? waiting for your reply praveenArticle: 54176
Thanks for your reply Ray and also Nicholas, Yet, I have some few questions remaining. How should we use this technique in practice, in HDLs? Take VHDL for example, how whe should write the code? And how to simulate it? From what Ray said I understand that there may be a way to write DA+SLR16 without explicit usage of Xilinx primitives. Obviously it should be like writing a code that a good synthesizer would ultimately optimize down to a single Xilinx LUT. So, now the question will be how to code such a LUT in a VHDL model that would feature all what we need (SLR16 mode, multiplexer in the output, implementation in a single xilinx LUT) and what synthesizer would be able to synthesize it correctly? And what about the simulation: can we use the same model for RTL simulations? And how much would be the code portable to different synthesize/simulation/verification tools? What will happen if we use the code for a FPGA family that do not have this feature? Would it function correctly (now obviously with penalties for speed/space)? Best Regards Arash "Ray Andraka" <ray@andraka.com> wrote in message news:3E8CAA0D.DC4695B4@andraka.com... > For a discussion on Distributed Arithmetic (DA), see the DA tutorial page on my > website. It is basically a method to take advantage of the LUT structure of an > FPGA to get more multiplies per unit area. It is traditionally bit serial, but > can also be parallelized to compute as many bits in parallel as you are willing > to pay for in area, all the way up to a full parallel implementation. It is > basically a rearrangement of the partial products in a sum of products to reduce > the hardwre. > > SRL16 mode is a Xilinx exclusive feature that allows the LUT to be used as an > addressable shift register. It is essentially a 16 bit serial-in parallel out > shift register with a 16:1 selector to select one of the 16 shift register taps > as the output. When the data is not being shifted in, it behaves exactly like a > LUT so that the data currently inside is addressed with the 4 LUT inputs. > > The SRL16s are useful for delay queues, in which case the address is generally > fixed and data is shifted in on every clock. For DA applications, normally one > uses LUTs containing all the possible sums of 4 constants times the 4 1 bit > inputs (see my website). A drawback to DA in the traditional sense is that the > coefficients are fixed since they are set at compile time. By replacing them > with SRL16's you can provide an ability to reload the coefficients without > having to reconfigure the FPGA. It requires some sort of loader circuit to > obtain the new data from somewhere (a memory or from some host processor), as > well as something to compute the LUT contents, which have 16 entries for each > set of four coefficients (this can be precomputed or computed inside the FPGA). > Support for SRL16's in other than a simple delay queue is somewhat sparse in the > synthesis tools, so we just instantiate the SRL16's. Instantiation has an added > advantage of letting you do the floorplanning in the code. The SRL16 is unique > to Xilinx, so even if the code were written without primitives, it wouldn't be > very portable. SRL16s can also be used for reorder queues by modulating the > address lines while data is shifting in. > > Arash Salarian wrote: > > > Hi, > > > > I've seen in many posts, ppl are talking about using distributed arithmetics > > and SLR16 in xilinx devices; mostly in Ray posts. I tried to find something > > to read about it using google but I had no chance. So basically I have only > > some guesses in my mind but no documents in hand. I've only a limited > > background about Xlinx devices and all I know is that the LUTs can be put in > > a SLR16 mode that would let us feed in a 16 bit value and then again by > > changing the mode back to normal, we'll have a LUT based on this value. > > So, what is this DA+SLR16 all about? Where and when should (or shouldn't) we > > use this technique? Where the LUTs' content come from? How should we store > > them (in BlockRAM?) How it's done in real practice, i.e. how we can code it > > in HDLs? Can we write a module in a HDL using this technique and yet > > preserve the portability (to other devices without such a feature, like > > Altera's)? How about simulations? > > > > Best Regards > > Arash > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 54177
acher@in.tum.de (Georg Acher) wrote in message news:<b6hgrt$meg$1@wsc10.lrz-muenchen.de>... > In article <20540d3a.0304030624.123cca37@posting.google.com>, > stenasc@yahoo.com (Bob) writes: > |> Hi all, > |> > |> I decided to have a go at writing a small fft for learning purposes. > |> (32 pts). I seem to be having problems with the fixed lengths for the > |> data. > |> > |> The twiddle factors are 16 bits. Initially, for butterfly stage 1, I > |> read in 16 bit input data (it has already been position reversed), do > |> the multiplication by the twiddle factor (I know you don't need to > |> multiply by the twiddle factor in the first stage as it is 1, but just > |> to keep it consistant).This brings the results for the real and > |> imaginary outputs to 32 bits. I truncate the 32 bits to the most > > A multiplication of two signed values with 16bit give a 31bit signed value. You > have only one sign bit in the output, but two in the input data ;-) > > Can that be the problem? Hi Greg, What seems to be happening is when I pass the 24 MS bits from one butterfly to the next, they mainly consist of sign bits ie mostlys 1's or 0's. The calculations in each butterfly add more sign bits with the result, that the final data ends up being all 0's or 1's. What can I do to avoid this ? Is there any way to scale the input data or do anything with the data passed between butterflys so this doesn't happen so this doesn't happen ? Regards BobArticle: 54178
acher@in.tum.de (Georg Acher) wrote in message news:<b6hgrt$meg$1@wsc10.lrz-muenchen.de>... > In article <20540d3a.0304030624.123cca37@posting.google.com>, > stenasc@yahoo.com (Bob) writes: > |> Hi all, > |> > |> I decided to have a go at writing a small fft for learning purposes. > |> (32 pts). I seem to be having problems with the fixed lengths for the > |> data. > |> > |> The twiddle factors are 16 bits. Initially, for butterfly stage 1, I > |> read in 16 bit input data (it has already been position reversed), do > |> the multiplication by the twiddle factor (I know you don't need to > |> multiply by the twiddle factor in the first stage as it is 1, but just > |> to keep it consistant).This brings the results for the real and > |> imaginary outputs to 32 bits. I truncate the 32 bits to the most > > A multiplication of two signed values with 16bit give a 31bit signed value. You > have only one sign bit in the output, but two in the input data ;-) > > Can that be the problem? Hi Georg Apologies for getting your name wrong, My typing fingers were operating quicker than my brain, not that that would be too difficult some days, and I can't even type!!! BobArticle: 54179
test
-----Original Message-----
From: Andy Peters [mailto:Bassman59a@yahoo.com]=20
Posted At: Tuesday, April 01, 2003 12:27 PM
Posted To: fpga
Conversation: More xilinx webpack verilog questions: always @(clock)
legal?
Subject: Re: More xilinx webpack verilog questions: always @(clock)
legal?
Jan Panteltje <panteltje@yahoo.com> wrote in message
news:<b64p0p$qe2$1@reader1.tiscali.nl>...
> Xilinx webpack 4.1, some question:
> If I use:
> always @(clock)
> it is optimized away (and subsequently no output at test)..
> if I use=20
> always @(posedge clock)
> things work, OK, then you get half the freq at test.
>=20
> I looked always() up in some verilog tutorial, and it seems to be
legal=20
> to write always @(clock)
>=20
> So is Xilinx wrong, or am I wrong, or what gives guys?
>=20
>=20
> module lcd_text_driver(clock, text, text_strobe,
> lcd_rst,
> lcd_read_data,
> lcd_e, lcd_rw, lcd_rs,
> lcd_write_data, lcd_dir, test);
>=20
> input clock;
> output test;
>=20
> // other in and outputs snipped
>=20
> reg [7:0] fstate;
> reg lcd_initialized;
> reg us_clock;
> wire test;
>=20
> // THIS=20
> //generate micro second clock (from 50 MHz)
> //always @(posedge clock)
> always @(clock)
> begin
> fstate =3D fstate + 1;
> if(fstate >=3D 50)
> begin
> fstate =3D 0;
> us_clock =3D !us_clock;
> end=20
> end // always
>=20
> assign test =3D us_clock;
> endmodule
>=20
> look at ..map:
>=20
> The signal "clock" is loadless and has been removed.
> Loadless block "clock" (PAD) removed.
Look again at your code. Without the "posedge," the always block is
sensitive only to clock, which means several things:
1) If you want an edge-triggered flip-flop, you need the "posedge,"
otherwise the synth tool will make a combinatorial latch. But ...
2) You code never uses the signal clock inside that block, so the tool
says, "whoops! You never use that signal, so the synth tool optimizes
it away. So, you have a latch, or something, that doesn't exactly do
what you want.
Remember that the "posedge clock" is what the synth tool uses as a
template for edge-triggered flops. When the tool sees it, it goes,
"ah! flop!" That's also why other signals shouldn't be on the
sensitivity list for a flip-flop.
Helpful side comment that may prevent much gnashing of teeth and
bullet-holes later:
Your comparison,=20
if (fstate >=3D 50)
may not do what you want. I would guess that fstate is not declared
an integer. However, Verilog helpfully considers the constant 50 to
be an integer, which is a 32-bit signed value. What happens is that
fstate is sign-extended to a 32-bit integer, and a bit-for-bit
comparison is made.
Follow this through. Say that fstate is declared like:
wire [5:0] fstate;
and, at some point, fstate is incremented and ends up as 6'd50. What
is the result of the following comparison:
(6'd50 =3D=3D 50)
?
To find the answer, simply sign-extend 6'd50 to 32 bits, and do a
bit-by-bit compare.
--a
Article: 54180This is an interesting discussion.. seems the Xilinx Spartan 2 current has flowed to Altera. I've also got a board with a space constraint.. I'ts still in the discussion phase so I havn't got a total fix yet.. but Cyclone or Spartan is the choice.. Cyclone because theres a rummor it can program its own config flash :-) But I have a question .. mainly for Martin because of the great work he did in the PSU evalutaion. (thanks for that by the way). When looking at the app note and then at Linear Tec's web site I noticed the LTC3251, 500mA switched cap. It has a peak current of 800mA so not much more but the current is delivered from a low ESR cap. How does that concept grab you ? Do you think it might be better / worse / same ? Arrow think its about US$2.01 Simon "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:ujYia.147215$Xa3.1268939@news.chello.at... > > I would like to thank all for their good ideas and help. > > > > I've tested some of the suggested ideas and wrote a little summary with > some > > osci plots. You can find them at: > > http://www.jopdesign.com/cyclone/powerup.jsp > > > > I've added plots for the darlington regulator circuit. > > Martin Schoeberl > >Article: 54181
> First question is whether either of the matrices is a constant, or if not if it is They are changing, because I want to use fpga as 'matrix co-processor'. I have to make 9 matrix multiplies and some addition in one algorithm pass, so I'll include some logic on higher address bits of matrix-ram. There are operations like A*B*C and A*B*A(transposed) so this logic will prevent copying matrix data between ram blocks. I think such copy-preventing will save me quite a lot of time. Nios will be using off-chip ram mostly, in-chip ram will be used generally for math data only (to speed-up things). Quartus shows that Nios will run for 63MHz in EP1C6, but Cyclones are quite new - I think good idea is to give at least 20% margin for fmax. Everything shows that I have >2000 LCes spare for matrices and 2 PI regulators (PI is small problem...), so it should fit into chip. I'll post results to this newsgroup, and (if I had enough time) maybe some 'opencore' code will be made? Who knows :-) -- jerry "The day Microsoft makes something that doesn't suck is probably the day they start making vacuum cleaners." - Ernst Jan PluggeArticle: 54182
> This is an interesting discussion.. seems the Xilinx Spartan 2 current has > flowed to Altera. > I've also got a board with a space constraint.. I'ts still in the discussion > phase so I havn't got a total fix yet.. but Cyclone or Spartan is the > choice.. Cyclone because theres a rummor it can program its own config flash > :-) > > But I have a question .. mainly for Martin because of the great work he did > in the PSU evalutaion. (thanks for that by the way). > > When looking at the app note and then at Linear Tec's web site I noticed the > LTC3251, 500mA switched cap. > It has a peak current of 800mA so not much more but the current is delivered > from a low ESR cap. > > > How does that concept grab you ? > Do you think it might be better / worse / same ? That's hard to say. I think that the required minimum startup current is not so high, but the FPGA 'takes what it gets'. It's more a problem of the regulator. If it detects a 'short circuit' with the maximum current at about 0.6 V. That's the trick with the helper circuits. The only way is to try it out (perhaps with the simulation circuit). I'm now happy with the LTC3405 and the darlington regulator. Martin > > Arrow think its about US$2.01 > > Simon > > > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message > news:ujYia.147215$Xa3.1268939@news.chello.at... > > > I would like to thank all for their good ideas and help. > > > > > > I've tested some of the suggested ideas and wrote a little summary with > > some > > > osci plots. You can find them at: > > > http://www.jopdesign.com/cyclone/powerup.jsp > > > > > > > I've added plots for the darlington regulator circuit. > > > > Martin Schoeberl > > > > > >Article: 54183
In article <20540d3a.0304040035.2558c5d9@posting.google.com>,
stenasc@yahoo.com (Bob) writes:
|> What seems to be happening is when I pass the 24 MS bits from one butterfly
|> to the next, they mainly consist of sign bits ie mostlys 1's or 0's.
|> The calculations in each butterfly add more sign bits with the result,
|> that the final data ends up being all 0's or 1's. What can I do to
|> avoid this ? Is there any way to scale the input data or do anything
|> with the data passed between butterflys so this doesn't happen so this
|> doesn't happen ?
The trick in FFT implementations with integer calculations is the scaling
strategy due to the restricted dynamic range. This includes the "placement" of
the input data and the scaling between the butterfly stages.
From your description it looks like you are scaling too much and are initially
passing too small values, so in the end you get just a -1/0/+1 rounding noise.
You should better use only bits (30:15) from the output of the multiplication and
don't use different bit lengths for the input and intermediate data. It get's
very confusing when doing the stuff for the first time.
BTW: I did also a FPGA-FFT from scratch a while ago, and I started first with the
"usual" float implementation in C. Then I replaced the float operations in the
butterfly kernel with functions for handling fixed point and conversion to and
from float. With that it is possible to check the correctness of each stage and
to see in which direction the values are going. The best way to find a scaling
problem is the "DC-offset" (real part for input point 0 if you see it as a
inverse FFT), since it is equally "spread" out over the 5 FFT-phases from one
input value to all output values.
After fiddling with the scaling and the memory addressing in the model, the
VHDL-implementation was quite easy. Now it's a 32point complex FFT core with
18Bit resolution, taking 100 cycles at 130MHz in a Spartan2. The core is then
used to calculate a 32K complex FFT in about 2.3ms for an OFDM-system :-)
--
Georg Acher, acher@in.tum.de
http://wwwbode.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 54184
In article <20540d3a.0304040041.2e7b0945@posting.google.com>,
stenasc@yahoo.com (Bob) writes:
|> Apologies for getting your name wrong, My typing fingers were
No problem, the names all have the same root ;-)
--
Georg Acher, acher@in.tum.de
http://wwwbode.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 54185Aldec provides FFT core for 256 points which needs 500 CLB slices + Memory. If your Spartan has enough memory resources- you would do. I have similar a core as well. A.Sergyienko Jerzy wrote: > > Hi > I'd like to know if is there any possibility to make usable IPCore > from Xilinx FFT 256pt, for Spartan? > Spartan IIe has similiar resources as virtex. > Or could You give me advice where I can find core this class? > > Greatings > > Jerzy GburArticle: 54186
> My distri. told me today I can expect the EP1C6 in may. type error: wanted to say: expect the EP1C12... The EP1C6 are available since a 'long' time agoArticle: 54187
acher@in.tum.de (Georg Acher) wrote in message news:<b6jomb$f5r$1@wsc10.lrz-muenchen.de>... > In article <20540d3a.0304040035.2558c5d9@posting.google.com>, > stenasc@yahoo.com (Bob) writes: > > |> What seems to be happening is when I pass the 24 MS bits from one butterfly > |> to the next, they mainly consist of sign bits ie mostlys 1's or 0's. > |> The calculations in each butterfly add more sign bits with the result, > |> that the final data ends up being all 0's or 1's. What can I do to > |> avoid this ? Is there any way to scale the input data or do anything > |> with the data passed between butterflys so this doesn't happen so this > |> doesn't happen ? > > The trick in FFT implementations with integer calculations is the scaling > strategy due to the restricted dynamic range. This includes the "placement" of > the input data and the scaling between the butterfly stages. > > From your description it looks like you are scaling too much and are initially > passing too small values, so in the end you get just a -1/0/+1 rounding noise. > > You should better use only bits (30:15) from the output of the multiplication and > don't use different bit lengths for the input and intermediate data. It get's > very confusing when doing the stuff for the first time. > > BTW: I did also a FPGA-FFT from scratch a while ago, and I started first with the > "usual" float implementation in C. Then I replaced the float operations in the > butterfly kernel with functions for handling fixed point and conversion to and > from float. With that it is possible to check the correctness of each stage and > to see in which direction the values are going. The best way to find a scaling > problem is the "DC-offset" (real part for input point 0 if you see it as a > inverse FFT), since it is equally "spread" out over the 5 FFT-phases from one > input value to all output values. > > After fiddling with the scaling and the memory addressing in the model, the > VHDL-implementation was quite easy. Now it's a 32point complex FFT core with > 18Bit resolution, taking 100 cycles at 130MHz in a Spartan2. The core is then > used to calculate a 32K complex FFT in about 2.3ms for an OFDM-system :-) Hi Georg, That sounds right, I am having another look at the scaling. I think you are correct. Thanks for your help. BobArticle: 54189
On Thu, 03 Apr 2003 20:22:22 -0800, Nicholas C. Weaver wrote: > In article <e8fd79ea.0304031738.3c3bb265@posting.google.com>, Matt Ettus > <matt@ettus.com> wrote: >>Thanks to everyone for the responses. We've decided for now to go with >>the Cyclone part, EP1C6, since it has more pins in the PQFP package. >> >>It seems to me that the non-BGA packages seem to be heavily >>deemphasized. I think that this is bad for many reasons: >> >>- protos harder to make and cost more - must use more board layers - >>rework difficult if not impossible >>- probing is much harder >> >>I hope that large PQFPs will be around for many years to come. > > Don't count on it by much. Pin bandwidth is a precious comodity, and a > PQFP-style package's bandwidth is a function of SQRT of board footprint, > while BGAs are linear in the size. > > Do you know if anyone's succeeded in Toaster-oven-soldering of BGA > packages? Dont know about toaster ovens but I've done 516 pin ones with a Granger hot air gun, No solder paste needed as the balls provide enough solder. you do need lots (and lots) of flux and some scheme of keeping the BGA aligned as you heat it (from behind) My guess is that toaster oven scheme would work if done in a similar fashion... PCWArticle: 54190
Simon, Like a bad cold? As you know, we designed out the power up issues in VII and subsequent products, and improved it substantially in 300mm SIIE. One caution, and I will raise it again: we have built 'zillions of Spartan II, IIE now (and IIE is all on 300 mm fab now). What that means is that we KNOW what it does, and we KNOW the abs max, and abs min numbers over PVT. Clever circuits that don't have access to all process corner material, and are verified over all temperatures and voltages aren't worth the paper (or html) they are on (in). You base your PDS (power distribution system) design on a few samples (from the same wafer, no doubt) and you will be very unhappy when you get surprised by what the next lot does to you....when it gets cold....or hot....or ramps on 'funny'....or..... Austin Simon wrote: > This is an interesting discussion.. seems the Xilinx Spartan 2 current has > flowed to Altera. > I've also got a board with a space constraint.. I'ts still in the discussion > phase so I havn't got a total fix yet.. but Cyclone or Spartan is the > choice.. Cyclone because theres a rummor it can program its own config flash > :-) > > But I have a question .. mainly for Martin because of the great work he did > in the PSU evalutaion. (thanks for that by the way). > > When looking at the app note and then at Linear Tec's web site I noticed the > LTC3251, 500mA switched cap. > It has a peak current of 800mA so not much more but the current is delivered > from a low ESR cap. > > How does that concept grab you ? > Do you think it might be better / worse / same ? > > Arrow think its about US$2.01 > > Simon > > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message > news:ujYia.147215$Xa3.1268939@news.chello.at... > > > I would like to thank all for their good ideas and help. > > > > > > I've tested some of the suggested ideas and wrote a little summary with > > some > > > osci plots. You can find them at: > > > http://www.jopdesign.com/cyclone/powerup.jsp > > > > > > > I've added plots for the darlington regulator circuit. > > > > Martin Schoeberl > > > >Article: 54191
stenasc@yahoo.com (Bob) wrote in message news:<20540d3a.0304030624.123cca37@posting.google.com>... > Hi all, > > I decided to have a go at writing a small fft for learning purposes. > (32 pts). I seem to be having problems with the fixed lengths for the > data. > .... > > Thanks > Bob Carter You didn't say what language you was using, C, Verilog, VHDL. Normally I would always do initial math study in C 1st, useful to later create test vectors for HDL test bench. Also you can just yank C FFT code off the web or textbook that works.Article: 54192
There are other choices: http://www.synplicity.com/products/altera/altera_promo.html In addition to a very reasonable price for a 1 year Synplify license this includes a 1-month license of Identify, which is an RTL level hardware debugging tool. - Ken McElvain CTO, Synplicity Paul Baxter wrote: > From Altera: > Dear LeonardoSpectrum(TM)-Altera Software User, > > Beginning April 1, 2003, Altera will no longer include > LeonardoSpectrum-Altera software licenses in software subscriptions or > with free software products. Altera will, however, continue to provide > Mentor Graphics(R) ModelSim(R) products for subscription customers and > will continue to work with Mentor Graphics as a key EDA partner to > support Altera(R) devices in commercial Mentor Graphics products. > Existing LeonardoSpectrum-Altera software licenses will continue to > work and Altera will continue to provide support for existing > LeonardoSpectrum-Altera software licenses distributed by Altera. > > ----------------------- > > Firstly, my hope was April fool's joke, but I'm not sure if they would be so > cruel.... so > > Oh dear, Altera's software solution just got worse. > They have dropped Leonardo synthesis tools. > > Leonardo was largely essential for getting decent synthesis over the full > range of VHDL constructs. > > Oh well, lets hope Altera just sells a PAR solution for a lower cost, > because I really need to get away from the below par bug-ridden stuff I keep > having to deal with. > > Cue Altera telling me its all now wonderful. Like I've heard a hundred times > already. I'm getting worked up because I've spent years overcoming tool > deficiencies and was comfortable with Leonardo + ActiveHDL + Altera PAR. I > however am bitter that I need to pay Altera for a 'full' design flow just > for PAR. > > Altera - I don't want your tools with half-baked promises of things working. > How about a feature freeze and a bit more time aiming for robust and > reliable. > > By the way, I'm not suggesting that Leonardo didn't have bugs, or other > manufacturer's tools are any better, just that after years of fighting and > getting a least worse low-cost solution I now have to either pay for > Leonardo (fair enough especially if Altera's PAR can be provided on its own > for much lower $$$) or have more Altera synthesis grief. > > Paul Baxter, my opinions are my own > > > >Article: 54193
Hi, I have the Xilinx Foundation v2.1i software, and am trying to get the license file. I tried registering trough Xilinx, and only 3 days ago they decided that they aren't going to issue licenses for this software. Does anyone know a way I can still use the software or can get a license? I'm a fourth year college student and need to use this software for a final project. Thanks, ScottArticle: 54194
In article <v8rimlesh8dk47@corp.supernews.com>, Scott <scott_howes@hotmail.com> wrote: >Hi, > >I have the Xilinx Foundation v2.1i software, and am trying to get the >license file. I tried registering trough Xilinx, and only 3 days ago they >decided that they aren't going to issue licenses for this software. Does >anyone know a way I can still use the software or can get a license? I'm a >fourth year college student and need to use this software for a final >project. What is your final project? 2.1 is VERY VERY old. Try downloading the Xilinx Webpack, it's a free beer liscence. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 54195
Hi I am developing a small design that it contain two modules (fixed and reconfigurable). The reconfigurable modules needed clock (sequential circuit). These reconfigurable modules are just small counters. The fixed module have some registers. I need one general reset signal that initialize all circuit (fixed and reconfigurable modules). So, I fixed Bus macros to pass some signals, including reset signal to other module (intercommunication between modules). I use constants inside of reconfig modules. (Ie: if pulse = "BF45" then...) But when I perform PAR (Place and Route) tool in the Active Module Implementation Phase of Modular Design, it happens the following warning: Line command: par -w top_map.ncd top.ncd top.pcf WARNING:Par:276 - The signal BM_reset_signal/TNET(3) has no load WARNING:Par:276 - The signal BM_reset_signal/TNET(2) has no load WARNING:Par:276 - The signal BM_reset_signal/TNET(1) has no load ------------------------------------------------------------------- PS: I have three output signals this bus macro that are open signals. What do I do with these signals? After to generate partial bitstreams of modules, when it´s performing the PAR tool of Final Assembly Phase of Modular Design, the following error happens: Line command: par -w top_map.ncd top.ncd top.pcf Loading device database for application par from file "..\..\pims/c_up/c_up.ncd". "top" is an NCD, version 2.37, device xc2v1000, package fg456, speed -4 The STEPPING level for this design is 0. FATAL_ERROR:Guide:basgitaskphyspr.c:366:1.17:137 - Guide encountered a Logic0 or Logic1 signal GLOBAL_LOGIC1 that does not have a driver or load within the module boundary. This problem may be caused by having a constant driving the input from outside the module boundary or because a driver or load comp did not meet the par-guiding criteria. The design will not be completely placed and routed by Par-Guide Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com Could someone help me? I appreciate any kind of help (or small tips). Eduardo Wenzel Brião Catholic University of Rio Grande do Sul state Porto Alegre city BrazilArticle: 54196
Well I'm desiging a 4 bit ALU, I'm using the XC4010XL FPGA, which is fairly outdated and is why I needed to use 2.1, because the webpack doesnt support that chip. "Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message news:b6ki0o$1hg0$1@agate.berkeley.edu... > In article <v8rimlesh8dk47@corp.supernews.com>, > Scott <scott_howes@hotmail.com> wrote: > >Hi, > > > >I have the Xilinx Foundation v2.1i software, and am trying to get the > >license file. I tried registering trough Xilinx, and only 3 days ago they > >decided that they aren't going to issue licenses for this software. Does > >anyone know a way I can still use the software or can get a license? I'm a > >fourth year college student and need to use this software for a final > >project. > > What is your final project? > > 2.1 is VERY VERY old. Try downloading the Xilinx Webpack, it's a free > beer liscence. > > > > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 54197
I looked at this last year. I was more or less satisfied with the core although I had less bits. One problem I had at 4 clocks per bit was not having access to the internal state of the 4-clock counter -- the delay depends on which tick the operands are presented. Perhaps this is a problem in simulation only (?) You may wish to see the posts dated 2002-09-12 at: http://groups.google.com/groups?hl=en&lr=&ie=ISO-8859-1&safe=off&q=Xilinx+LogicCore+Pipelined+Divider&btnG=Google+Search Also as I recall, the Xilinx Simulink blockset doesn't include a block for their divider core, while the Altera DSP Builder does. (If this has changed, do let me know.) -rajeev- ----------------- Salman Sheikh <sheikh@pop500.gsfc.nasa.gov> wrote in message news:<b6f44e$nru$1@skates.gsfc.nasa.gov>... > Hello, > > I am using Simulink to model a divider. My input is two integers of size 31 > bits for the numerator and 24 bits for the denominator. For the precision I > require, the result requires 43 bits consisting of 37 fractional bits and 6 > bits for the magnitude. I see that Xilinx has a pipelined divider core > (v2.0), but will this give me the resolution I need? If not, does anyone > know of any other cores that I can use for a Xilinx Virtex II part? > > > SalmanArticle: 54198
Scott wrote: > Well I'm desiging a 4 bit ALU, I'm using the XC4010XL FPGA, which is fairly > outdated and is why I needed to use 2.1, because the webpack doesnt support > that chip. I haven't looked recently (I've got Foundation 4 to work with), but isn't the only thing preventing XC4000 support via WebPACK the lack of xst support for the part? Didn't someone somewhere report that you can map/par these older parts with WebPACK if you have the EDIF file already at hand? If that is the case, then an XC4000 code generator for Icarus Verilog may be a highly worthwhile project. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 54199
In article <v8rjljekbqj086@corp.supernews.com>, Scott <scott_howes@hotmail.com> wrote: >Well I'm desiging a 4 bit ALU, I'm using the XC4010XL FPGA, which is fairly >outdated and is why I needed to use 2.1, because the webpack doesnt support >that chip. Why specifically the XL? Could you use a Spartain 1? -- Nicholas C. Weaver nweaver@cs.berkeley.edu
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