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Rick Collins wrote: > > Phil Hays wrote: > > > > Rick Collins wrote: > > > Then again some of the tools are nothing to brag about. I find that > > > Modelsim crashes once every 4 or 5 reloads of a design. > > > > Do you reload or restart the simulation? > > > > -- > > Phil Hays > > So far it only crashes when I am reloading a simulation. I often work in > a mode where I find several small bugs one at a time. I fix the problem > in my HDL and reload and restart the simulation. This does not require > that I exit the tool. But once in several reloads, it will get to the > end of complilation and instead of prompting me to input a command, it > crashes. Then I have to run Modelsim again and reload the simulation. > > -- > > Rick "rickman" Collins > > I've been using ModelSim PE on NT4.0SP4/6 for 2 1/2 years now & have had hardly any problems. The only time it seems to crash is when having failed to load a design because of e.g. a missing model I fix the error & then try to re-load the sim. The biggest problem for the PE version was a memory leak that didn't get fixed till 5.3c or 5.4c & we started with 4.7e. However that being said I run simulation in what might be a different way. I pre-compile all my Verilog source(s) into a set of libraries and then get the simulator to pull in the models from these using `-L' flags. So if I'm changing just a few bits of RTL source or maybe a testbench model or 2 then running the ``reload'' command only has to update these & not recompile the whole lot. I *do* have 1 or 2 gripes but in the whole I think its the best value for money of any EDA tool out there. I only wish I could presuade my colleagues to forgo their annual holidays so I could spend the dosh upgrading to the SE/EE edition under Linux.Article: 31151
Try to attatch different BLKNM attributes to the flip flops that should not be maped together. This can be done either in the .ucf file or in the VHDL code, what would look something like this: attribute BLKNM : string; attribute BLKNM of MyFF0 : label is "MyFF0"; attribute BLKNM of MyFF1 : label is "MyFF1"; More about this attribute can be found in the Xilinx Foundation documenation.... Hope, this works Patrick <hamish@cloud.net.au> wrote in message news:13SK6.827$25.3370@news1.eburwd1.vic.optushome.com.au... > For the last few days I've been fighting with Xilinx MAP's > "register ordering" feature. This "feature" attempts to group > flip flops with similar names (related by numbers in the signal name) > into the same slice. For example, mybus(0) and mybus(1) will be > mapped together, and so will mysig_0 and mysig_1. > > Of course, once MAP has done this, there's nothing PAR can do about > it. If mysig_0 and mysig_1 are both sourced and sunk on opposites > sides of the die, PAR will just place the slice as best it can, > and both paths may fail timing. Not desirable when you're running > fast (150MHz+) in a large chip (XCV2000E). > > I'm used to delaying signals in my code to improve the routing > by doing things like mysig_d1, mysig_d2, etc. However, since MAP > groups these together into a single slice, there's no routing > improvement at all. Same if you use a vector; mysig_d(0) and > mysig_d(1) will be grouped together. > > To make matters worse, when Synplify duplicates signals to > improve the fanout, the resulting signal names attract MAP's > attention. eg mysig may be duplicated to mysig_1, mysig_2 etc > which will be grouped into pairs by the register ordering. > > (On the other hand, it's a useful feature when you are dealing with > signals which truely are parallel parts of a bus. If you disable > register ordering (map -r), you can see what happens without it. > The logic gets a lot bigger, especially if you happen to be working > on a 64 bit bus; then timing fails due to routing congestion etc.) > > Any ways to work around this? MAP doesn't seem to allow you to > turn this off on a signal by signal basis. The best I can do is > to try to name signals so that MAP won't touch them. > Some things I've done to trick MAP: > > 1. Rename mysig_d1, mysig_d2 to mysig_1d, mysig_2d, etc. Doesn't > help if you use an array mysig_d(n downto 0) though. > > 2. Interestingly, if you have a signal mybus(7 downto 0), and Synplify > duplicates some of those, you get mybus_1(0), mybus_2(0), > mybus_1(1), mybus_2(2) etc. These get grouped as mybus_1(0) with > mybus_1(1), etc, which might not be so bad. > > It might be possible to use this to work around the problem with > mysig_d. What if mysig_d was an array of std_logic_vector(0 to 0)? > Your signals would be mysig_d(n)(0), which MAP might overlook. > > 3. The biggest hack, but the most effective.. use a Perl script to > modify the EDIF netlist after synthesis. I get my script to look > for particular signals which I want MAP to leave alone. It then > changes things like mybus(0) to mybus_0_, > mybus_1(0) to mybus_1_0_, mybus_d(0) to mybus_d_0_, etc. The > trailing underscore stops MAP from finding the number. > > #3 is pretty ugly. Synplify has an attribute to specify the > format of the signal name in the EDF -- syn_edif_bit_format. > You can apply it signal by signal, in your VHDL code. > However, I tried getting it to write out mybus(0)_, and the > attribute was completely ignored. Looks like it can only > let you configure the type of brackets used; (), <>, []. > > Anyone else have any ideas? This behaviour is a real killer on > signals with large fanout (eg in the order of several hundred, > to thousands of flip-flops). > > > regards > Hamish > -- > Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 31152
Rick, I'm running Windows 2000. Where can I find info on ModelSim PE? How much does it cost? Does it work with Virtex-E FPGAs? Thanks, Dave Feustel Fort Wayne, Indiana -------------------------------- "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3AFE90AE.D0BA307E@algor.co.uk... [snipped] > I've been using ModelSim PE on NT4.0SP4/6 for 2 1/2 years now & have had > hardly any problems. > The only time it seems to crash is when having failed to load a design > because of e.g. a missing model I fix the error & then try to re-load > the sim. The biggest problem for the PE version was a memory leak that > didn't get fixed till 5.3c or 5.4c & we started with 4.7e. > > However that being said I run simulation in what might be a different > way. I pre-compile all my Verilog source(s) into a set of libraries and > then get the simulator to pull in the models from these using `-L' > flags. > > So if I'm changing just a few bits of RTL source or maybe a testbench > model or 2 then running the ``reload'' command only has to update these > & not recompile the whole lot. > > I *do* have 1 or 2 gripes but in the whole I think its the best value > for money of any EDA tool out there. I only wish I could presuade my > colleagues to forgo their annual holidays so I could spend the dosh > upgrading to the SE/EE edition under Linux.Article: 31153
On Sun, 13 May 2001 06:12:08 -0500, "Dave Feustel" <dfeustel@mindspring.com> wrote: >Does anyone have any experience with >or opinion of the Avnet Virtex-E Development kit? I've worked with an Avnet xcv800 pci board and it is very nice. One gripe I have is that it has some micro connectors which are difficult to obtain. I wish someone sold some wire-wrapping board with a matching connector. Another thing you need to pay attention to is the oscillator has an enable pin and if you don't drive it, it might get assigned to zero so your clock dies as soon as you load your design. The board comes with full schematics which is nice because regular documents are missing som details. Muzaffer FPGA DSP Consulting http://www.dspia.comArticle: 31154
Not Verilog but this VHDL link should get you on the right track. http://www.cs.ucr.edu/~dalton/i8051/ "PeckPeck2" <chrisdekoh@pacific.net.sg> wrote in message news:3afe6375$1@news.starhub.net.sg... > Hi > Am doing a school project...concerning the designing the an 8051 core... > am wondering if anyone has written a similiar verilog code which I could > look at.. > > > > Thanks > > >Article: 31155
Eric Smith <eric-no-spam-for-me@brouhaha.com> writes: > Neil Franklin <neil@franklin.ch.remove> writes: > > Methinks, you do not know, that you can still get TOPS-20 v7.xx > > together with fitting hardware TOAD-1 [1] (an KL-10 clone with 30bit > > extended addressing) from XKL (http://www.xkl.com/). > > Bzzzt! No longer commercially available. Not any more? Bummer. All the more reason for me to get on with my clone then. :-) -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual RobberyArticle: 31156
Sounds like you need to add the black-box attribute to your component. Check the Synplify help. Michael w-y Lai wrote in message <9ditak$gcj$1@news.ust.hk>... >I construct the RAM in my VHDL program by the basic unit 16x1 which is >provided by the xc4000x >library, but when I do the synthesis stpe using FPGA_Express, it always says >16x1 RAM are unlinked Cell, how can I solve this problem? >Thank you very much! > >Here is my code for a 16x4 single port RAM > >----------- >library IEEE; >use IEEE.std_logic_1164.all; >library xc4000x; >library synplify; >use synplify.attributes.all; > >entity ram_16x1s is >--generic (init_val : string := "0000" ); >port (O : out std_logic; > D : in std_logic; > A3, A2, A1, A0: in std_logic; > WE, CLK : in std_logic); >end ram_16x1s; > >architecture xilinx of ram_16x1s is > >--attribute xc_props: string; >--attribute xc_props of u1 : label is "INIT=" & init_val; >component RAM16x1s > port (D : in std_ulogic; > WE : in std_ulogic; > WCLK : in std_ulogic; > A0 : in std_ulogic; > A1 : in std_ulogic; > A2 : in std_ulogic; > A3 : in std_ulogic; > O : out std_ulogic); >end component; >begin >Article: 31157
> On Sun, 13 May 2001 06:12:08 -0500, "Dave Feustel" > <dfeustel@mindspring.com> wrote: > > >Does anyone have any experience with > >or opinion of the Avnet Virtex-E Development kit? > > I've worked with an Avnet xcv800 pci board and it is very nice. One Odd, the Avnet Virtex Development Kit board I got last October came with an XCV300. Was the XCV800 a special model? > gripe I have is that it has some micro connectors which are difficult > to obtain. I wish someone sold some wire-wrapping board with a > matching connector. Another thing you need to pay attention to is the > oscillator has an enable pin and if you don't drive it, it might get > assigned to zero so your clock dies as soon as you load your design. > The board comes with full schematics which is nice because regular > documents are missing som details. Yeah, our board sat in the box ever since we got it, mainly because I didn't have the time to muck around with tapping I/Os from that funny AMP connector. I wound up buying an Xess XSV-300 instead. For my application, it turned out to be almost perfect. Now, I know Insight-Electronics (www.insight-electronics.com) offers a PCI base-connector board for their Spartan2-150 PCI evalualtion kit. The base-connector board converts the PCI 32-bit edge-connector into a bunch of standard pin headers, which are very easy to work with. (Naturally, the base-board doesn't generate any PCI signals of its own, and I'm sure it adds a lot of unwanted delay to the I/O paths.) This could be a good way to get generic test-points through the PCI-interface, for only $100.Article: 31158
On Fri, 11 May 2001 16:29:39 -0400, Eric <erv_nospam@sympatico.ca> wrote: >I've had the same problem many times, with unused pins being changed >to an output for some internal signal, and it seems to be an infortunate >trick used by the router when it can't complete operations (looks like a >minor bug). > >If you carefully look at the bitgen report, you'll see a warning about it. > >Spent the morning on it the first time it happened, now part of routine checks >whenever something goes wrong. > >----------- > >Talking about getting crazy with a Spartan, I recently had a design where >a controller loaded the configuration in a spartan, and it all worked well >as long as a ROM simulator was plugged. As soon as I started using a "real" >Eprom, the Spartan chip could not be configured anymore. > >I tried anything I could think about, like tweaking the bitstream upload software, >buffering the signals, adding an external latch, a serie resistor to prevent gliches, >slowing down the processor clock. Nothing helped. > >Somewhat confused, I hooked a second identical Spartan chip with only >PROGRAM, CCLK & DIN connected , and this one just got configured well, >while the one on the board still refused to work. > >I finally discovered that 2 of the IO lines that were connected to the processor's >data bus also had "TDI" and "TCK" as an alternate function (oups!). >Since I did not use JTAG at all, I overlooked the fact that during configuration, >these alternate functions are active and *will* badly interfere with the device >bitstream loading, if the timing is "right". > >As usual, the problem lied between the keyboard and the screen ... > >Eric. > Yeah, I've had similar fun with the HDC and LDC dual-function pins. I have learned to connect them to something *other* than a CPU bus! JohnArticle: 31159
Real quick newbie question: What is the safest way to implement a 4 bit register and/or latch in a Lattice 1024EA using Lattice's ispDesignExpert?Article: 31160
Hi
Am doing a school project...concerning the designing the an 8051 core...
am wondering if anyone has written a similiar verilog code which I could
look at..
Thanks
Article: 31161On Sun, 13 May 2001 16:16:07 -0700, sadadasdsa <dsadasdasdadada@jkdsljlfkskljkljslfsf.net> wrote: >> On Sun, 13 May 2001 06:12:08 -0500, "Dave Feustel" >> <dfeustel@mindspring.com> wrote: >> >> >Does anyone have any experience with >> >or opinion of the Avnet Virtex-E Development kit? >> >> I've worked with an Avnet xcv800 pci board and it is very nice. One > >Odd, the Avnet Virtex Development Kit board I got last October came with >an XCV300. Was the XCV800 a special model? > I believe they have a pci board with the larger chip because they have exactly the same package. >> gripe I have is that it has some micro connectors which are difficult >> to obtain. I wish someone sold some wire-wrapping board with a >> matching connector. Another thing you need to pay attention to is the >> oscillator has an enable pin and if you don't drive it, it might get >> assigned to zero so your clock dies as soon as you load your design. >> The board comes with full schematics which is nice because regular >> documents are missing som details. > >Yeah, our board sat in the box ever since we got it, mainly because >I didn't have the time to muck around with tapping I/Os from that >funny AMP connector. > >I wound up buying an Xess XSV-300 instead. For my application, it >turned out to be almost perfect. > >Now, I know Insight-Electronics (www.insight-electronics.com) offers a >PCI base-connector board for their Spartan2-150 PCI evalualtion kit. >The base-connector board converts the PCI 32-bit edge-connector into a >bunch of standard pin headers, which are very easy to work with. >(Naturally, the base-board doesn't generate any PCI signals of its own, > and I'm sure it adds a lot of unwanted delay to the I/O paths.) >This could be a good way to get generic test-points through the >PCI-interface, for only $100. actually we ended up using the same trick. We plugged in a pci backplane and hooked up logic analyzer probes on it. Muzaffer FPGA DSP Consulting http://www.dspia.comArticle: 31162
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--------------6462E3F33C1C4633D4220BB4 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Erik, True. We decided to fully test and disclose what is working in the ES material. The items that are partially working, as you say, may be just fine for investigation of a new feature. Obviously, production material has the fixes to the very few items that slipped through into silicon in the ES parts. If anyone has any comments on how to improve the Errata list process, or has had a less than perfect experience with it, please email me at austin@xilinx.com. This is a new procedure, and we are committed to continual improvements, Austin Erik Widding wrote: > "Meelis Kuris" <matiku@hot.ee> wrote in message > news:3afbcfb5@news.estpak.ee... > > > > "Erik Widding" <widding@birger.com> wrote in message > > news:%PaK6.12945$t12.971754@bgtnsc05-news.ops.worldnet.att.net... > > ... > > > revision. But overall, none of the errata is particularly bad, just > don't > > > expect the DCM to do all the really cool stuff listed in the data sheet. > > > > What do you mean by that? What doesn't it do then? > > Actually, the thing I'm concerned about is, does fine phase shift > > work ok (at 270MHz)? > > Can't test it right now myself but my whole project relies on that phase > > shift, so I'm a bit worried. > > There are a number of limitations listed in the errata. But it has been > reported to me by an FAE that some of the features with problems, i.e. > variable phase shift, are usable for testing purposes. In this particular > die revision many items listed in the errata are merely not 100% reliable, > or not 100% characterized. You should call your FAE to get a complete copy > of the errata. If a feature that you need is listed in the errata, call him > back to find out "just how broken" the feature is. Just because something > is listed on the errata as not working, doesn't necessarily mean that it is > completely broken. > > Regards, > Erik Widding. > > -- > Birger Engineering, Inc. -------------------------------- 781.481.9233 > 38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.com --------------6462E3F33C1C4633D4220BB4 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Erik, <p>True. We decided to fully test and <i>disclose</i> what is working in the ES material. <p>The items that are partially working, as you say, may be just fine for investigation of a new feature. <p>Obviously, production material has the fixes to the very few items that slipped through into silicon in the ES parts. <p>If anyone has any comments on how to improve the Errata list process, or has had a less than perfect experience with it, please email me at austin@xilinx.com. This is a new procedure, and we are committed to continual improvements, <p>Austin <p>Erik Widding wrote: <blockquote TYPE=CITE>"Meelis Kuris" <matiku@hot.ee> wrote in message <br><a href="news:3afbcfb5@news.estpak.ee">news:3afbcfb5@news.estpak.ee</a>... <br>> <br>> "Erik Widding" <widding@birger.com> wrote in message <br>> <a href="news:%PaK6.12945$t12.971754@bgtnsc05-news.ops.worldnet.att.net">news:%PaK6.12945$t12.971754@bgtnsc05-news.ops.worldnet.att.net</a>... <br>> ... <br>> > revision. But overall, none of the errata is particularly bad, just <br>don't <br>> > expect the DCM to do all the really cool stuff listed in the data sheet. <br>> <br>> What do you mean by that? What doesn't it do then? <br>> Actually, the thing I'm concerned about is, does fine phase shift <br>> work ok (at 270MHz)? <br>> Can't test it right now myself but my whole project relies on that phase <br>> shift, so I'm a bit worried. <p>There are a number of limitations listed in the errata. But it has been <br>reported to me by an FAE that some of the features with problems, i.e. <br>variable phase shift, are usable for testing purposes. In this particular <br>die revision many items listed in the errata are merely not 100% reliable, <br>or not 100% characterized. You should call your FAE to get a complete copy <br>of the errata. If a feature that you need is listed in the errata, call him <br>back to find out "just how broken" the feature is. Just because something <br>is listed on the errata as not working, doesn't necessarily mean that it is <br>completely broken. <p>Regards, <br>Erik Widding. <p>-- <br>Birger Engineering, Inc. -------------------------------- 781.481.9233 <br>38 Montvale Ave #260; Stoneham, MA 02180 ------- <a href="http://www.birger.com">http://www.birger.com</a></blockquote> </html> --------------6462E3F33C1C4633D4220BB4--Article: 31164
Meelis, I know the fixed phase shift works in silicon (my lab people tested it, and I have tested it, too). I suggest emailing the hotline for a a quick response. http://www.support.xilinx.com/support/clearexpress/websupport.htm Austin Meelis Kuris wrote: > Hi! > > I need to shift phase of 270MHz clock signal 90 degrees. > As I can't use CLK90 output of DCM in high frequency mode, > I'm using fine phase shift of clk0 output. > For some reason it doesn't work in simulation, output clock is > still exactly phase-aligned to the input clock. > I'm using Modelsim XE, with new libraries from xilinx site. > > Am I doing something wrong or is it just the simulation software? > > Thanks in advance, > > Meelis > > Here's the source: > ---------------------------------------------------------- > entity tb is > end tb; > > architecture tb_a of tb is > > component DCM > > port ( CLKIN : in std_logic; > CLKFB : in std_logic; > DSSEN : in std_logic; > PSINCDEC : in std_logic; > PSEN : in std_logic; > PSCLK : in std_logic; > RST : in std_logic; > CLK0 : out std_logic; > CLK90 : out std_logic; > CLK180 : out std_logic; > CLK270 : out std_logic; > CLK2X : out std_logic; > CLK2X180 : out std_logic; > CLKDV : out std_logic; > CLKFX : out std_logic; > CLKFX180 : out std_logic; > LOCKED : out std_logic; > PSDONE : out std_logic; > STATUS : out std_logic_vector(7 downto 0) > ); > end component; > > attribute DLL_FREQUENCY_MODE : string; > attribute CLKOUT_PHASE_SHIFT : string; > attribute PHASE_SHIFT : integer; > > attribute DLL_FREQUENCY_MODE of dcm1: label is "HIGH"; > attribute CLKOUT_PHASE_SHIFT of dcm1: label is "FIXED"; > attribute PHASE_SHIFT of dcm1: label is 64; -- actual phase shift is period > * PHASE_SHIFT / 256 > > component bufg port ( > I : in std_logic; > O : out std_logic); > end component; > > signal clk, clk90, gnd, Reset, clk90DCM1o : std_logic:='0'; > > begin > gnd <= '0'; > Reset <='0'; > clk<= not clk after 10 ns; > > dcm1 : DCM > > port map ( > CLKIN => clk, > CLKFB => clk90, > DSSEN => gnd, > PSINCDEC => gnd, > PSEN => gnd, > PSCLK => gnd, > RST => Reset, > CLK0 => clk90DCM1o > ); > > bufg5 : bufg port map( > I => clk90DCM1o, > O => clk90 ); > > end tb_a;Article: 31165
Hi! Here is free UART 16550 compatible core CVS webpage. You can download it if you want - it includes specs too. http://www.opencores.org/cvsweb.shtml/uart16550/ "Mark Walter" <maw@nospam.com> wrote in message news:1ALH6.226933$GV2.47295492@typhoon.san.rr.com... > Does anyone know of where I can find a free Verilog source code for a Serial > UART that can be used in a Xilinx XC4005XL FPGA? I am in need of such code > to add to a FPGA design I am making for remote access to the FPGA CPU... > > Thanks, > Mark > >Article: 31166
Hi!
As I can see on this newsgroup, there is a lot of interest in FREE IP
cores for different purposes. I'm a member of OpenCores group that provides
quite a few of them.
Anyone interested is free to browse through our website and CVS repository:
www.opencores.org
There is a lot of interest among developers and engineers for PCI IP core
which is also interesting to design. We are currently developing PCI to
WISHBONE SoC bus bridge core and we need developers that are willing to
contribute their knowledge and experience in form of Verilog or VHDL design,
verification or at least advice.
We have prepared preliminary PCI IP core specification, available at
http://www.opencores.org/cores/pci/
Anyone interested can also subscribe to our mailing list via internet:
http://www.opencores.org/mailinglists.shtml
Regards,
Miha Dolenc
Article: 31167For some time now I've noticed that every now & again PAR would hang up in the ``route PWR/GND'' phase of iteration 2. Or, at least, progress would slow to a crawl. Since I've only got 722 such connections none of the answers on the web seemed at all relevant. Slowly it began to dawn on me that this only seemed to happen on a *Sunday* !? Since this realisation I've kept a record & sure enough for the 4th time since I started recording it happened again yesterday, Sunday! This is at least an engineering level proof that something weird is going on. 2 possible explanations present themselves: o The day of the week is used as some sort of random seed for a heuristic algorithm. o There's an underground member of the hard religious right who has bombed the s/w. I can generally unblock the problem by using a cost table other than the default 1.Article: 31168
"Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3AFF54B3.50B5DD4B@xilinx.com... > Meelis, > > I know the fixed phase shift works in silicon (my lab people tested it, and I > have tested it, too). > > I suggest emailing the hotline for a a quick response. > > http://www.support.xilinx.com/support/clearexpress/websupport.htm Well: "WebCase is NOT available to students." And that's exactly what I am. I just can't get to that web page. MeelisArticle: 31169
Hi, I'm interested in using a huffman decoder as part of a jpeg project. So far, I've seen a core from Ocean Logic (http://www.ocean-logic.com/pub/OL_Huff.pdf), but the datasheet seems a bit non descriptive (the same core pops up in a few places under license, I think; Xentec seem to do the same one). Does anyone know about / can anyone recommend a core for this task, or have info on price, clock speed, size, etc? Thanks, GArticle: 31170
There is been many messages about failed Xilinx device programming, I found following bug. I used the Hardware Debugger of the Xilinx Foundation F3.1i for Virtex E (XCV1000EBG560 in my case) programming, slave serial mode, LPT cable. When start downloading design, PROG (LPT pin 6) goes low and remains low until the end of the bitstream. Of course, the result is that configuration fails. Normally there must be low lewel pulse only before configuration. I disconnected the TMS/PROG wire from /PROG pin of the FPGA and resetted FPGA manually, then configuration was successful. JaanArticle: 31171
In comp.arch.embedded Ben <ejhong@future.co.kr> wrote: : Hi, : I have a PCI device whose interface is not compatible with CardBus : standard. But I want to build a CardBus PC Card with the PCI device. What, exactly, is not compatible? Granted, I have not throughoutly checked this, but CardBus32 (NOT PCMCIA) looks PCI compliant to me. You will have to hardwire the separate Card Detect and Voltage Detect lines, but the protocol is PCI. So, given a PCI peripheral device target chip, turning it into a CardBus device should be a simple routing problem. : By the way, does it make sense to build a CardBus PC Card : with a PCI device? It does, and I am thinking of doing the same thing. -- ****************************************************** Never ever underestimate the power of human stupidity. -Robert Anson Heinlein GeirFRS@invalid.and.so.forth ******************************************************Article: 31172
Software: synopsys-fpga_analyzer, First I use fpga compiler to optimize my design. then transfer the optimized CLB and IOB to gates then save as .xnf format. But the *.xnf failed to be generated. It is because the startup file still contains the IOB, which isn't transferred to be the gates What's wrong with it? would anyone giveme a hand? Thank you!!Article: 31173
Hi! I've been using Modeltech XE which comes with WebPack and I'm getting really tired of this design size limitation and it's generally quite slow and the DCM phase shift problem I wrote about, etc. So, what other free/shareware simulator can I use for simulation where I can also use Virtex2 specific things like DCM? Can I use Veribest simulator coming with Actel Desktop software? Is it possible to use unisim library with it? How? Tried linking the same unisim library which was meant for Modelsim, no success. Or any other suggestions? Thanks, MeelisArticle: 31174
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