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Hi, We´re an University searching team and we´re working on Xilinx FPGA technology. We´ve developed a program to be downloaded into our FPGA desing by the Xchecker cable. Now, we´d like to keep our program in a PROM. But, unfortunately, we don´t know how to translate our FPGA file into a PROM file to be downloaded to the PROM. We´re looking for information about a translator program (SW) and any useful tips related to that. Do you know something about that? Would you mind helping us? Thank you so much for your help!. Best regards, Segis.Article: 31001
Can anyone out there who has used these devices tell me: o How good/efficient/robust the s/w is ? aka how good is 3.3i+latest SP ? o How the -4,5,6 speed grades compare with the Virtex-E -6,7,8 in ``real life''? o Where you can actually get some ? In particular the XC2V1000FF896Article: 31002
Hello, I'm looking for information on the use of a Move-type of microprocessor being used in a product. Two that have been mentioned in various sources are: New England Digital ABLE processor in AppleTalk routers George Risk Industries producing a move processor based product Implementations in a FPGA? If anyone has any information on either, I'd greatly appreciate it. Thanx in advance for your help. -- Will Gilreath will@williamgilreath.comArticle: 31003
Hi all, While I am waiting for a response from National, I may as well ask some questions here. I am driving a DS90CR483 ChannelLink transmitter with an Altera 20K200EFC484 FPGA. I am driving 48bits of LVTTL data into the DS90CR483 at 33MHz and at 66MHz. At 33MHz everthing seems to be fine. At 66MHz data rate, with a few of the 48bits of LVTTL data driven, everything looks ok. But when I drive all 48bits of LVTTL data at 66MHz, the LVDS clock from the DS90CR483 has huge amounts of jitter and noise. The eye diagram of an LVDS data line also exhibits similar behaviour, which I assume is as a result of the clock. My clock generator feeding the DS90CR483 has fairly slow edges, around 6ns. I suspect that this is switching noise getting into the DS90CR483 PLL, but I am not really sure and I am still doing some measurements. Any ideas or suggestions from anybody that has used these ChannelLink transmitters would be appreciated. Tony. _________________________________ Tony Proudfoot, tonyp@vl.com.au Hardware Design Engineer _________________________________Article: 31004
you may want to check out Nallatech www.nallatech.com -Rich Rotem Gazit wrote: > I am looking for a prototyping board with the following characterizations: > > 1) TI 5408 or 548 or 5409 or 549 DSP. > > 2) Xilinx Virtex or Spartan-II FPGA. > > (Didn't find any in Optimagic or Xilinx WEB sites). > > Thanks for your help, > > Rotem.Article: 31005
Hey there,
I'm started a project 4 months ago using Xilinx Student
Edition v2.1 tools and an evaluation board (XESS XS40). It turns out
I've since needed to use 32-bit IEEE floating point addition and
multiplication throughout my design. Currently, there the evaluation
board I'm using no longer has the real-estate I need to implement my
design with. When I attempt to synthesize and simulate this design with
the Xilinx Student Edition v2.1 tools, it runs out of memory (even
through I'm using a WinNT platform with 256MB of SDRAM).
To solve my real-estate problem, I'm probably going to
purchase one of the Xilinx Vertex-II FPGAs. However, I'm not sure which
of the following Xilinx Development Systems I should purchase (to help
overcome the rest of my problems):
1. Alliance Series
2. Foundation Series ISE, or
3. Foundation Series
How do these Xilinx Development Systems compare?? Any suggestions or
recommendations?? Does anybody know if any of these Xilinx Development
Systems have support for 'real' types in VHDL (i.e. floating point
numbers)?? Thanks.
Kris Nichols
Article: 31006I am using Foundation iSE 3.1i,VirtexII 2v1000,456pin I used 10 FIFOs(32width*64depth),2 RAMs(32*18) which are all generated by CORE Generator with RPM , but after PAR,7128 nets can not be routed, most of which are data bus and address bus. Is this problem concerned with RPM? Thank you!Article: 31007
I am using Foundation iSE 3.1i,VirtexII 2v1000,456pin I used 10 FIFOs(32width*64depth),2 RAMs(32*18) in my design which are all generated by CORE Generator with RPM , but after PAR,7128 nets can not be routed, most of which are data bus and address bus. Is this problem concerned with RPM? Thank you!Article: 31008
Hello, Where could I find any tutorials to floorlplaning and layout on the inet? Best regards TomekArticle: 31009
Hi there,
According to me, what you have put in the function description is a 4-bit and
function. Since the compiler needs at least an nor/nand + inverter, this gives
a problem.
I suggest that you take a look to libraries from Altera/Xilinx to get a good
idea
on the approach you need to take for the library.
Kind regards,
Koen
Venkatesh Akella wrote:
> Hi,
>
> Recently I've been playing around with Synopsis Library Compiler trying
> to develop a LUT based FPGA synthesis library. From what I have read from
> the Reference Manuals and User Guides (as sketchy as they are) it seems I
> have been able to develop a library that compiles, but not one I can perform
> synthesis with.
>
> In essense I'm trying to get FPGA_compiler to technology map to LUTs
> rather than gate primities during synthesis, but appear not to be having any
> luck. My synthesis library only contains a LUT definition and registers. The
> LUT definition is as follows:
>
> library ( lut ) {
> technology ( fpga );
>
> ..... etc.....
>
> cell (lut4) {
> area : 0.5 ;
> pin ( A B C D) {
> direction : input;
> }
> lut(L) {
> input_pins : "A B C D" ;
> }
> pin (Z) {
> direction : output;
> function : "(L)" ;
> }
> }
> }
>
> This compiles fine with Library compiler and produces the library file
> lut.db.
>
> However, when I try to compile a small design with very simple
> combinatorial logic, FPGA_compiler gives the following error message:
>
> compile -map_effort medium
>
> Loading target library 'lut'
> Error: The target library does not contain all required gates.
> Either a NOR, or an AND and an OR gate (two-input) is required for mapping.
> (OPT-102)
> Information: Compile terminated abnormally. (OPT-100)
>
> It appears that FPGA_compiler requires at least a NOR or and AND and an
> OR gate to technology map. However, I would like to direct it to map to LUT
> technology as decribed by my synthesis library.
>
> Is there something that I am missing here? I've tried many different
> times but with no success. Can anyone help me in trying to resolve this
> problem.
>
> Thanks in advance,
>
> Mathew
>
> mwojko@yahoo.com
Article: 31010"Roger.chen" wrote: > > My design is quite large,the functional simulation is ok.When > doing post timing,I found the output 200MHz clock of my clock > module is constant "0", later I tried to do timing simulation of > clock module seperately,the problem still exists. Hi Are you sure the simulation resolution is small enough? I encountered the same kind of problem with a Virtex simulation (I don't know about Virtex-II): the DLL model won't simulate correctly if the resolution is greater than 100ps. -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 31011
In article <3af9ebbf.2054834@news.dtgnet.com> jeffb"at"sencore.com writes:
>asuihkon@beta.hut.fi (Aki M Suihkonen) wrote:
>>In article <3AF74FEC.9CE2C870@xilinx.com> Vikram.Pasham@xilinx.com writes:
>>>Berni & all,
>>The discrete noiseless channel section contains an example of
^^^^^^^^^
>>a 'perfect code' Hamming (7,4) under a restricted noise model.
^^^^^
>>In this case, C = 4/7 - not including the parity.
I guess, I didn't bother to check my message -
it's of course the discrete channel with noise I'm referring to.
>
>Funny, the only reference to Hamming that I see in the paper is in
>PART II: THE DISCRETE CHANNEL WITH NOISE subsection...
>17. AN EXAMPLE OF EFFICIENT CODING on page 27.
>In the equation you refer to, Shannon is setting up an (unrealistic) example
>where a block of seven binary symbols can either be unerrored, or have exactly
>one errored symbol. The equation shows that this (non-AWGN) noise condition
>creates a channel with 4/7 bits/symbol capacity (this has nothing to do with
>parity, he hasn't even discussed the Hamming block code yet!) He then at the
>top of page 28 shows how a seven symbol Hamming block code can identify the
>errored symbol in the above example. Did *you* read the paper? Did you read
>the original post? BTW - This thread has been discussing the Shannon-Hartley
>theorem and the equation for channel capacity of a band-limited channel in the
>presence of AWGN (bits-per-second).
Yes, I did read the paper.
What I believe, that Shannon included the Hamming code as an example of
coding, that will be able to transmit C=4/7 bits/symbol without error,
given that the entropy of the noise channel is known - and also that
N is very finite.
>>Progressively more complex coding will at N -> inf, correct N*H bits
>>where H is the entropy of the noise channel.
At the time of Shannon wrote the paper, BCH was not known.
If it were, I believe Shannon would have included a coding
BCH( 2^N, 2^N*log2(H)*K ) or something to prove the point.
-> disclaimer - I dont have time or perhaps the ability to derive
the equation for perfect BCH coding for H when N -> inf.
My point is that Shannon is consistent with the notation.
There is an analogy between H and C in the discrete noisy model
and the SNR and C in the bandwidth limited model.
--
Problems 1) do NOT write a virus or a worm program
"A.K.Dewdney, The New Turing Omnibus; Chapter 60: Computer viruses"
Article: 31012Tomasz Brychcy wrote: > Hello, > > Where could I find any tutorials to floorlplaning and layout on the inet? > > Best regards > > Tomek Ray Andraka has a very informative document on his site: http://www.andraka.com. Tool manuals and numerous tries and feedback/know-hows from these tries will give you the best answer. I have tried at least 35 different floorplannings for a XCV2000E and still have lot of things to do on this way. UtkuArticle: 31013
On Wed, 9 May 2001 08:10:05 +0200, "Tomasz Brychcy" <T.Brychcy@ime.pz.zgora.pl>
wrote:
>Hello,
>Where could I find any tutorials to floorlplaning and layout on the inet?
>Best regards
>Tomek
You might try "Introduction to Floorplanning" at
http://www.fliptronics.com/floorplanning1.html
A bit dated, but still relevant
Philip
Philip Freidin
Fliptronics
Article: 31014Rick Filipkiewicz wrote: > Can anyone out there who has used these devices tell me: > > o How good/efficient/robust the s/w is ? aka ho I recompiled a couple of old designs to get a feeling for the Virtex-II Performance. They went through without any problems. But the designs were rather small (up to 900 LUTs) I did not implement them in hardware. > o How the -4,5,6 speed grades compare with the Virtex-E -6,7,8 in > ``real life''? -4 speedgrade was about 60% faster than Spartan-II -5 > o Where you can actually get some ? In particular the XC2V1000FF896 I only could find samples of XC2V40 for about $30 at insight and nuhorizon Kolja SulimmaArticle: 31015
"Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3AF87AD0.F5D3462F@algor.co.uk... > > Can anyone out there who has used these devices tell me: > > o Where you can actually get some ? In particular the XC2V1000FF896 We bought XC2V1000FG456 from NuHorizons. It was a factory order and it was NCNR. There still are a few kinks in the silicon (two page errata sheet), so I wouldn't expect distribution to stock parts until the next die revision. But overall, none of the errata is particularly bad, just don't expect the DCM to do all the really cool stuff listed in the data sheet. Right now, it only does most of the cool stuff. I think it took us about four weeks to get parts, after we ordered them. Regards, Erik Widding. -- Birger Engineering, Inc. -------------------------------- 781.481.9233 38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.comArticle: 31016
Kris, Support for floating-point types would depend on the synthesis tool, but I believe that it is included in the numeric_std.vhd IEEE library, so it should be supported by most synthesis tools. As a relatively new user, Xilinx would suggest the Foundation ISE tools. As a VHDL user, you will benefit from having two synthesis tools: Synopsys FPGA Express and XST, Xilinx's new synthesis tool. I have found that having two synthesis tools makes debugging code quite a bit easier. Working at the Hotline here at Xilinx, I have to use all our tools quite often, and have come to prefer the ISE enviornment over the older Aldec Foundation software, especially for primarily HDL designs. Alliance will not likely not be your choice as it is only is the back-end implementation tools. You will need your own synthesis and/or schematic capture to complete your design flow. Of course you should try the ISE enviornment for yourself. You can download the free WebPACK ISE software which will have the same interface as Foundation ISE. You may also be elegible for a 30-day trial of Foundation ISE by contacting your favorite distributor or browsing here: http://www.xilinx.com/switchtospeed/ I hope this helps, Dylan Buli Xilinx Applications Kris Nichols wrote: > Hey there, > I'm started a project 4 months ago using Xilinx Student > Edition v2.1 tools and an evaluation board (XESS XS40). It turns out > I've since needed to use 32-bit IEEE floating point addition and > multiplication throughout my design. Currently, there the evaluation > board I'm using no longer has the real-estate I need to implement my > design with. When I attempt to synthesize and simulate this design with > the Xilinx Student Edition v2.1 tools, it runs out of memory (even > through I'm using a WinNT platform with 256MB of SDRAM). > To solve my real-estate problem, I'm probably going to > purchase one of the Xilinx Vertex-II FPGAs. However, I'm not sure which > of the following Xilinx Development Systems I should purchase (to help > overcome the rest of my problems): > 1. Alliance Series > 2. Foundation Series ISE, or > 3. Foundation Series > How do these Xilinx Development Systems compare?? Any suggestions or > recommendations?? Does anybody know if any of these Xilinx Development > Systems have support for 'real' types in VHDL (i.e. floating point > numbers)?? Thanks. > > Kris NicholsArticle: 31017
From an IC layout perspective, analog is placed by hand and is a true art where as digital layout is more of a pushbutton approach once you define your boundaries.... Technically it's all analog. >Analog design includes analog signals that change continously between >extremes. >Digital design includes digital signals that can have only a few >distinguishable states. > >HC > >Tomasz Brychcy wrote in message <3af77f8d$1@news.vogel.pl>... >>Hello, >> >>What is a difference between analog design and digital design? >> >>Best regards >> >>Tomek >> >> > > ------------------------------------------------------------------ Beau Schwabe IC Mask Designer National Semiconductor Wired Communications Division 500 Pinnacle Court, Suite 525 Mail Stop GA1 Norcross, GA 30071 ------------------------------------------------------------------Article: 31018
This is a multi-part message in MIME format. --------------2E552DAD0D51C151445957EE Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit I never saw the original post but if this person is using FC1 to target a Xilinx device, I would first check to see that not only the proper libraries were declared but also in the proper oder. There is a utility called "synlibs" than when run, will output the proper library declarations for running DC or FC1. I would run this and verify the proper libraries are being used in the .synopsys_dc.setup and/or script file. Second, I would be sure this user is not doing something to shoot himself/herself in the foot when compiling the design. The advanced capaibility of DC/FC gives this opertunity more-often than not it seems. I would suggest to look at the sample run scripts in the $XILINX/synopsys/examples directory and possibly use one of these scripts to compile the design. I would also double check the .synopsys_dc.setup file against the template shown in this directory. Most likely, after following those two suggetsions, you will no longer see this problem. The better solution for now would be not to use FC1 and instead use FC2 as it generally gives better results but that is up to the user. -- Brian Srinivasan Venkataramanan wrote: > Hi, > > Venkatesh Akella wrote: > > > > Hi, > > > <SNIP> > > combinatorial logic, FPGA_compiler gives the following error message: > > > > compile -map_effort medium > > > > Loading target library 'lut' > > Error: The target library does not contain all required gates. > > Either a NOR, or an AND and an OR gate (two-input) is required for mapping. > > (OPT-102) > > I haven't used this tool, neither I am a FPGA Designer. > > In general Logic synthesis rests on the fact that NAND & NOR are > basic gates and we could implement any complex combinatorial logic > with either of them (or both). So I think what FPGA express trying to > do is to do this simple check before proceeding further. So to make > the tool happy, just add a NOR gate to your library and set a > "dont_use" attribute on that cell. > > Not sure whether this will solve your problem (:- > > Good Luck, > Srini > > > Information: Compile terminated abnormally. (OPT-100) > > > > -- > Srinivasan Venkataramanan (Srini) > ASIC Design Engineer, > Chennai (Madras), India --------------2E552DAD0D51C151445957EE Content-Type: text/x-vcard; charset=us-ascii; name="brian.philofsky.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brian.philofsky.vcf" begin:vcard n:Philofsky;Brian x-mozilla-html:TRUE url:http://www.xilinx.com org:Xilinx Software Marketing;SLAM adr:;;2300 55th St;Boulder;CO;80301;USA version:2.1 email;internet:brian.philofsky@xilinx.com title:Sr Technical Marketing Engineer fn:Brian Philofsky end:vcard --------------2E552DAD0D51C151445957EE--Article: 31019
Rick, 2V1000ES are here at the factory. I don't know about the FF896, but I did evaluate one in the lab, and it is a really clean nice package (tons of connections to ground so it is really quiet for ground bounce -- love those flip chips!). It is -5, even though ES is not "graded". The -5 for 2V is faster than the -8 for Virtex E. As an example, in Virtex E a design with 155 MHz global clocks is getting agressive, and constraints may get tough to meet in a large design. In Virtex II, we see the same at 311 MHz. That isn't to say that with careful tweaking and floor planning you can not do better in either. By the way, there are 2V40's in fg256 as ES around, too. Get to a disti or FAE. Austin Rick Filipkiewicz wrote: > Can anyone out there who has used these devices tell me: > > o How good/efficient/robust the s/w is ? aka how good is 3.3i+latest SP > ? > > o How the -4,5,6 speed grades compare with the Virtex-E -6,7,8 in > ``real life''? > > o Where you can actually get some ? In particular the XC2V1000FF896Article: 31020
I apologize to all those posting/reading the recent Shannon capacity thread. I was 100% wrong in my statements about parity bits. Here is some background... There has been an on-going thread in this news group about Shannon capacity. The original question was about the following equation: C = W*Log2(1-S/N) bps Does the caculated capacity C include parity bits of a coded channel? I now believe the answer is *no, it does not*. Throughout Shannon's paper, C refers to the *information rate only*. The above equation shows the relationship between the amount of error-free *information* throughput, bandwidth and S/N. The information throughput does *not* include the added bits due to whatever coding scheme is chosen. In the following typical system, the above equation shows the limit to the total info in and out for a channel of a given bandwidth and S/N. The challenge of the engineer is to design the encode/decode and mod/demod functions so as to achieve this limit. info in -> encoding -> modulation -> channel -> demod -> decode -> info out Again, in my previous posts I mis-stated how "parity" bits are considered in the above equation/system. I apologize for any confusion. Good Day to all. NemoArticle: 31021
On Tue, 08 May 2001 16:39:51 -0500, Kevin Smith <xkevinsm@ti.com> wrote: >This is a multi-part message in MIME format. >--------------40F4E444352D0E868141E55A >Content-Type: text/plain; charset=us-ascii >Content-Transfer-Encoding: 7bit > >Why not use OFFSET=IN BEFORE and OFFSET=OUT AFTER so the P&R tool does >the arithemetic for you? If you use these options it takes into account both >the clock period >(assuming you use a PERIOD constraint), as well as the clock input buffer >delay. >--- >Keb'm Maybe I'm missing something (quite possible), but I know what the clock->out the circuit driving the FPGA and the input setup times of the circuit driven by the FPGA. The clock->out of the driving circuit (plus wiring delay) gives me the value for OFFSET = IN AFTER. PAR then figures out the needed I/O timings based on the clock. Likewise, the driven circuit's setup time would be an OFFSET = OUT BEFORE constraint to my FPGA. Interestingly, Synplify gives what I want (but has other problems), while the Xilinx Constraints Editor apparently doesn't. It looks like I'm going to have constraints all over the place. ---- Keith ========================================== > >"Keith R. Williams" wrote: > >> Is there a way of specifying OFFSET = IN AFTER and OFFSET = OUT BEFORE >> from the constraints editor (Alliance 3.1i)? I would rather have the >> tool do the arithmetic (clock cycle isn't fixed). >> >> ---- >> Keith >Article: 31022
Uh oh, does this leave Austin as the lone dissenter? "Nemo" <nemo@dtgnet.com> wrote in message news:3afa67dc.10129415@news.dtgnet.com... > I apologize to all those posting/reading the recent Shannon capacity thread. I > was 100% wrong in my statements about parity bits. Here is some background... > > There has been an on-going thread in this news group about Shannon capacity. > The original question was about the following equation: > > C = W*Log2(1-S/N) bps > > Does the caculated capacity C include parity bits of a coded channel? > > I now believe the answer is *no, it does not*. Throughout Shannon's paper, C > refers to the *information rate only*. The above equation shows the > relationship between the amount of error-free *information* throughput, > bandwidth and S/N. The information throughput does *not* include the added > bits due to whatever coding scheme is chosen. In the following typical system, > the above equation shows the limit to the total info in and out for a channel of > a given bandwidth and S/N. The challenge of the engineer is to design the > encode/decode and mod/demod functions so as to achieve this limit. > > info in -> encoding -> modulation -> channel -> demod -> decode -> info out > > Again, in my previous posts I mis-stated how "parity" bits are considered in the > above equation/system. I apologize for any confusion. > > Good Day to all. > > Nemo >Article: 31023
I cannot speak as to what Synplicity does or doesn't do. However, I ran into the same licensing type issue in this post. I didn't have to re-install my OS, or re-format my HD (on my PC). I don't remember exactly what I did to fix it, but I seem to recall it involved uninstalling and deleting synplify, then re-installing. I tried to find which file it was writing to so I could delete it, but I never was able to find it. However, after removing all of synplify (and maybe removing it from the registry as well - although I am not sure on this, but it wouldn't surprise me, since installers seem to leave that stuff lingering around often), things once again worked without TOO much pain... Tom Mike Treseler wrote: > Markus Sponsel wrote: > > > > Hi there, > > > > unfortunately (or thank god) synplify pro has a very heavy protection. We > > had the same problem in our company some time ago where a trainee > > manipulated the date 6 (!) month in the future to test another program. > > "Only" reformating the harddrive end putting the OS new to it wonn't work. > > it seems that the license manager writes the date somewhere to the > > bootsector. So the easiest way is to contact synplicity to get this problem > > solved. Otherwise you have to format your harddrive (also clean the > > bootsector, but be careful !! this may destroy your harddrive) and put the > > OS new to it and reinstall synplify pro. So we (the trainee) did and it > > worked again. Next time we will contact synplicity, because it was a pain to > > do the procedure. > > I find it hard to believe that a reputable vendor like Synplify would > write licenses stuff to my boot sector. Can anyone confirm or refute > this? > > -Mike Treseler > Fluke NetworksArticle: 31024
Markus Sponsel wrote:
>
> Hi there,
>
> unfortunately (or thank god) synplify pro has a very heavy protection. We
> had the same problem in our company some time ago where a trainee
> manipulated the date 6 (!) month in the future to test another program.
> "Only" reformating the harddrive end putting the OS new to it wonn't work.
> it seems that the license manager writes the date somewhere to the
> bootsector. So the easiest way is to contact synplicity to get this problem
> solved. Otherwise you have to format your harddrive (also clean the
> bootsector, but be careful !! this may destroy your harddrive) and put the
> OS new to it and reinstall synplify pro. So we (the trainee) did and it
> worked again. Next time we will contact synplicity, because it was a pain to
> do the procedure.
I find it hard to believe that a reputable vendor like Synplify would
write licenses stuff to my boot sector. Can anyone confirm or refute
this?
-Mike Treseler
Fluke Networks
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