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In article <3A6B1A54.97388C5C@t-online.de>, a.eckhardt@t-online.de wrote: > Greg Neff wrote: > > > I doubt that this is your problem, but I still would design to avoid > > bus contention. If you can't do it with a synchronous state machine, > > (...) > > Effectively, I do this synchoneously. The /enable/ input > is fed directly from a D-latch which is clocked by the mainclock. > Nevertheless I am concerned about different delays between > DATA1.OE-->off in Chip#1 and DATA2.OE-->on in Chip#2. > That problem remains the same, synchroneously or asynchroneously. > (snip) I meant that you would have multiple enable outputs from the state machine, with 1 clock period between one enable negating and the next enable asserting. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/Article: 28726
> I have checked with Insight Electronics and they seem to have a fair
number of chips in stock but many are larger than I need. I may end up
using an older Xilinx XC4000 or something (no block ram) and Insight
seems to have plenty of them.
XC4K is to expensive.
> Anyone having issues obtaining small number of parts?
Yes. Everytime. But it helps to insist.
Conversion with distributor last week:
Me: I need Spartan-II
Disti: We do not have any.
They will only be in production starting april 2001
Me: Xilinx claims to have sold 1M parts in Oktober.
But I only need sample quatities anyway.
Disit: You usually do not get samples from Xilinx.
Me: I received 2 samples six month ago, I just need some more.
Disit: In that case I might be able to find some for you.
I then got 24 of these non existing Spartan-II, and they are marked C,
not CES.
The samples I only mentioned, because a xilinx FAE scanned the database
of the distributor and told me how many there are in stock. The
distributor insisted that there would be none, but gave up after a
overseas branch of the same disti confirmed the information.
The motto is: Just call again.
Kolja
Sent via Deja.com
http://www.deja.com/
Article: 28727Have a look at bresenhams line drawing algorithm. It solves the problem of counting n steps in m clock cycles with the best possible error and affordable hardware. e.g. if n and m are x bits, you need 2x LUTs CU, Kolja Sent via Deja.com http://www.deja.com/Article: 28728
Hi! From an Auction I got a box with 720 parts XC4013XL for $360. (Nice price, isn't it?) I can design for them with the university tools, but I would like to work with them at home, too. But Webpack ISE can only handle XC4010XL parts. Is there a way to obtain the incremental additional license for just this one part for a reasonable price? Kolja Sent via Deja.com http://www.deja.com/Article: 28729
Kolja, Page 338 in the Virtex II handbook (datasheet) details stand alone master select map with no cpld (just the flash memory, and the 2v part). The 2V40 will be in that range, in similar large quantities in about a year from now. As Peter mentioned, they just came out of the oven, so availability is still yet to be determined. The good news about the 2V40 is that it is a tiny die, so even in the first phases of production there is yield. Of course, Spartan II pricing will not be standing still, either. And I think the parts availability in December 2001 is not valid. I just checked the internal website, and that is not what I am seeing. Go back to your distributor and check on the dates again. Austin kolja@prowokulta.org wrote: > peter.alfke@xilinx.com wrote: > > Rick Collins wrote: > > > Anyone know of the > > > expected availability and price of a low end VirtexII? > > I will check prices and availability, obviously I personally encounter > no > > problem in that regard :-) > > Hmm. Low end parts. I was just told, by insight/memec germany, that > XC2S30 and XC2S15 are scheduled to be available December 2001. > So, a XC2V40 will be available earlier than that? At a similar price? > (less than $10) > > Also, what happend to master parallel mode? I would like to get rid > of the CPLD to read my FlashROM. > It's a little anyoing to almost double the FPGA price due to the > configuration ROM circuitry. > > Kolja Sulimma > > Sent via Deja.com > http://www.deja.com/Article: 28730
Greg Neff wrote: > I meant that you would have multiple enable outputs from the state > machine, with 1 clock period between one enable negating and the next > enable asserting. Oh, yes, that would make life much easier. But the timing is too tight for that; a complete data transfer has to be performed within a single clock period (33ns), followed by a data transfer from the other chip. -- Ralf A. Eckhardt a.eckhardt@t-online.deArticle: 28731
Search for a file called glbl.v in your xilinx folder and compile that. Then when you laod your design, include glbl in the load. I don't use verilog too much these days so I don't remember the syntax something like vlog glbl.v vsim work glbl top of course with any other switches and what not which I don't remember right now. If you still have trouble I can look up that syntax. Chris Utku Ozcan wrote: > Can I simulate a Verilog model of a RAMB4_S8_S8 element of > Virtex-E in a VHDL testbench? Not succeeded in that yet. > > RAMB4_S8_S8 is in $XILINX/verilog/src/unisims and this Verilog > code requires $XILINX/verilog/src/glbl.v to be compiled correctly. > > In typical Verilog testbench following must be done: > > glbl my_glbl (); > > In VHDL, its equivalent I can figure out would be: > > my_glbl : glbl; > > But when I choose "Design->Load Design..." and architecture > of VHDL testbench, Modelsim tells me that it cannot resolve > glbl in glbl.GSR assignment in RAMB4_S8_S8 element, although > I had compiled it into work library. > > The reason why I have use Verilog models of Xilinx macros instantiated > in VHDL testbench is that there are plenty of VHDL codes which call > Xilinx macros. > > VHDL models can be used by using: > > LIBRARY UNISIM; > USE UNISIM.all; > > ... which are not typed in original VHDL codes. But if I do it, then > Synplify will be angry with that, because it will try to compile > VHDL simulation models of Xilinx macros, which is nonsense. > > Is it possible to use LIBRARY and USE constructs with GENERATE?: > > IF SIMULATION=TRUE GENERATE > LIBRARY UNISIM; > USE UNISIM.all; > END IF; > > UtkuArticle: 28732
Hello Pawel, Look into http://www.optimagic.com/. The site is not updated since last few months though. Ashok Pawel wrote: > Hi, > Is there any on the Web site with a table or chart of "FPGA market > shares" - for free? > And how does it change during last years? > I've looked for, but I didn't find them, except "for registered people". > Thanks, > Pawel > -- > Pawel Tomaszewicz > Warsaw University of Technology > 00-665 Warsaw, Nowowiejska 15/19, Poland > > Sent via Deja.com > http://www.deja.com/Article: 28733
Kuldeep, kkdeep@my-deja.com wrote: > i have synthesized a design using synopsys fpga compiler II targeted at > xilinx XC4000 family. i want to know > 1. what placelment and routing tool i have to use to complete my design Xilinx tools - Alliance series probably would be the best choice. > > 2. what are the different optins available? > 3.is there any evaluation version avalable of these tools. Check with the Xilinx sales rep. in your area. > > 4.i have done the functional simulation at gate level by exporting VHDL > netlist? is there any way to simulate the timing before P & R. > Yes. > > thankx in anticipation > --kuldeep > > Sent via Deja.com > http://www.deja.com/Article: 28734
Dan wrote: > Is it possible to directly drive/receive a IEEE1394 firewire bus from the > LVDS outputs of a Xilinx FPGA ? > > Also, where is a good place to learn more about the firewire standard ? > > Sincerely > Daniel DeConinck > High Res Technologies, Inc. I don`t think that you can drive an IEEE1394 bus directly from the outputs of of a Xilinx FPGA. The IEEE1394 bus have three protocol layers. Two of these layers are implemented in the Link Layer Controller and the Physical Layer Controller. The Link Layer you can get as core from Xilinx. The Physical Layer you can get at Texas Instruments or Philips Semiconductor or so. If you will get information about IEEE1394 you can contact the page www.1394ta.org. There are a lot of links about this theme and also links where you can get specifictions about the bus. There is also a book: Don Anderson, FireWire System Architecture Second Edition, Addison Wesley Christoph HauzenederArticle: 28735
Austin, I assume you mean fg456? As it turns out, the Spartan II parts are STILL not available, so I have to use the Virtex parts which are $250 more each for the same basic part. I won't get into how ticked about that I am here... Thanks, Austin "Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3A6C5F9E.F8D8C929@xilinx.com... > Austin, > > fg256 is die facing up. > > there is no "cavity" per se. > > there is a cap over the die and bondwires to protect them. > > the fg256 is a 4-layer laminate package (little pcb) > > Austin > > Austin Franklin wrote: > > > It appears that the FG456 parts are cavity UP, but I want to make sure > > before doing my pinouts... > > > > The floorplanner gives the low number, low letter in the upper left. The > > FPGA Editor gives the low number, low letter in the upper left. The package > > drawing shows low number, low letter in the upper left (top view of > > package). That to me, means this is a cavity up part. > > > > The BG352 is a cavity down part...since the floorplanner gives the low > > number low letter in the in the upper RIGHT . The FPGA Editor gives the low > > number, low letter in the upper RIGHT. The package drawing shows the low > > number, low letter in the upper left (top view of package). That, to me, > > means this is a cavity DOWN part...since the die has to be flipped to line > > up the die pins with the package pins. > > > > Both the FPGA Editor and the Floorplanner are both 'die' view, it would > > appear. When doing floorplanning, at least for me, I would prefer the > > Floorplanner be a TOP view (or give you the option of die view or top view), > > so I can lay my chip out without having to flip everything over to really > > see how it lines up with the outside world... > > > > I REALLY wish they had a chart that showed the orientation of the die in > > each package...and I've mentioned this to them many a time. > > > > Any comments? >Article: 28736
In article <wkofx19fkq.fsf@geriatrix.circlesXXXXXquared.com>, jms@geriatrix.circlesXXXXXquared.com wrote: > I seem to be having difficulty finding an online supplier for one off > quantities of Xilinx FPGA/CPLDs in the UK. Specifically Spartans. And > preferebly at £few like their press release implies ! > > I've found are the XC95xxx on RS and that's about it. RS/Electromail stock the smaller Spartan devices, also. Insight-Memec don't mind supplying small quantities. I also buy a lot off them for work, though. Leon -- Leon Heller, G1HSM Email: leon_heller@hotmail.com Tel: (Home) +44 1327 359058 (Work) +44 1327 357824 Work WWW: http://www.irisys.co.uk Personal WWW: http://www.geocities.com/SiliconValley/Code/1835 Sent via Deja.com http://www.deja.com/Article: 28737
Hi Austin, Austin Lesea wrote: > > Ray, > > Good points. For those who can take the time to hand place and route > and tweak, the fabric can be pipelined to take advantage of the > speed. > > The area penalty is large, however, as you note. > > If you can do sustained 18 X 18 multiplies at 300 MHz with the > multiplier/bram, how fast do you think you can make it go when you > hand tweak it in LUT's? How do you get it to run at 300 MHz? The data sheet only goes to a -5 speed grade, which gives 2.89 ns clock to Dout on the rams, and a 4.18 ns delay time through the multiplier. Do you have the timing specs for faster speed grades, and do you have the timing specs for the pipelined version of the multiplier? Regards, Allan. -- Allan Herriman mailto:allan_herriman.hates.spam@agilent.com Agilent Technologies Voice: +61 3 9210 5527 Advanced Networks Division Fax: +61 3 9210 5550 347 Burwood Highway Forest Hill 3131 AustraliaArticle: 28738
Austin, did I miss something here?? The data sheet has the multiplier delay at 4+ ns and the clock to out of the BRAM another 2.9 ns or so. Without even considering routing, this puts you under 150 MHz in a -5 part. What are the numbers for the pipelined multiplier that we can't get at through the software or data sheet? With very careful design, the 150 MHz numbers can be reached with an 18 bit multiplier in the slowest virtex-4 parts (pipelined). I haven't had a chance to carefully evaluate the speed of the V2 fabric. I don't see the carry chain delays in the data sheet. Any idea how fast a 20 bit adder is assuming inputs from registers in an adjacent CLB? How much does fan-out slow down prop delays in V2 (virtex is pretty sensitive to loading)? Austin Lesea wrote: > > Ray, > > Good points. For those who can take the time to hand place and route and tweak, > the fabric can be pipelined to take advantage of the speed. > > The area penalty is large, however, as you note. > > If you can do sustained 18 X 18 multiplies at 300 MHz with the multiplier/bram, how > fast do you think you can make it go when you hand tweak it in LUT's? > > Austin > > Ray Andraka wrote: > > > Austin Lesea wrote: > > > > > > Allan, > > > > > > There is a register before the last partial product accumulator that can be > > > used to make the multiplier synchonous, and aid in pipelining it and getting > > > much higher speed from it. > > > > > > Unfortunately, software does not support this feature initially. (I know, I > > > know...but we got almost everything else in and working so don't be too > > > unhappy). If this is a requirement initially, I am sure we can work > > > something out (e.g. a core or something). > > > > > > The idea behind the multiplieres is that they are parked next to the bram's > > > so FIR filters, FFT's, etc are easy to implement at incredible clock rates. > > ^^^^^^^^^^ > > > > Hmmm... Those multipliers coupled with the BRAM look like the *SLOWEST* part of > > the > > VirtexII architecture, especially if we don't have access to the multiplier's > > pipeline > > registers. I think we can already match the performance for FIRs and FFTs > > in the Virtex architecture, perhaps even in the slower speed grades, granted at > > a > > higher area cost and using techinques that may not be obvious to the software > > DSP guy. > > For example, Andraka Consulting is now offering a 16 point fft core for virtex > > which > > will run at clock/sample rates of better than 140 MS/s in the slow virtex-4 > > parts. Looks like > > that is already faster than you can make the multipliers in V2 go. Go to a > > VirtexE-8, and the > > speed advantage of not using the multipliers is substantial. > > > > > > > > This is all part of the Xtreme DSP initiative that is rolling in to town. > > > > > > With all of those 18X18 multipliers, BRAM's, and gates, these things blow > > > the doors of any DSP out there by a factor of about 80 times faster. > > > > > > Austin > > > > > > Allan Herriman wrote: > > > > > > > Hi Peter, > > > > > > > > Can you please let me know if there's an option to allow the multipliers > > > > to be clocked? The picture in the datasheet makes it look like the > > > > multiplier is a purely combinatorial function of the inputs. The timing > > > > information supports this. > > > > > > > > I am concerned that the relatively slow clock to output delay of the > > > > block rams coupled with the multiplier delay will limit the clock speed > > > > to about 100MHz in filter applications. > > > > > > > > Thanks, > > > > Allan. > > > > > > > > Peter Alfke wrote: > > > > > > > > > > Ray, this may be the rare case where your long ( and distinguished ! > > > > > ) experience misleads you. > > > > > In the 13 years I have been at Xilinx, I have never seen us as well > > > > > prepared for the introduction of a new family, as we are today with > > > > > Virtex-II. > > > > > We have had software since last October, silicon since late > > > > > November, and have been testing it furiously ever since. We finished > > > > > writing a 536-page Virtex-II Handbook in December, and shipped many > > > > > thousands of printed copies in early January. We have had extensive > > > > > training for our FAEs last fall, and we are putting together the > > > > > slides for a public seminar right now. > > > > > Highest on my list of exciting features is the Digitally Controlled > > > > > Impedance, which effectively puts the series termination resistor > > > > > right into the output driver, or the parallel termination right into > > > > > the input buffer ( all optionally of course). It will be a gods-end > > > > > for people putting >500-pin packages on a pc-board, not having to > > > > > bother with resistor packs... > > > > > Hundreds of 18 x 18 multipliers (<4ns) are nice, as are 16 global > > > > > clocks in all devices, each with an input mux that can glitch-free > > > > > select between two sources. Ripple carry delay is 45 ps per bit, a > > > > > 24-bit synchronous counter runs at 300 MHz, etc. > > > > > Exciting stuff. As I mentioned,earlier, I am working on a 1 GHz > > > > > frequency counter, on a 200 MHz asynchronous FIFO, and on > > > > > metastability testing. > > > > > > > > > > Sorry for the blatant propaganda. Got carried away by my enthusiasm. > > > > > > > > > > I had been impatiently waiting for the Ides of January, for a long > > > > > time ! > > > > > > > > > > Peter Alfke, Xilinx Applications > > > > > ===================================== > > > > > Ray Andraka wrote: > > > > > > > > > > > erika_uk@my-deja.com wrote: > > > > > > > > > > > > > > Hi, > > > > > > > > > > > > > > Does the tool handle it well ? > > > > > > > > > > > > Like any other new architecture, I suspect it will take a while > > > > > > for the tools to catch up to the new silicon. In the past, > > > > > > it has taken about a year after the introduction of the > > > > > > silicon before the tools were close to ready for prime time. > > > > > > Macro libraries lag even further behind. In the case of Virtex, > > > > > > I didn't start recommending them for customers until a little > > > > > > over a year ago...because of tools issues. > > > > > > > > > > > > > > > > > > > > --Erika > > > > > > > In article <979567585.218715@news2.cybercity.dk>, > > > > > > > "Rune Baeverrud" <fpga@no.spam.iname.com> wrote: > > > > > > > > Hello, > > > > > > > > > > > > > > > > Xilinx Virtex-II has now been officially announced. > > > > > > > > > > > > > > > > Check out the press release: > > > > > > > > http://www.xilinx.com/prs_rls/vtx2ship.htm > > > > > > > > > > > > > > > > and the Virtex-II Handbook: > > > > > > > > http://www.xilinx.com/products/virtex/handbook/index.htm > > > > > > > > > > > > > > > > Some highlights are: > > > > > > > > - digitally controlled impedances for input and output pins > > > > > > > > - new resources for clock management and clock synthesis > > > > > > > > - digital spread spectrum clocking > > > > > > > > - encrypted bitstreams > > > > > > > > - dedicated multipliers > > > > > > > > > > > > > > > > Go and see for yourself! > > > > > > > > > > > > > > > > Regards, > > > > > > > > Rune Baeverrud > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Sent via Deja.com > > > > > > > http://www.deja.com/ > > > > > > > > > > > > -- > > > > > > -Ray Andraka, P.E. > > > > > > President, the Andraka Consulting Group, Inc. > > > > > > 401/884-7930 Fax 401/884-7950 > > > > > > email ray@andraka.com > > > > > > http://www.andraka.com or http://www.fpga-guru.com > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com or http://www.fpga-guru.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28739
Anyone know why Xilinx isn't putting the recent copies of their XCell magazine online? They've only got up through the 2nd Qtr 2000, and that's the way it has been since around October. I can't imagine why they wouldn't want the extra exposure by having it available online. (I have an article on digital downconversion in Q4 I'd like to link to, several people have asked). -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28740
The Atmel FPGAs are well suited to partial reconfiguration, this is one of thier stong suits. These can be reconfigured in rectangular "windows" of arbitrary size, which makes them a bit more friendly than devices that are configured in vertical slices (virtex). Still, partial configuration carries with it a large can of worms, which nobody's tools adequately address. Some of these problems are especially acute when the reconfiguration is executed while the system clock is running. I know the Atmel parts can handle that, I did such a design back in '95 on the AT6K line (see the dynamic hardware video processor paper on my website). Yes I ran across a number of the pitfalls in that design. Atmel has had a tools for replacing constants for better than 5 years now. It would be nice if they carried the tools a little further. Ulf Samuelsson wrote: > > The AT6000 has a tool which supports automatically changing constants. > This is used to update filters. > It is hard to reconfigure on the fly, and there are some research/development > going on with some customers. > So far, info is only available under NDA. > > -- > Best Regards > Ulf at atmel dot com > These comment are intended to be my own personal view > and may or may not be shared by my Employer Atmel Sweden. > > <pawel5732@my-deja.com> skrev i meddelandet news:949ph3$kbq$1@nnrp1.deja.com... > : Hi, > : What FPGAs do support a partial reconfiguration? > : What FPGAs can be reconfigured "on-the-fly"? > : Is this possible to use this feature with a tool? > : Thank you, > : Pawel > : > : > : Sent via Deja.com > : http://www.deja.com/ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28741
Chris Dunlap wrote: > Search for a file called glbl.v in your xilinx folder and compile that. > Then when you laod your design, include glbl in the load. > > I don't use verilog too much these days so I don't remember the syntax > something like > vlog glbl.v > vsim work glbl top > > of course with any other switches and what not which I don't remember > right now. > > If you still have trouble I can look up that syntax. > > Chris Chris, in my mail I had stated that glbl.v had already been compiled. Now I have learned that it is impossible to use the VHDL equivalent of the following Verilog construct which is necessary for verification with Xilinx macros: glbl global (); ...because in Modelsim (the simulator I'm using, which I have forgotten to mention it) it is impossible to instantiate Verilog models, which do not have terminals, within VHDL code. The only solution I have found is to modify the Verilog models of the macros, which lets me get rid of using glbl.v. Following example is for RAMB4_* elements in Xilinx UNISIM library: tri0 GSR = RSTA | RSTB; /* instead of tri0 GSR = glbl.GSR ; */ This was a Modelsim-related problem. I'm still waiting for a concise answer for my previous question about Modelsim in news:comp.lang.verilog!! UtkuArticle: 28742
Hi, Can you help me ? I search a book or a note on different multiplier architecture !!! -- EricArticle: 28743
Tech support has confirmed an annoying little bug in the mapper in the v10.0 release of MAX+2 (PC). If you have a single register driving multiple outputs, regardless of the timing goals or constraints which have been set, the mapper will replicate the single register N times for N outputs. The replicated registesr will be mapped to "internal" LEs (CLBs for the Xilinx weenies), rather than the IO cells. I've experienced this on ACEX1K designs. I haven't taken the time to run regression tests across SW version, FPGA families, etc. So... consider this a "heads up" for all you Altera weenies out there. Tech support indicated that the next "major release" would have a fix. -- Bob Elkind, eteam@aracnet.comArticle: 28744
The BGA's can be used by "small guys" too. We use for soldering BGAs to proto boards a hand-made thermal isolated box, hot-air gun and thermometer. The problems are positioning the chip before soldering and checking the result after soldering (the factories use X-rays for checking the proto series). Jaan. >No chance. Xilinx chose to drop the flat packs, so the small guys will have to face the task of mounting those terrible BGA's...Article: 28745
Austin Lesea <austin.lesea@xilinx.com> wrote: > Kolja, > > Page 338 in the Virtex II handbook (datasheet) details stand alone master > select map with no cpld (just the flash memory, and the 2v part). That shows a Xilinx PROM, that does not need addresses supplied to it. These parts reach the endcustomers at very high prices. (More than a Spartan-II) You know, the same distributors that give wrong release dates :-) With the XC4K parts you could use 28F010 or similar. Ironically with the cost for a XC4K I coul well afford a Xilinx PROM :-) CU, Kolja > The 2V40 will be in that range, in similar large quantities in about a year > from now. As Peter mentioned, they just came out of the oven, so > availability is still yet to be determined. The good news about the 2V40 is > that it is a tiny die, so even in the first phases of production there is > yield. > > Of course, Spartan II pricing will not be standing still, either. > > And I think the parts availability in December 2001 is not valid. I just > checked the internal website, and that is not what I am seeing. Go back to > your distributor and check on the dates again. > > Austin Sent via Deja.com http://www.deja.com/Article: 28746
Austin Lesea <austin.lesea@xilinx.com> wrote: > Kolja, > > Page 338 in the Virtex II handbook (datasheet) details stand alone master > select map with no cpld (just the flash memory, and the 2v part). Just to give you an example on why I will not use XC18V02: Insight/Memec Germany sells me small quantities of XC2S200 for DEM 60,- (about $28) XC18V02 for DEM 68,- (about $32) It does not make much sense to double the price of the PFGA for configuration. A XC9036XL plus AM28F040 kosts me DEM 15,- ($7) and is a factor of 5 below the Xilinx PROM. It costs more board space, though. You really should start building FLASH based FPGAs. Actel claims they take up less silicon area, anyway. Kolja Sent via Deja.com http://www.deja.com/Article: 28747
Does anybody know, where I can find documentation about using hard macros created with the FPGA editor of Xilinx foundation software a) In a schematic b) In a VHDL design Thanx, Kolja Sent via Deja.com http://www.deja.com/Article: 28748
Any comments about Atmel's starter kit ATSTK40? Is it worth it? Thanks, FilipArticle: 28749
Hi, all. Because of Xilinx' inspired (not!) canning of the erstwhile Philips 5 volt Coolrunner CPLDs, I've ported a design to an Atmel ATF1502AS. This works well. The production people previously used a Xilinx Parallel Cable III to program the Coolrunner. Atmel's JTAG ISP software uses their own cable or an Altera Byteblaster. For the sake of the production people I would prefer to continue to use the Xilinx cable. Is anyone aware of any software out there to use the Xilinx cable for non-Xilinx JTAG programming? My apologies for crossposting. Thanks in advance, Richard ------------Richard Dungan------------- Radix Electronic Designs, Orpington, UK richardATradix-designDOTcoDOTuk ---------------------------------------
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