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I find it much better to use signals instead of variables in synthesizable code. There are more pitfalls to beware of with variables. Using variables in something other than a test bench is usually an indication that you need to re-think your approach to this design. #ROBERTUS WAHENDRO ADI# <PH671019@ntu.edu.sg> wrote in message news:0CF260C495FED111A6610000F866308D15F993E5@mail3.ntu.edu.sg... > Hi all, > Can variable be shared between one process to another? > if yes, How to do it? > > tia > Robertus Wahendro Adi > > >Article: 28776
But why are the Xilinx FlashROM that expensive compared to competitive standard FLASHs of the same size? (By a factor of 8) Or is this just some small quantity distributor effect? From my VLSI knowledge the extra cost for the address counter should be more than canceled by the reduced pin count. Also, if your only form of access is a configuration stream you can very easily work with defekt blocks like in the extremly cheap NAND-Flash parts. This will give you a yield close to 100% I just saw a 1Gb NAND Flash listet for $200 end customer price. Also: NAND Flashs use only 12 Pins for theire interface. A compatible master parallel mode would be easy to implement in your FPGAs. Kolja In article <3A6E1379.1A2451FA@xilinx.com>, Austin Lesea <austin.lesea@xilinx.com> wrote: > Lasse, > > Flash technology tends to lag about two years behind the standard CMOS > process. Right now, 0.18u flash is just in the first process development > stage, not sampling yet. > > We are actively examining all of the many ways one could provide > configurations to our FPGA's. For large farms of our new parts, Flash > Memory Cards may be the best answer for price/performance. > > Austin > > Lasse Langwadt Christensen wrote: > > > kolja@prowokulta.org wrote: > > > > > > Austin Lesea <austin.lesea@xilinx.com> wrote: > > > > Kolja, > > > > > > > > Page 338 in the Virtex II handbook (datasheet) details stand alone > > > master > > > > select map with no cpld (just the flash memory, and the 2v part). > > > > > > Just to give you an example on why I will not use XC18V02: > > > > > > Insight/Memec Germany sells me small quantities of > > > > > > XC2S200 for DEM 60,- (about $28) > > > XC18V02 for DEM 68,- (about $32) > > > > > > It does not make much sense to double the price of the PFGA for > > > configuration. > > > > > > A XC9036XL plus AM28F040 kosts me DEM 15,- ($7) and is a factor of 5 > > > below the Xilinx PROM. It costs more board space, though. > > > > > > You really should start building FLASH based FPGAs. Actel claims they > > > take up less silicon area, anyway. > > > > I doubt it's possible to get flash in 0.15/0.12 um as use d by the > > Virtex-II > > > > -- Lasse > > (+)--------------------------(+) > > | Lasse Langwadt Christensen | > > | Aalborg, Denmark | > > (+)--------------------------(+) > > Sent via Deja.com http://www.deja.com/Article: 28777
> The easiest thing to do is to add a directive to your code. For > Synplify, do the following: > > -- synthesis translate_off > library unisim; > use unisim.all; > -- synthesis translate_on > > Voila. The synthesis tool will ignore the library clause and do the > right thing, and the simulator will use the library and do the right > thing. Yes, Andy, this is one of the best workarounds. But there are hundreds of VHDL codes, which we wouldn't touch them, if possible. Modification of 4 Verilog models of Xilinx macros was much easier than to update hundreds of VHDL code according to the method above. UtkuArticle: 28778
Hello Newsgroup! How can I implement a real bidirectional route-through wire (no direction pin, e.g. a databus) in an Actel 54SX? Is it allowed to interconnect an INBUF and OUTBUF as work-around? Greetings, Ingo Purnhagen _______________________________ Ingo Purnhagen (Dipl.-Ing.) OHB-System GmbH Abt. Hardware Universitaetsallee 27-29 28359 Bremen, Germany Fon: +49 421 2020 702 Fax: +49 421 2020 610 mailto:XXXpurnhagen@ohb-system.de http://www.ohb-system.de XXX to be removedArticle: 28779
Dear Allan and Ray, I'm very excited about the dedicated 18x18 multipliers in Virtex-II but I know it's going to be a while before we get used to what we can actually use them for. Regarding performance, the key point to notice is that they will be the fastest combinatorial multipliers of that size which you can have. A fully pipelined multiplier in CLBs is going to be faster, and I for one am pleased that the MULT_AND gate still has a purpose :-) The higher performance of combinatorial multiplier is going to be a lovely feature to have when used in the more 'processing' types of DSP. In these cases, the algorithms are not so wonderfully data-path as an FIR filter and decisions will often be made. The clearing of a pipeline is horrible to 'think' about and brings the overall performance of the algorithm down below a slow combinatorial process (of which the multiplier may only be part of it). Certainly all those people who have enjoyed building their own micro-processors in FPGAs (me included) will love the single cycle multiplier to build into their ALU at no impact on CLB area. The other observation is the 18-bit width supported by the block RAM and multiplier in combination. The whole point about most of our CLB based DSP has been to reduce the bits to a minumum. It has been very few times that I've implemented 16 bit arithmetic. Now with 18-bit support it makes it much easier to address the world associated with 16-bit fixed point algorithms normally applied to DSP processors. It is highly likely that most of these algorithms don't actually need 16 bits either, but they can often be so invoved that no ones wants to go and work out the exact requirements. The CLBs will still provide the simple functions such as accumulation of any bit-width and ability to select a scaled result. The MAC becomes a very simple but useful building block and all at the cost of a few CLBs for the accumulator and control. I'm excited because this is a style that is about multi-cyle processing, and since the memory is 4x deeper than in Virtex-E, then I will be looking at lots of cycles. Even if I settle for 100MHz clock rate on my MAC, then to scan through 1024 words (2 operands at a time) in the associated block RAM will still mean I can sample at about 200KHz which a great for control loops and lots of channels of 8KHz communications audio. The smallest Virtex-II gives me 400Mega-MAC of processing power at 100MHz clock rate. For the lower sample rate applicatons such as comms audio (8KHz) it is not lack of processing power, but how to to keep feeding enough to the multipliers. Time to look at all the lovely ways you can communicate with external RAM!! Your sincerely, Ken Chapman - Xilinx Applications (UK)Article: 28780
Hi, I'm using Xilinx Alliance 3.3 SP6 on Windows 2000. When I try to program with Hardwaredebugger the program crashes as soon as the cable is detected. When I remove the cable the program starts normally. Does anybody know why??? -- Regards Jens Popp mailto:popp@rs.uni-siegen.deArticle: 28781
Jim Watts wrote: > > The 4k and Spartan placer was good at placing pins. For Virtex and WHAT???? The 4K/Spartan automatic pin placement is horrible, and the relatively sparse routing resources in these devices make it critical to get the placement right. It does OK for a one time through the tools design, but if you are iterating the design (and who doesn't) and the chip is reasonably utilized in terms of density and performance, you will get routing and/or timing problems on an iterated design.... guaranteed. The VIrtex and SpartanII are better in this regard, thanks to the Versa-ring which gives more plentiful routing around the chip's periphery. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28782
If the translate_on off is too much to add, you could remap the unisim library to the synplicity virtex library in synplicity. Utku Ozcan wrote: > > > The easiest thing to do is to add a directive to your code. For > > Synplify, do the following: > > > > -- synthesis translate_off > > library unisim; > > use unisim.all; > > -- synthesis translate_on > > > > Voila. The synthesis tool will ignore the library clause and do the > > right thing, and the simulator will use the library and do the right > > thing. > > Yes, Andy, this is one of the best workarounds. But there are > hundreds of VHDL codes, which we wouldn't touch them, > if possible. > > Modification of 4 Verilog models of Xilinx macros was much > easier than to update hundreds of VHDL code according > to the method above. > > Utku -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28783
Ken Chapman wrote: > > Dear Allan and Ray, > > I'm very excited about the dedicated 18x18 multipliers in Virtex-II but I know it's > going to be a while before we get used to what we can actually use them for. > > Regarding performance, the key point to notice is that they will be the fastest > combinatorial multipliers of that size which you can have. A fully pipelined > multiplier in CLBs is going to be faster, and I for one am pleased that the Agreed. Where I see the most potential for the multipliers is in tight feedback loops that cannot be heavily pipelined. I'm not real hot on building DSP microprocessors in the FPGA, as I think that misses the point and in general has put people on the wrong track for hardware DSP. > > The other observation is the 18-bit width supported by the block RAM and multiplier > in combination. The whole point about most of our CLB based DSP has been to reduce > the bits to a minumum. It has been very few times that I've implemented 16 bit > arithmetic. Now with 18-bit support it makes it much easier to address the world > associated with 16-bit fixed point algorithms normally applied to DSP processors. > It is highly likely that most of these algorithms don't actually need 16 bits > either, but they can often be so invoved that no ones wants to go and work out the > exact requirements. The CLBs will still provide the simple functions such as > accumulation of any bit-width and ability to select a scaled result. Actually, I see quite a bit of 16 to 20 bit and wider data in the apps I've been dealing with, and this is usually at quite high sample rates. The multipliers are a nice feature, and as you point out it will take us all a little time to get used to using them. I don't think they'll be quite as invaluable as the SRL16 is to me (which also took some time to fully appreciate) because their speeds are so much slower than what the fabric is capable of. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28784
Hi Folks, We have a student project in which it is required to implement some image processing operations (e.g. filtering) on an FPGA based board connected to a PC. The aim is to assess the suitability of FPGAs in Desktop publishing. We still have to decide on the FPGA board to be used. We want an FPGA board with a DMA module on board to speed up data transfer from host memory to on-board memory. Could you please advice us on a commercial FPGA board to purchase?? Cheers, PS. Our purchase budget is 3000$ Sent via Deja.com http://www.deja.com/Article: 28785
Don't know if its bad form to answer ones own posting but here goes. It turned out not to be the length of the registers but the number of combinatorial variables in equations. I had two equations each summing up 32 bits in a register. After I paired the register bits with parenthesis, XST had no problems finishing. Jerry English wrote: > Greetings, > > I have a verilog module that FPGA Express and Ambit can > > compile just fine. When I use XST in Foundation 3.3.06i > > XST hangs at 50%. I have let it run over night with no > > results. I am targeting Spartan II 2S200. While I muck > > about the code trying to get XST to finish the compile > > I thought I would ask if anybody has had a similar experience > > with XST and what they did to fix it. I'm thinking that some > > of the register lengths may be a bit much for the tool to handle. > > regards > > JerryArticle: 28786
The Virtex II encryption requires a battery to always be on. Xilinx says the current is <100nA and the battery will last as long as the battery's shelf life. They do not discuss battery technologies of choice. I only know how to change the batteries on my baby's toys. What would a good battery technology be ? What would the shelf life be ? What is your opinion of this battery method ? I have opened a case with Xilinx. Their support could not find more information at this time. Sincerely Daniel DeConinck High Res Technologies, Inc.Article: 28787
Ray Andraka wrote: > If the translate_on off is too much to add, you could remap the unisim > library to the synplicity virtex library in synplicity. As I stated in my first posting in this thread, neither LIBRARY UNISIM; USE UNISIM.all; nor --synthesis translate_on LIBRARY UNISIM; USE UNISIM.all; --synthesis translate_off "or nor" any combination of both existed in VHDL codes. That means, VHDL codes have been designed for synthesis, but not for any kind of simulation. In order to get rid of any update of any combination of both above, because there are hundreds of VHDL codes, we have updated _only_ the Verilog macros which are called from within $XILINX/verilog/src/unisims to another directory. UtkuArticle: 28788
I've just got through to a Xilinx rep on my sixth phone call to him. I
thought he was going to be really helpful, given that he had bothered
to send two copies of an email with his phone number. Instead he just
mentioned Insight and Avnet which he could have put in his email. Twat* !
Maybe I'll look towards Europe for a supplier.
Jon
* No offence to goldfish intended.
Article: 28789"Dan" <daniel.deconinck@sympatico.ca> wrote in message news:e0Db6.116140$JT5.4096438@news20.bellglobal.com... > The Virtex II encryption requires a battery to always be on. > > Xilinx says the current is <100nA and the battery will last as long as the > battery's shelf life. > > They do not discuss battery technologies of choice. I only know how to > change the batteries on my baby's toys. > > What would a good battery technology be ? What would the shelf life be ? > > What is your opinion of this battery method ? > > I have opened a case with Xilinx. Their support could not find more > information at this time. > > Sincerely > Daniel DeConinck > High Res Technologies, Inc. You may be surprised to find that the companies that makes batteries for your children's toys also make them for embedded applications. Check out Duracell's web site, for one. Another possibility is a so-called "super cap". It's basically a very large capacitor which can provide power for several hours (maybe days, depends on the current drawn). I forget who makes them. It comes down to your application, really. If you're designing something that's almost always on, and just needs to survive short power outages, I suggest the capacitor. Otherwise, a regular or re-chargeable battery may be better. For more information, look at the app notes for real-time clocks. They also need battery backup. A good example is the MM58274C from National Semiconductor (http://www.national.com/an/AN/AN-365.pdf). Cheers, JamieArticle: 28790
"M.Sivanandan" wrote: > I have instantiated the startup virtex block in one of my top level design, which has some other components instantiated. I have connected the toplevel reset to the startup virtex blocks input. Now to what pin or signal should i connect the reset ports of other components instantiated in my toplevel? Please give me the solution. Thanks in advance The same signal you have connected to STARTUP. Reset signal goes both to STARTUP and to your reset in your HDL codes. UtkuArticle: 28791
"Jamie Sanderson" <jamie@nortelnetworks.com> writes:
> Another possibility is a so-called "super cap". It's basically a very large
> capacitor which can provide power for several hours (maybe days, depends on
> the current drawn). I forget who makes them.
Panasonic last time I looked.
Jon
Article: 28792Ray Andraka schrieb: > > You haven't compared the clock-to-Qs of the flip-flops and SRL16's have you? Ahhh, No. Whats the differnce?? (Iam to lasy to look at the data sheet ;-)) -- MFG FalkArticle: 28793
steve@sk-tech.com wrote: > > Hello all, > > I have a existing design that has been going through the design flow > just fine for months. All of a sudden the placer and router scores > went through the roof! To the point where my design won't compile. > When I look at my UCF file with the Constraint's Editor I see a tab at > the bottom called "Source Constraints". I click on that tab and look > at the contents in the window. I see several TIMESPEC statements that > I have not added and they are causing my design to not compile > properly. the TIMESPECs added were things like PADS to PADS and PADS > to FFS, etc. The values they are using are too fast. I do not know why > this started and how to get rid of them. Some things in the design are > not constrained and that is intended. It seems like the tools are > trying to force 100% coverage by added these TIMESPECs??? I have all > the most recent Service Patches installed. Any clues would be most > appreciated. You're using synthesis, right? If you tell your synthesis tool to forward-annotate its timing constraints, it puts those constraints into either a .ncf file (Synplify does this) or right into the .xnf file (which is what FPGA Express does). Note that when you start the Constraints Editor, it looks at those files. The easiest thing to do is to tell the synthesis tool not to forward-annotate constraints. Then you must delete the .ncf file and re-run the synthesis. You might also want to see what constraints your synthesis tool is using for its work. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 28794
Daniel Nilsson wrote: > > Hi. > I´have just got my jtag programmer functioning, and now I want to test > something simple with it. > I am completely new to programmable logic, so I need some info about how to > connect it... I guess I will need a global clock, but what else will I need? > All I want to do is get some led's blinking. My device is a xilinx XC9572 > PC44. You need a design to load into the part. -- ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 28795
Ray Andraka wrote: > > Jim Watts wrote: > > > > The 4k and Spartan placer was good at placing pins. For Virtex and > > WHAT???? The 4K/Spartan automatic pin placement is horrible, and the > relatively sparse routing resources in these devices make it critical > to get the placement right. It does OK for a one time through the > tools design, but if you are iterating the design (and who doesn't) and > the chip is reasonably utilized in terms of density and performance, > you will get routing and/or timing problems on an iterated design.... > guaranteed. I'm with Ray on this. My last 4KXLA designs were about 75-80% full (lotsa memories) and I never had any problems routing or meeting timing. And I'll add: board layout goes a whole lot smoother if you put some thought into your pinouts. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 28796
Jim Watts wrote: > > Advice: Switch to Xilinx Sometimes, that's just not possible. -- ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 28797
I am attempting to do a boundary scan test (generated via Corelis) on a chain that contains an Adaptec AIC-7899G SCSI host adapter IC. My test currently fails the infrastructure test, receiving all 1's. The 7899 is at the end of the chain. When I short out the TDI & TDO pins of the 7899, the rest of the chain responds correctly. At this point, I feel that the BSDL file I have for this device may be incorrect. Since I have had zero success getting any information from Adaptec, I was wondering if anyone has successfully tested this device and would be willing to share the BSDL file used for this. Thank you for your assistance. Regards, Bob Bernatchez Test Engineer Solectron Technology, Inc. Bobbernatchez@nospam.nc.slr.com Remove nospam to reply Sent via Deja.com http://www.deja.com/Article: 28798
As far as I know, you can only wire one IOPAD to a pin, but you can wire the IOPAD to an IBUF and multiple TBUF's.Article: 28799
Hi Jim, I design frame grabbers/ image processing boards using Xilinx FPGAs. What university are you at ? What is the name of the course ? my FPGA boards are at http://www.pixelsmart.com If I can help please let me know. What need is there for filtering a DTP bitmap ?? Sincerely Daniel DeConinck High Res Technologies, Inc.
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Compare FPGA features and resources
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