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I will tell you a philosofical dilemna, I'm an FPGA designer in Canada which is a descent peacefull, country. Why would I go to France I'm Tunisian, I do have and in your face a deep hate for this country. Athough I like the francophone culture, I have a deep hate/liking of this country culture. The United States, with the bloody george bush, and the people of the gulf war. I better stick in here in Montreal, and complain about the weather, It's better than France Racism, or USA war on the arabs. Sorry but you have to consider the human side along with the technical stuff, Yours Truly Fredj Le magnifique Sent via Deja.com http://www.deja.com/Article: 29076
Rick, OOPS. Sorry. Keep checking the web for our technote on the subject. Austin Rick Collins wrote: > Austin Lesea wrote: > > > > .... I can't watch while misleaading information is spread around: > > > > > > If you want to know what the 20KE PLL really does, measure it with > > other things happening in the part. > > > > [Image] > > > > This is what Altera doesn't want you to see. It is their "perfect" > ...snip... > > > > Austin > > Austin, > > Just a reminder. This is not a binary group. If you have an image to > post, it should be done with a link or a reference, not as part of the > message. > > My understanding is that if a lot of binaries get posted to a non-binary > newsgroup, it can result in the group being dropped from some servers. > Then there will be people don't get to read any of your posts! > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > URL http://www.arius.comArticle: 29077
Ed Ngai wrote: > > "Kevin J. McCann" wrote: > > I am an amateur circuit designer. It seems that the FPGA world may now be > > inexpensive enough for me to give it a try. Could you please recommend a > > book and board combo that would get me going. Although I have a good > > understanding of TTL style logic design, I have no experience with this > > more advanced stuff. > > Thanks, > > Kevin > > I've come across an older book "FPGA Workout, Beginning Exercises > w/ the Intel > FlexLogic FPGA", X Systems Engr. Software, 2608 Sweetgum dri., > Apex, N.C. 27502 > 1-800-549-XESS. I've heard they have a 2nd ed of this book ? Intel does FPGAs?Article: 29078
This is a multi-part message in MIME format. --------------9C6FB90EE09F67CCEC7EE387 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit In order to properly infer a bi-driectional I/O, three things need to be done. 1. An inout port needs to be declared 2. An input path needs to be described from the inout port 3. A tri-stated output path needs to be described to the same port. It seems number 3 trips most people up one way or another. In general, it is recommended to decribe all of these (especially the tristate) on the top-level file although is not always necessary if you are doing a standard top-down synthesis compile methodology. A small example can be found in the Synthesis and Simulation Guide, http://toolbox.xilinx.com/docsan/3_1i/docsan.htm, at http://toolbox.xilinx.com/docsan/3_1i/data/common/sim/chap04/sim04006.htm. Look at the "Inferring Bi-directional I/O" section. I know this is not the Virtex section of the book but this still applies to Virtex. -- Brian kkdeep@my-deja.com wrote: > I have a design which has some inout pins. it is finally targetted at XILINX, > virtex family. when ever i use I/O pads while synthesisng my chip in FPGA > Compiler II, the inout is not synthesised properly. The problem i have found > was it is placing buffers at the io pins which are unidirectional. so only > input is working while out put is not working. so plz tell me how to tell the > compiler that use bi-directional buffers. thanx in advance kuldeep > > Sent via Deja.com > http://www.deja.com/ --------------9C6FB90EE09F67CCEC7EE387 Content-Type: text/x-vcard; charset=us-ascii; name="brian.philofsky.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brian.philofsky.vcf" begin:vcard n:Philofsky;Brian tel;work:1-800-255-7778 x-mozilla-html:TRUE url:http://www.xilinx.com org:Xilinx, Inc.;Software Marketing adr:;;2300 55th Street;Boulder;CO;80301;USA version:2.1 email;internet:brianp@xilinx.com title:Sr. Technical Marketing Engineer fn:Brian Philofsky end:vcard --------------9C6FB90EE09F67CCEC7EE387--Article: 29079
This is a multi-part message in MIME format. --------------FC561AF1CF05D3CEB899AC2A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit You don't mention whether you are using VHDL or Verilog but I will take the educated guess that you are using VHDL. If you are using Verilog, the recomendations would be slightly different. For VHDL, there are at least three ways to go for this. 1. There is a model for the STARTUP block in the unisim library located at $XILINX/vhs/src/unisims however it does not contain any functionality. It will declare the block but does not do anything for you. You can point to the Unisim library and perform the simulation without the global reset functionality. 2. You can instantiate a STARTBUF and connect this too all register reset/presets in the design. This will allow you to functionally simulate the global reset. 3. You can run the EDIF file produced by Leoanrdo through NGDBUILD --> NGD2VHDL and use that structural netlist for simulation. You will need to point to the Simprim library for the structural components. If you go this way, the STARTUP block will be replaced by a ROC (Reset On Configuration) which will automatically handle the global reset for you upon invoking the simulation. Take a look at the Synthesis and Simulation Design Guide, http://toolbox.xilinx.com/docsan/3_1i/docsan.htm. Chapter 6 for more information on what I briefly explained above. Also if you are using Verilog, help for that language is documented there as well. I know I plug this book a lot but it answers a lot of peoples questions in the area. I suggest most all FPGA designers to at least glance through it for synthesis and simulation questions/problems. -- Brian Dr Daz wrote: > I've just changes synthesis tools from Synopsys to Leonardo and I'm > having a small problem with my post-synthesis simulation. Synthesising > to Xilinx XC4000XL the design uses a global reset therefore Leonardo > connects this input to the STARTUP block. However, when I come to > perform post-synthesis simulation of my design no simulation model > exists for the STARTUP block so I can not simulate a reset condition. > I'm sure that there must be a mechanism for working around this problem > but I can't seem to find any information on the problem. Anybody else > experienced this problem? Got a solution? > > Loenardo version 1999.1 > > Thanks for any help. > > Darrell. > > Sent via Deja.com > http://www.deja.com/ --------------FC561AF1CF05D3CEB899AC2A Content-Type: text/x-vcard; charset=us-ascii; name="brian.philofsky.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brian.philofsky.vcf" begin:vcard n:Philofsky;Brian tel;work:1-800-255-7778 x-mozilla-html:TRUE url:http://www.xilinx.com org:Xilinx, Inc.;Software Marketing adr:;;2300 55th Street;Boulder;CO;80301;USA version:2.1 email;internet:brianp@xilinx.com title:Sr. Technical Marketing Engineer fn:Brian Philofsky end:vcard --------------FC561AF1CF05D3CEB899AC2A--Article: 29080
This is a multi-part message in MIME format. --------------924DFFE3A5C9A8629F2D8BEC Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Intel did do Programmable Logic at one time as did AMD, Motorola and TI. Intel did have the FLASHlogic line in the early 90's but sold the line to Altera sometime in the mid-90's. Altera has since discontinued the line, http://www.altera.com/html/products/flash.html -- Brian Andy Peters wrote: > Ed Ngai wrote: > > > > "Kevin J. McCann" wrote: > > > I am an amateur circuit designer. It seems that the FPGA world may now be > > > inexpensive enough for me to give it a try. Could you please recommend a > > > book and board combo that would get me going. Although I have a good > > > understanding of TTL style logic design, I have no experience with this > > > more advanced stuff. > > > Thanks, > > > Kevin > > > > I've come across an older book "FPGA Workout, Beginning Exercises > > w/ the Intel > > FlexLogic FPGA", X Systems Engr. Software, 2608 Sweetgum dri., > > Apex, N.C. 27502 > > 1-800-549-XESS. I've heard they have a 2nd ed of this book ? > > Intel does FPGAs? --------------924DFFE3A5C9A8629F2D8BEC Content-Type: text/x-vcard; charset=us-ascii; name="brian.philofsky.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brian.philofsky.vcf" begin:vcard n:Philofsky;Brian tel;work:1-800-255-7778 x-mozilla-html:TRUE url:http://www.xilinx.com org:Xilinx, Inc.;Software Marketing adr:;;2300 55th Street;Boulder;CO;80301;USA version:2.1 email;internet:brianp@xilinx.com title:Sr. Technical Marketing Engineer fn:Brian Philofsky end:vcard --------------924DFFE3A5C9A8629F2D8BEC--Article: 29081
I think the RC1000-PP board originated from Celoxica Ltd (www.celoxica.com). They offer toolkits and support along with the board which has 4 32-bit banks of 2MB of ram. Andrew "Vincent Clerc" <vincent.clerc@horizon-tech.fr> wrote in message news:95mhbi$asm$1@front7.grolier.fr... > Dear Zhen, > > Horizon Technologies will soon have the solution you request for : > > Their PCI mother board supports a daughterboard which provide 4 SRAM Like > 64bit 512MByte memory banks connected to an APEX20k400. > This board will also have three 32bits input channels each capable of > 125MBytes/s sustained transfer rate for outside world compatibility. > > You can contact them by email or phone. > > Delrue@horizon-tech.fr > > tel : +33 1 60 92 10 03 > > http://www/horizon-tech.fr > > Vincent > > Zhen Luo <zhenluo@ee.princeton.edu> a écrit dans le message : > 95di54$i85$1@cnn.Princeton.EDU... > > I am looking for an FPGA board with a PCI interface (or PMC). I hope the > > FPGA would have access to at least 4 banks of memory (preferably SRAM) of > > 32-bit data. And I hope each bank of memory would have large capacities > (>= > > 4M bytes). Does anyone know any board of this type? > > > > I did a search myself and the closest one I could find are the RC1000 > board > > from Alpha Data (4 banks, 32-bit interface, 2M bytes for each bank) and > > SMT406 from Sundance (4 banks, 36-bit interface, 2.25M bytes for each > bank). > > I wonder if there is anything bigger than that. > > > > Thanks, > > > > -- Zhen Luo > > > > > > > >Article: 29082
I did it in a month. What FPGA part are you trying to put it on and what memory do you have available? Andrew <tchoh@my-deja.com> wrote in message news:95m5li$j87$1@nnrp1.deja.com... > > > Hi. > > I wondered if anyone out there had attempted to implement the new AES > in an FPGA. > > If so, being new to the world of crytography, I wonder if you have any > general tips/advice? > > Thanks. > > > Sent via Deja.com > http://www.deja.com/Article: 29083
frouatbi@my-deja.com wrote: > I will tell you a philosofical dilemna, I'm an FPGA designer in Canada > which is a descent peacefull, country. > > Why would I go to France I'm Tunisian, I do have and in your face > a deep hate for this country. Athough I like the francophone > culture, I have a deep hate/liking of this country culture. > > The United States, with the bloody george bush, and the people of > the gulf war. > > I better stick in here in Montreal, and complain about the weather, > It's better than France Racism, or USA war on the arabs. > > Sorry but you have to consider the human side along with the technical > stuff, > > Yours Truly > > Fredj Le magnifique > > Sent via Deja.com > http://www.deja.com/ Keep your political views to yourself. Since you don't like the United States so much why are your living in one of its states? (;>)Article: 29084
Hi all, I'm using Xilinx Project Manager 3.1i (Xilinx Foundation Base) and I'm trying to perform a Functional Simulation of some Verilog design, but the signals I want to see are not shown in the Component Selection for Waveform Viewer window. I thought I should be able to view any signal in my design. I thought running something like Top_Level.Lower_Level.Signal_Name or Top_Level/Lower_Level/Signal_Name in a script file should let me view any Signal_Name in module Lower_Level instantiated by module Top_Level but it doesn't work for me. Does anyone knows what to do to view any signal in a design (including lower-level module's signals?) Thanks for the help.Article: 29085
Hey Jerry, he lives in Montreal. Still Canadian last time I checked. Sincerely Daniel DeConinck High Res Technologies, Inc.Article: 29086
<frouatbi@my-deja.com> wrote in message news:95mk3j$gj$1@nnrp1.deja.com... > > > I will tell you a philosofical dilemna, I'm an FPGA designer in Canada > which is a descent peacefull, country. > > Why would I go to France I'm Tunisian, I do have and in your face > a deep hate for this country. Athough I like the francophone > culture, I have a deep hate/liking of this country culture. > > > The United States, with the bloody george bush, and the people of > the gulf war. > > > I better stick in here in Montreal, and complain about the weather, > It's better than France Racism, or USA war on the arabs. > > Sorry but you have to consider the human side along with the technical > stuff, > > Yours Truly > > Fredj Le magnifique Although I can see from where you come from, I do not think it is appropriate to post these (racist?) comments on this newsgroup.Article: 29087
On Mon, 05 Feb 2001 10:36:36 -0700, Brian Philofsky <brian.philofsky@xilinx.com> wrote: >Take a look at the Synthesis and Simulation Design Guide, >http://toolbox.xilinx.com/docsan/3_1i/docsan.htm. Chapter 6 for more >information on what I briefly explained above. Also if you are using >Verilog, help for that language is documented there as well. > >I know I plug this book a lot but it answers a lot of peoples questions in >the area. I suggest most all FPGA designers to at least glance through it >for synthesis and simulation questions/problems. > >-- Brian Hi Brian, Recently Xilinx shipped the 3.3.06i device update CD to go together with SP6. The intructions with the CD said it must be installed prior to the SP6. Unfortunately the CDs arrive many weeks after the SP6 became available on the web site, and there was no info with SP6 that you needed to wait for the CD before installing SP6. If SP6 has already been installed, and then the CD arrives, is it ok to install the CD, and then re-install SP6, or is everything hosed. With the CD there were two yellow/green pages of "read me first" that among other things, indicates that there is updated documentation in the online (via the web) for the Libraries Guide, and Synthesys and Simulation Design Guide. Like many users, I have installed the documentation on my local machine (takes about 30MB). I would much prefer to update my local copy of the documentation so I don't have to go on-line to read the docs. Could you please make available the files that were changed so that I can update my local copy. There does not seem to be a way to do this given starting point links such as http://toolbox.xilinx.com/docsan/3_1i/docsan.htm as this dumps you int the frames based system. Philip Freidin Philip Freidin FliptronicsArticle: 29088
In article <95m5li$j87$1@nnrp1.deja.com>, tchoh@my-deja.com wrote: > > > Hi. > > I wondered if anyone out there had attempted to implement the new AES > in an FPGA. > > If so, being new to the world of crytography, I wonder if you have any > general tips/advice? > > Thanks. > > Sent via Deja.com > http://www.deja.com/ ----------------------------- Hi, I'm cofounder of a startup, ---- 3rdeye Technology, LLC ---- We have patent-pending IP cores that can do a number of encryption algorithms as logic gate functions, meaning, completely non-sequentially. (DES, AES, Twofish, RC6, Serpent, SHA-1) Thus, we can perform these algorithms in just one process (clock) cycle, versus multiple sequential cycles. We presently have a version of Rijndael (AES) which will encipher/decipher a 128-bit key, which we have so far fitted in an Altera EPK1500 device. We also have versions of DES which will fit in Altera and Xilinx devices, which run the gamut of just single DES (1DES), to a device which will do 1DES-3DES in one chip. --- All non-sequentially --- All our designs are in VHDL, which we can port to any technology and device family which can accommodate the necessary gate count to implement them. The advantage of our approach is we trade off real-estate (gates) for speed and ease of designs. Also, because our designs are completely non-sequential (static logic) we draw the lowest possible power for a given device technology, while outperforming sequential based implementations in the same device technology. And as device features get smaller, the number of device families which will be able to easily accommodate our designs will rise, though currently, ASIC designs would provide the means to create the most optimal design fits. We are presently seeking licensing and partnership agreements with interested entities for use of our IP cores and methodology. For interested parties, I can be contacted at: Jabari Zakiya 3rdeye Technology, LLC 703-608-9233 (cell) jzakiya@hushmail.com Sent via Deja.com http://www.deja.com/Article: 29089
Hello, Does anyone have or know where I can find a list of .ucf commands and their syntax... Thanks in advance... JeffArticle: 29090
I didn't have an SPROM in my implementation. With it, you need to follow the guidelines described in the errata on the Insight web site ( http://www.insight-electronics.com/solutions/kits/xilinx/downloads/jtagErrataNotice.pdf ). This is linked to the Development kit page at http://www.insight-electronics.com/solutions/kits/xilinx/spartan-ii.html. Karim LIMAM wrote: > Hi, > > The JTAG Clock is already selected as start up clock. > When I try to configure the FGPA with a bypass through the SPROM .. I get a > doctor Watson error ?? > > Thanks. Marc Baker XilinxArticle: 29091
jzakiya@my-deja.com writes: > I'm cofounder of a startup, > > ---- 3rdeye Technology, LLC ---- > > We have patent-pending IP cores > that can do a number of encryption > algorithms as logic gate functions, > meaning, completely non-sequentially. > (DES, AES, Twofish, RC6, Serpent, SHA-1) > Thus, we can perform these algorithms > in just one process (clock) cycle, > versus multiple sequential cycles. Sure, one SUFFICIENTLY LONG clock cycle. Care to quote cycle times for real FPGAs (or ASIC processes)? For most applications a pipelined implementation is much preferred, as you get much higher total throughput. The exception is usually when you have a single stream of data to be encrypted in a feedback mode. I have no doubt that you'll get a patent (it's possible to get a patent on *anything*), but I'm curious as to what aspect of the encryption implementation you're patenting. Surely you don't think that simply expanding the equations into a large combinatorial function is in any way novel? For instance, there have been many DES chips that implemented a single round combinatorially. If you try to flatten two rounds into a sum-of-products, it gets completely unmanageable, but you can simply chain multiple single-round combinatorial circuits to get what you describe. It's just not particularly better than doing it the conventional way, with pipeline registers between the rounds.Article: 29092
"Jeff and Bev Neil" <jbneil@cfl.rr.com> wrote in message
news:JsHf6.97868$8V6.13360091@typhoon.tampabay.rr.com...
> Hello,
> Does anyone have or know where I can find a list of .ucf commands and
their
> syntax...
> Thanks in advance...
> Jeff
Jeff,
Try support.xilinx.com, Software Manuals, HTML format, Libraries Guide
(on left), Attributes, Constraints and Carry Logic.
Several topics under this section discuss the .ucf commands and their
syntax. The most prominent one is Attributes/Logical Constraints.
Also, look at the Development System Reference Guide. It has a ton of
information. Chapter 6, in particular, is great because it discusses the
constraints that most designers use.
The in-famous RLOCs are covered under Chapter 12, Relative Location
(RLOC) Constraints.
Or click on the below URL to get to the Libraries Guide.
http://toolbox.xilinx.com/docsan/3_1i/docsan.htm
Good luck.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL USA
Article: 29093In article <qhhf28a7vv.fsf@ruckus.brouhaha.com>, Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote: > jzakiya@my-deja.com writes: > > I'm cofounder of a startup, > > > > ---- 3rdeye Technology, LLC ---- > > > > We have patent-pending IP cores > > that can do a number of encryption > > algorithms as logic gate functions, > > meaning, completely non-sequentially. > > (DES, AES, Twofish, RC6, Serpent, SHA-1) > > Thus, we can perform these algorithms > > in just one process (clock) cycle, > > versus multiple sequential cycles. > > Sure, one SUFFICIENTLY LONG clock cycle. Care to quote cycle times > for real FPGAs (or ASIC processes)? > > For most applications a pipelined implementation is much preferred, > as you get much higher total throughput. The exception is usually > when you have a single stream of data to be encrypted in a feedback > mode. > > I have no doubt that you'll get a patent (it's possible to get a > patent on *anything*), but I'm curious as to what aspect of the > encryption implementation you're patenting. Surely you don't think > that simply expanding the equations into a large combinatorial function > is in any way novel? For instance, there have been many DES chips > that implemented a single round combinatorially. If you try to flatten > two rounds into a sum-of-products, it gets completely unmanageable, > but you can simply chain multiple single-round combinatorial circuits > to get what you describe. It's just not particularly better than > doing it the conventional way, with pipeline registers between the > rounds. ------------------------------- We have compiled and simulated a 1DES design which can both encipher/decipher in ECB mode in one device. It was fitted in an EPF10K100EQC-208-1 and was simulated with Altera Maxplus II 9.6 almost a year ago. It had a worse case total propagation delay (TPD) for a complete block of 155 ns. With current Altera and Xilinx devices, and using newer (better) synthesis and place and route tools, we can do under 100 ns in their small devices, and better in their bigger devices. We were able to briefly use a gallium-arsenide ASIC library to compile a full 1DES design, and its worse case TPD was under 20 ns (~18 ns) (>50 MBlocks/s -> 3.2Gbits/s). This, again is without pipelining, which allows these cores to easily implement various design modes (ECB, CBC, ect) with the minimalist amout of control logic and with the lowest possible power consumption. A full 3DES design in an Altera or Xilinx (currently the FPGA device families with the largest gate count chips) should have a 3DES TPD of < 150 ns, based on their device specifications. ASIC designs in even .25 micron families should do < 75-100 ns. and with .18-.13 micron CMOS devices we project full 3DES TPDs around 50-75 ns. AES was a very good selection by NIST (National Institute of Standards and Technology) as the AES algorithm from a hardware implementation viewpoint. Since it only requires 10, 12, or 14 rounds (for 128, 192, and 256 bit keys) it is relatively faster than DES, even though it's blcoksize is twice as wide (128 vs 64 bits) and its key schedule is much more involved. The full encipher/decipher chip for a 128-bit key which can compile (unoptimized) into an Altera EP20K1500 device had a simulated worse case TPD of about 200 ns with Quartus 2000.9 With the claimed better synthesis and place and route tools of Quartus II, it should not only compile to be faster, but we may also be able to compile a full 128-256 bit key design in one device. But you must also realize, when I say **FULL** design, I mean not only the cipher arithmetic is done non-sequentially, but also the full key expansion (for AES) for each keysize is also done non-sequentially, ALL IN ONE DEVICE! Our devices are the simplest encryption devices to design with, requiring the least amount of external control logic to interface to, which enables systems to be made with less parts (which lowers total system costs), using less power, and which are faster than all other sequential design EXCEPT highly pipelined designs, which have all their attendant problems. In fact, you can pipeline our design at the block level, versus the single cipher round function level, and get better perfermance too. Also, for special purpose applications, such as for MACs, where you only need the encipher function, we can make even faster devices which will fit in smaller chips. We can also strip out the key expansion logic for AES if desired, if that function can be done in software. The point is, their is a science to performing these algorithms non-sequentially which is much more involved than stringing a bunch of XOR gates together. And just like many things are "obviious" AFTER someone has done it, our design methodology is not very "obvious" especially since no one has done any of the algorithms we have implemented in the manner we have AND with their efficiency and utility. Again, for parties interested in learning more about our technology and IP portfolio, please feel free to contact me. Jabari Zakiya 3rdeye Technology, LLC 703-608-9233 jzakiya@hushmail.com Sent via Deja.com http://www.deja.com/Article: 29094
Yes, what's the point ?? Such comments has nothing to do in here !!! Vincent <frouatbi@my-deja.com> a écrit dans le message : 95mk3j$gj$1@nnrp1.deja.com... > > > I will tell you a philosofical dilemna, I'm an FPGA designer in Canada > which is a descent peacefull, country. > > Why would I go to France I'm Tunisian, I do have and in your face > a deep hate for this country. Athough I like the francophone > culture, I have a deep hate/liking of this country culture. > > > The United States, with the bloody george bush, and the people of > the gulf war. > > > I better stick in here in Montreal, and complain about the weather, > It's better than France Racism, or USA war on the arabs. > > Sorry but you have to consider the human side along with the technical > stuff, > > Yours Truly > > Fredj Le magnifique > > > Sent via Deja.com > http://www.deja.com/Article: 29095
> I did it in a month. What FPGA part are you trying to put it on and what > memory do you have available? > > Andrew Hi Andrew. Thanks for replying. I'm finding the whole area of cryptography very interesting, although I can't claim to understand the motivations for the design of Rijndael in detail. I'm implementing the block for a Spartan II 150. Ideally I'd like to use a single block RAM, so I thought that maybe I could implement a single forward S-table and a reverse S-table in one (512 byte) RAM. I have a requirement of something like 50 clock cycles to process all 16 bytes, running at around 50MHz. Sent via Deja.com http://www.deja.com/Article: 29096
Hello, I need to build a 'switching matrix'. (Please look at the picture to understand the message ). I must be able to 'route' the signal from port A to port X,Y or Z, and idem for B and C. If port X is used, it quite understandable that i wont be able to 'route' an other signal comming from port A.B or C there. The signal that i'll use is PCM clocked at the speed of "from 64Khz to 3Mhz". Each port has a TX and RX pin. Once a 'virtual' route is created, ( example, from port B to port Z ) i must be able to create a other 'route' ( example, from port A to port Y ) without creating a glitch or noise to the first one already 'live'.For testing a 3x3 ports matrix is ok. but the next one will be around 30x30 ports matrix. My question is, which device can be the best for this kind of application, and , an idea how to build the concept of a matrix like that. Regards, Marc./ S_mythicbird@hotmail.com Ps: remove the S_ if you want to reply via email. Thanks.Article: 29097
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end
Article: 29098Hello. I have an FPGA board with an XC4010. The current tools (Foundation 3.1/3.3) & VHDL/Verilog synthesizers (FPGA Xrp, Spectrum, etc) don't show support for the XC4000 "plain vanilla" family of parts. I was however told that the 4000E uses the same bitstream as the 4000 so one could "set up" the tools for an 4010E and use that bitstream to configure the 4010, is this true? (I was told internally 4000E and 4000 are the same). If not, is there anyone who wants to "trade" multiple 4010 and 4003A parts for 4000E series? Thanks! V.Article: 29099
I am trying to implement a simple design. An error report is as below: ERROR:Pack:198 - NCD was not produced. All logic was removed from design. This is usually due to having no input or output PAD connections in the design and no nets or symbols marked as 'SAVE'. You can either add PADs or 'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in the mapper. Problem encountered generating the NCD. I have assigned all the pins in the design entry. what is wrong?
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