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Peter wrote: > > To be safe, the cell would need to be of known high quality and be > replaced more often than every decade. Every 5 years would be safer, > and moreover the designer would have to build in something (a large > cap) to hold the VCC up while it is being changed. That cap cannot be > any sort of electrolytic (which includes tants); it would have to be a > ceramic. Which leads to the interesting question of what happens when a battery replace fails, such that the KEY is lost. ( eg the battery briefly shorts on insert, or the PCB is placed, with best intentions, onto an antistatic rubber mat while the change over is done )... How does the Virtex indicate this Key failure to the customer ? Do you contact the supplier, 5 years on, for a key for Product MMM, Version NNN,release Dat YYYY ? (plus the instructions / tools for loading this key back into the newely NV ram..) Or maybe it has to be back to supplier for a re-load of key, and if they were paranoid enough to need this, imagine the cost overheads of this administration ? I can see a market for 20 year+ guaranteed backup batteries ( at a premium of course :-) - jgArticle: 29051
duh, how do I specify a timing constraint on a module port for a module
instantiated inside another one.
eg
module av(clk, ....)
... other stuff
my_mod testmod(clk2, ....)
endmodule
I want to set a period constraint on clk2.
I am using Xilinx F1.5 student edition software
Thanks
Rob
Article: 29052
The FPGA conference list on optimagic.com seems to be outdated. What
FPGA-related conferences are scheduled for 2001, besides the ACM/SIGDA
conference in Monterey?
Thanks,
EKC
alpha3.1 AT ix DOT netcom DOT com
Article: 29053"Kevin J. McCann" wrote: > I am an amateur circuit designer. It seems that the FPGA world may now be > inexpensive enough for me to give it a try. Could you please recommend a > book and board combo that would get me going. Although I have a good > understanding of TTL style logic design, I have no experience with this > more advanced stuff. > Thanks, > Kevin I've come across an older book "FPGA Workout, Beginning Exercises w/ the Intel FlexLogic FPGA", X Systems Engr. Software, 2608 Sweetgum dri., Apex, N.C. 27502 1-800-549-XESS. I've heard they have a 2nd ed of this book ?Article: 29054
Let me just correct some misunderstandings. Then everybody is free to use his own imagination. 1. The encryption feature is an option. If you don't want to use it, just ignore it. No battery, no key. All you see is one unused and unusable pin. 2. If you want to use an encrypted bitstream, you must first load a triple-DES key into the chip (168 bits ) and you then must send it an encrypted bitstream, but you can also send an unencrypted bitstream. The FPGA is smart enough to know the difference and work in either case. 3. Readback is no longer an option when you use an encrypted bitstream. (for obvious reasons, since the internal configuration memory is decrypted "plaintext" information, that must be kept secret. ) 4. When there is no Vcc, the battery keeps the latches alive that store the key information. Nothing more. The battery does not maintain the whole configuration. Every time you re-apply Vcc, you must again reload the (encrypted) configuration. But the data looks like rubbish and cannot be used on any other chip, that has a different ( or no ) key stored. 5. Battery current, when Vcc is active, is sub-nA. Zero for all practical considerations. When Vcc is off, the battery current is below 100 nA. This current consumption is irrelevant. Even a small 100-mAhour-capacity battery would theoretically drive 100 nA for one million hours, which is more than 100 years. Battery capacity and the precise number of nanoamps required are not the issue. Battery self-discharge, and the cleanliness of the socket and pc-board are the important factors. 6. Exchanging the battery is uncritical, provided Vcc is active during the operation. That's why we do not recommend a parallel capacitor, and definitely not a leaky electrolytic. During battery change you can short circuit the battery pin to Vcc or to ground or leave it open as long as you want (provided Vcc is up ). The key information will stay intact. Maybe this clarified something. Peter Alfke ==================== Jim Granville wrote: > Peter wrote: > > > > To be safe, the cell would need to be of known high quality and be > > replaced more often than every decade. Every 5 years would be safer, > > and moreover the designer would have to build in something (a large > > cap) to hold the VCC up while it is being changed. That cap cannot be > > any sort of electrolytic (which includes tants); it would have to be a > > ceramic. > > Which leads to the interesting question of what happens when > a battery replace fails, such that the KEY is lost. > ( eg the battery briefly shorts on insert, or the PCB is placed, with > best > intentions, onto an antistatic rubber mat while the change over is done > )... > > How does the Virtex indicate this Key failure to the customer ? > > Do you contact the supplier, 5 years on, for a key for Product > MMM, Version NNN,release Dat YYYY ? (plus the instructions / tools > for loading this key back into the newely NV ram..) > > Or maybe it has to be back to supplier for a re-load of key, and > if they were paranoid enough to need this, imagine the cost > overheads of this administration ? > > I can see a market for 20 year+ guaranteed backup batteries > ( at a premium of course :-) > > - jgArticle: 29055
In article <3A6DE0C8.D4EE4F7A@xilinx.com>, peter.alfke@xilinx.com wrote: > Will be fixed next week. > It sometimes helps to complain to the newsgroup. :-) > Peter Alfke Yet, Nothing new @ http://www.xilinx.com/xcell/xcell.htm Did I miss something ? ------------------------------------------- Rotem Gazit mailto:rotemg@mysticom.XYZ-REMOVE.com http://www.mysticom.com ------------------------------------------- Sent via Deja.com http://www.deja.com/Article: 29056
Austin Lesea wrote: > http://www.xilinx.com/support/programr/cables.htm > > for the "new" cables that use USB for faster configuration. > Except for us poor suckers stuck with WinNT Question: Does Foundation 2.1iSP6 run under Win2K ?Article: 29057
Peter Alfke wrote: > > Terry Hicks wrote: > > > > > Sounds like another Y2K on a continuous basis... > > C'mon, let's put this in perspective. ...SNIP... > Now Xilinx offers, in a new family, the option of > encrypting the bitstream. > And all I hear is the whining that batteries don't > last, need to be changed, > causing a service problem. Y2K, my foot ! ...SNIP... > I did not expect a loud "thank you" for offering a > new valuable and, in certain > cases, priceless feature. > But I had not expected all this whining either. > Encrypted bitstreams are encrypted for a reason. > Changing the battery every > decade is a minor nuisance, well worth the > protection it offers, if you need > the protection. Nobody forces you to use this > unique option. > End of soapbox. > > Peter Alfke Peter, Don't you think you are over reacting a little? I don't see this as an attack on the Virtex II chips. I see this thread as a discussion of the pros and cons of the encryption feature as well as a discussion of how it can best be used. I didn't see Terry even mention Xilinx or Virtex II. He was simply making a comment about what he sees as a significant problem with the production and maintenance of battery backed up products. If you go back to Terry's message there is no mention anywhere of any brand names, just the general description of problems with battery technology making products disposable rather than repairable. Sounds like my electric shaver, instead of lasting 5 years or more with blade changes, they last 2 years because of battery failure. I would suggest that instead of seeing this discussion as "whining", you take advantage of it and tell us all how best to use the encryption feature and to provide products that can be maintained for many years. In a later post I see you refer to a Xilinx recommendation of not using a parallel capacitor. Is this in an app note anywhere? I have reread your posting here on the Virtex II and did not see a mention of it. Sounds like a good opportunity to me. BTW, I don't think you need to keep pointing out that the encryption feature is optional. People do understand that. They just need to bat around the issues of using it. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX URL http://www.arius.comArticle: 29058
i need to create a clock multiplier.i'm using xc4k series fpga and i know that using spartan series it can be made.i'm beginer so i made search on this subject and found nothing.please help meArticle: 29059
I've just changes synthesis tools from Synopsys to Leonardo and I'm having a small problem with my post-synthesis simulation. Synthesising to Xilinx XC4000XL the design uses a global reset therefore Leonardo connects this input to the STARTUP block. However, when I come to perform post-synthesis simulation of my design no simulation model exists for the STARTUP block so I can not simulate a reset condition. I'm sure that there must be a mechanism for working around this problem but I can't seem to find any information on the problem. Anybody else experienced this problem? Got a solution? Loenardo version 1999.1 Thanks for any help. Darrell. Sent via Deja.com http://www.deja.com/Article: 29060
See Dr. Steve Wilton's page of "Upcoming and Recent FPGA/VLSI/CAD Conferences" at www.ee.ubc.ca/~stevew/conf.html. Jan Gray, Gray Research LLCArticle: 29061
Goran, please tell us what the multiplication factor is. 2 is relatively easy if your input frequency has a duty cycle close to 50%. Anything higher is impossible inside XC4000 and Spartan. Virtex and Spartan2 can multiply by up to 4, and Virtex-II can cover a much wider range, and they can do that without any input duty-cycle restriction. Peter Alfke, Xilinx Applications goran wrote: > i need to create a clock multiplier.i'm using xc4k series fpga and i know that using spartan series it can be made.i'm beginer so i made search on this subject and found nothing.please help meArticle: 29062
Hi,
I want to make a single cycle low pulse as a global reset in VHDL:
signal start : std_logic;
begin
p: process(reset, clk) begin
if(reset = '1') then
start <= '0';
else if(rising_edge(clk) and clk = '1') then
start <= '1';
end if;
end process p;
control_rest_of_design <= start;
...
For a Xilinx part I would use the ROC block for the reset signal. What
should I use for an Altera device? If I remove the reset signal, although
the initial state of the DFF inferred is '0', so I get my one cycle low
pulse, Leonardo Spectrum will optimise the DFF away, as the input is always
'1'. All the examples in the Quartus and Leonardo manuals appear to export
the reset signal to an external pin. I can directly instantiate a DFFE but
this only works correctly for Synplify Pro, Leonardo Spectrum gives a 'DFFE
start not mapped to atom in Flex20K library' warning, and the EDIF produced
tries to instantiate a non-existent DFFRS so the synthesis fails. I assume
there is some kind of conflict and it is renaming the DFFE component.
I'm sure this is basic Altera design, any help would be much appreciated.
Thanks
James Rowland
Design Engineer
Article: 29063Gerhard Griessnig schrieb: > > I get an error message although i use the UCF( NET "P2_TXCLK" > USELOWSKEWLINES;). > I had try to declare P2_TXCLK as IBUF, as IBUFG and without buffer! > My error mesage: > ERROR:MapLib:93 - Illegal LOC on symbol "P2_TXCLK.PAD" (pad signal=P2_TXCLK) > or BUFGP symbol "C37642" (output signal=P2_TXCLK_BUFGPed), IPAD-IBUFG should > only be LOCed to GCLKIOB site. Yes, this is a really stupid bug of the P&R Software (hello Peter ;-) When there are more than 4 clock nets in the design, the P&R Software tries to assign all clocks to global clock nets by default. SOLUTION. Go to the synthesis constraints (click to the versions view, in the tree there is somewhere the menu for the synthesis constraints) go to PORTS, adjust the default setting (first line) for use clock lines to DONT USE(dont know exactly the name, Iam at home now and dont have the software here). Now adjust the nets that should use the global clock nets (remember that the clock pins MUST use global clock lines), all other clock nets can be left unchanged (they use the default mode). Press OK. -- MFG FalkArticle: 29064
Rick Filipkiewicz schrieb: > > Except for us poor suckers stuck with WinNT > > Question: Does Foundation 2.1iSP6 run under Win2K ? Jep. -- MFG FalkArticle: 29065
jimmy75@my-deja.com wrote: > > > None of our boards will fit this particular application. A board > > with a PCI bus interace is needed for the high-speed transfers > > between the FPGA board memory and the PC running the desktop > > publishing app. All our boards interface through the > > parallel port which is too slow for this type of application. > > Yep. We need a PCI board for our purpose preferably with a DMA > controller and a Xilinx Virtex chip(s) and lots of memory. If only we > could make one on our own! > I had a look on the web and didn't find all these features altogether > in one board. We were hoping that somebody out there could help us. > > -- Jim > > Sent via Deja.com > http://www.deja.com/ I'm currently looking at a board for some ASIC prototyping. Its by a company called Nallatech, in Scotland. It might be what you're looking for. It's called Balleynuey 2 and it accepts 4 Plug-in daughter boards, of which they sell different kinds (Virtex, ARM, I/O, etc..). Additionally, if anyone has any feedback or experience with this board, I would appreciate hearing it. Thanks! www.nallatech.com -Dan National SemiconductorArticle: 29066
Thanks Rick. point well taken. Maybe all this talk about short-lived lithium batteries ws getting on my nerves... Let's not forgt that Dallas Semiconductor has been packaging SRAMs with batteries for many years. If you need large-capacity programmable logic, and you are concerned your design being blindly ripped off, and you don't want to just rely on the lawyers, then Virtex-II with battery back-up is your only choice. Peter Alfke, Xilinx ApplicationsArticle: 29067
It is certainly usefull to have this encyption option. It may not be ideal for all cases. Personally I may use it for the first year or so with a new customer before sizing them up for trustworthyness. I know I have been ripped off in the past. When customers tabulate the BOM they feel that they could save money making my boards themselves. I like to tell them that a $500 software program is distributed on a $1 CD and $2-10ish manual. I say that hardware manufacturers likewise have costs beyond the PCB that require similar mark-ups. Off course they don't care. They just rub their hands together dreaming of their lower costs when they reverse engineer my boards. Thanks to Xilinx for giving me a tool to help fight back. Sincerely Daniel DeConinck High Res Technologies, Inc.Article: 29068
Rob Finch wrote: > duh, how do I specify a timing constraint on a module port for a module > instantiated inside another one. > > eg > module av(clk, ....) > ... other stuff > my_mod testmod(clk2, ....) > > endmodule > > I want to set a period constraint on clk2. > I am using Xilinx F1.5 student edition software > > Thanks > Rob Look at the TNM, TNM_NET, TIMEGRP and TIMESPEC commands used in UCF described thoroughly in http://support.xilinx.com. In this page, go to library, and go to M2.1i manuals. In the front page of the M2.1i manuals, you will find M1.5i manuals. These manuals are the best for you. Xilinx has placed the link in such a deep place. UtkuArticle: 29069
I have a design which has some inout pins. it is finally targetted at XILINX, virtex family. when ever i use I/O pads while synthesisng my chip in FPGA Compiler II, the inout is not synthesised properly. The problem i have found was it is placing buffers at the io pins which are unidirectional. so only input is working while out put is not working. so plz tell me how to tell the compiler that use bi-directional buffers. thanx in advance kuldeep Sent via Deja.com http://www.deja.com/Article: 29070
jhass@aurora.mrc.unm.edu (Joe Hass) writes:
> In article <3a7a137f$1@news.starhub.net.sg>,
> "Kang Liat Chuan" <kanglc@agilis.st.com.sg> writes:
> |> Besides the front-end design language, what are the major
> |> difference between FPGA design and IC design?
>
> If you make a mistake in your IC design it may cost more than your yearly
> salary to correct and take several months. IC designers tend to sweat
> the details and spend a lot of time verifying their designs before
> committing them to silicon.
Programmable devices like software let you start manufacturing and
even sell a product before it is fully designed.
In the old days if you bought something that didn't work it went back
to the shop. Now you're expected to have to download new windows
drivers. And notice the set-top box software changing from time to
time. The same thing now applies to programmable devices and a
product's digital circuitry. With some care and it can be changed even
after it is sold.
Which is great news in the modern .com looking for funding.
Jon
Article: 29071Hi. I wondered if anyone out there had attempted to implement the new AES in an FPGA. If so, being new to the world of crytography, I wonder if you have any general tips/advice? Thanks. Sent via Deja.com http://www.deja.com/Article: 29072
Bonjour, Poste : Ingénieur électronique Salaire : 240 à 340 KF suivant profil et expérience Contrat : CDI, embauche immédiate Lieu de travail: Les Ulis, ZA de Courtaboeuf (91), 20 km Sud de Paris par A6 ou N118 Société high-tech dans le domaine des systèmes numériques de traitement de données, nous utilisons les technologies les plus performantes en FPGA, en processeurs DSP C6X, et en électronique numérique dans des produits destinés aux applications d'acquisition et de traitement du signal (radar, ultrasons, imagerie médicale, télécoms, aérospatial, radio-astronomie,.) Dans le cadre du développement d'une nouvelle gamme de produits, nous recherchons un ingénieur électronicien ou informaticien, BAC +5, (écoles d' ingénieurs ou universités) maîtrisant le développement sur FPGA (VERILOG, et/ou VHDL) et possédant des connaissances en électronique numérique et en C, C++. L'anglais est nécessaire. Si vous êtes intéressé, merci d'envoyer votre CV par Email, fax ou courrier à : Patrick DELRUE delrue@horizon-tech.fr Pour tout renseignement complémentaire téléphonez au 01 60 92 10 10 HORIZON TECHNOLOGIES Bât Oslo - les Fjords - 19, Avenue de Norvège 91953 COURTABOEUF Cedex fax: 01 64 46 21 46 WEB: http://www.horizon-tech.frArticle: 29073
Dear Zhen, Horizon Technologies will soon have the solution you request for : Their PCI mother board supports a daughterboard which provide 4 SRAM Like 64bit 512MByte memory banks connected to an APEX20k400. This board will also have three 32bits input channels each capable of 125MBytes/s sustained transfer rate for outside world compatibility. You can contact them by email or phone. Delrue@horizon-tech.fr tel : +33 1 60 92 10 03 http://www/horizon-tech.fr Vincent Zhen Luo <zhenluo@ee.princeton.edu> a écrit dans le message : 95di54$i85$1@cnn.Princeton.EDU... > I am looking for an FPGA board with a PCI interface (or PMC). I hope the > FPGA would have access to at least 4 banks of memory (preferably SRAM) of > 32-bit data. And I hope each bank of memory would have large capacities (>= > 4M bytes). Does anyone know any board of this type? > > I did a search myself and the closest one I could find are the RC1000 board > from Alpha Data (4 banks, 32-bit interface, 2M bytes for each bank) and > SMT406 from Sundance (4 banks, 36-bit interface, 2.25M bytes for each bank). > I wonder if there is anything bigger than that. > > Thanks, > > -- Zhen Luo > > >Article: 29074
Hi all, I am working on a project to port an C-ANSI program to Handel C target XILINX 4000E series. If you have any information about Handel-C such as tutorial, guideline,etc..., let me know ! Cheers ejeandeau@mpc-data.co.uk -- Posted from anchor-post-34.mail.demon.net [194.217.242.92] via Mailgate.ORG Server - http://www.Mailgate.ORG
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z