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Depends on how you write your code. Synplicity, for instance, will do the right thing if you write the vhdl so the load is in front of the add: cnt_d<=din when ld_n ='0' else q; cin<=1 when ld_n='1' else 0; process... cnt<=cnt_d+cin; Later versions of synplicity handle the simpler cases like the ccle without going to this extent. It still doesn't handle merging logic with adders too well. Jan Gray wrote: > > The Spartan-II (Virtex-family) carry logic is different from that of the > XC4000 family. > > It is possible to implement a CC8CLE in 4 slices (4 half CLBs), but as I > wrote just yesterday at www.fpgacpu.org, the CC8CLE implementation (F2.1i > library) uses twice as many slices as necessary. I suspect your favorite > synthesis product also requires 8 slices. > > As I wrote yesterday, you can implement > o = add ? a + b : a > o = add ? a + b : c > o = add ? a + b : a ~& b > <<and other even cooler things>> > in one logic cell (half-slice) per bit if you know the trick (using MULT_AND > together with MUXCY and XORCY). The Virtex library CC8CLE implementor (and > my synthesis vendor's technology mapper) are apparently unaware of the > technique. > > Jan Gray, Gray Research LLC > FPGA CPU News: www.fpgacpu.org -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27176
13-Nov-00
Rickman Hi,
Long time ago (~3 years) a similar problem arise when there was a
need for crc in 1G Ethernet using Ocra device and the solution was
simple instead of having 32 FF using 96 FF when the F.O. of each FF was
now devided to 3 and this solve the matter.
the frequancy in that case was 125M so this should do for you as well.
have a nice day
Illan
In article <3A0CB396.C53D0AA2@yahoo.com>,
rickman <spamgoeshere4@yahoo.com> wrote:
> I posted this message earlier from the office, but it does not seem to
> be showing up now, so I will ask again.
>
> I am working on a CRC calculation which is similar to other
calculations
> that I need to do in an FPGA. Because we want to be target
independant,
> we will not be able to use any target specific optimizations. My
problem
> is that in performing CRC calculations for 32 bit parallel, the
> equations end up being rather complex with up to about 20 inputs. This
> is too many for the speeds we are trying to use (>=80 MHz). So we are
> looking for alternative ways to reduce the complexity of the logic.
>
> One way that I have heard is to use a higher order polynomial which
is a
> multiple of the one desired. This can have the effect of spreading the
> calculations over more bits so that each bit uses fewer inputs and can
> be calculated at a faster rate. Then to get the correct result, a
> polynomial division is done. The trick seems to be trying to find a
> polynomial that makes the calculation simpler.
>
> Anyone heard of this and have any idea of how to find such a
polynomial?
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
>
> Ignore the reply address. To email me use the above address with the
XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com
>
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 27177
Hi,
I believe that you should upgrade your synopsys to
2000.11. The message below is quoted from Solvit news:
=========================================================================
October 24, 2000 Functional Bug in MC-inside-DW Flow SS-147
=========================================================================
*******************
NEWS
*******************
Functional Bug in MC-inside-DW Flow
===================================
A functional STAR (Synopsys Technical Action Request) has been reported
in the MC-inside-DW flow that may affect your design. This bug only affects
the Design Compiler 2000.05 release, and it's patch versions.
The bug has been fixed in the Design Compiler 2000.11 release.
...
Steven Derrien wrote:
>
> Hello,
>
> We've just upgarded to synopsys VSS 2000.05 and Xilinx M3.1, and some of
> my design whiwh used to simulate fine now generate an error during
> vhdlsim. Specificaly I use a behavioral model for the async_fifo core in
> the Coregen Library and this gives me the following error message (note
> that I did not forget to recompile all the library source file after
> upgrading)
>
> vhdlsim,106: The following error was encountered while elaborating
>
> /INFIFO/FIFO/CONTROL/WRSYNC_DCOUNT_BLK/GEN_WRSYNC_DCOUNT/WRSYNC_DATA_COUNT_SUB/COMPONENT:
> **Error: vhdlsim,4:
> Array index range length mismatch.
>
> The configuration I use for my design seems consistent to me (and was
> actually generated by the
> coregen tool itself). What I don't understand is that synopsys now find
> an error in xilinxcorelib vhdl
> source code while It didn't in previous version.
>
> for all : pci2usr use entity XilinxCoreLib.async_fifo_v1_0(behavioral)
> generic map(
> c_wr_err_low => 0,
> c_has_rd_count => 0,
> c_has_rd_ack => 0,
> c_wr_ack_low => 0,
> c_has_wr_count => 1,
> c_has_wr_ack => 0,
> c_has_almost_full => 0,
> c_has_almost_empty => 1,
> c_wr_count_width => 8,
> c_rd_count_width => 0,
> c_has_rd_err => 1,
> c_data_width => 32,
> c_has_wr_err => 1,
> c_rd_ack_low => 0,
> c_rd_err_low => 0,
> c_fifo_depth => 255,
> c_enable_rlocs => 1,
> c_use_blockmem => 1);
> end for;
>
> Has someone faced the same problem ?
>
> Steven
Hope this can help!!
Regards,
Addie Tang
------------------------------------------------
------------------------------------------------
-- --
-- Kai-cheong Tang, Addie --
-- VLSI Design Engineer --
-- Solomon Systech Limited --
-- Email: addietang@solomon-systech.com --
-- --
------------------------------------------------
------------------------------------------------
Article: 27178i don't think devel. tools are a problem, the gnu stuff works fine. for more info, check out the group leon-sparc on www.egroups.com or the web page (use google to search for 'leon sparc') cheers david Frank Van de Sande wrote: > hi, > > has anyone ever used the Sparc prcessor core from ESA (called Leon)? > > I'm considering it's use as a softcore in a Virtex, but i'm a bit > worried about development tools (compilers etc) > > any experiences about the model and/or the tools? > > thanks > > Frank Van de Sande > fvds12@yahoo.comArticle: 27179
Thank you all for your replies. I will definitely look into the 74245 part. Hayden Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27180
Ty Ray, I'll follow your advice and use an external pull-up.<br>JonasArticle: 27181
I'm a FPGA designer like you. I work for a medium sized company based out of Southern California, with a small San Jose design office. We need a few more talented FPGA engineers. I can't say enough about the place I work at. I am a Junior member of our staff, and there are only 5 designers including myself. The other 4 have worked together for a long time and are super talented. We do networking stuff, and just are bombarded with work. If you are talented, and have a good personality (pleasant to work with) then please contact me to learn more. Like I said, I'm not an HR person, I'm not a headhunter, you could possibly be working in the cube right across from me. Tons of financial perks, and we have been in business for 10 years. Our #1 account: Cisco, our #2 account: Nortel. We aren't fly by night. We just need talented people for a great working atmosphere. -- - Brad - bpollard@alumni.calpoly.eduArticle: 27182
> I haven't looked at the details of CRC to know how feasible this is, but > here's an approach you can try: > > You are trying to compute functions > > result(i) = F1(input(i), feedback(i-1)) > > feedback(i) = F2(input(i), feedback(i-1)) > [snip] > > feedback(i) = F3(F4(input(i)), feedback(i-1)) I think if you look at the CRC calculations, the first thing you want to do is XOR each input bit with the corresponding state bit, then feed that vector to a cloud of XOR gates. That is, I don't know of any way to pipeline it. You can push the FFs around the timing loop so that they grab things right after that initial XOR. I get a sore head every time I try to think that way, but it helped a lot when we did the CRC-32 in a 3190 many years ago. -- These are my opinions, not necessarily my employers. I hate spam.Article: 27183
Phil and steve,
thanks for the comments.
Phil James-Roxby wrote:
> Richard Meester wrote:
> >
> > Hi All,
> >
> > I am looking for some in depth information about LUTS and edif file
> > specs.
> >
> > I know what luts are, and what they can be used for, but is there any
> > information on what equations to use when, and what init strings to
> > provide. I read an article which described some of this by a truth
> > table, but i would much like a xilinx documentation on the technical
> > part of a lut.
> >
> > About the edif specs. I would like to know how to write a valid edif
> > file structure. Do you know of any information about this, except for
> > the $300,00 specs itself.
>
> I've done a fair bit of work involving LUTs and EDIF. I'm not entirely
> sure what you mean in the second paragraph, in terms of equations and
> init strings. The init string for a LUT in a Xilinx piece is simply the
> 1 bit wide 16 entry look-up table. Is this what you mean?
Yes, the 16*1 lookup table. The articel i read described this lookup table,
but i am not sure which inputs are for which part of the lookup table. I did
what steven and you are suggesting and trying to figure out the edif from
simple vhdl examples. This also gives me lut equations. I.e. for an AND i
qet the equation I0 + I1 and an init string of E.
in a 4lut lookup table i would have something simular. But which input is
connected to which place in the table. This is needed to calculate the init
string.
I.e.
| 00 | 01 | 10 | 11 -> these are I0 and I1, but which one is I0
and which one is I1. Is the first one I0?
--------------------------
00 |
01 |
10 |
11 |
above are I2 and I3. But which is which. Is the first one I2?
Secondly, the luts can also behave as rams, and LFSR. How do you connect
such a lut, and how does the table look like.
>
> I sussed how to write EDIF by looking at the output of synthesis tools,
> its all ASCII and quite humanly readable. To check the syntax of my
> handwritten EDIF, I used Active VHDL which will tell you the line number
> of your first error and not much else. But its about as good as it
> gets.
> I believe Brad Hutchings and the people at BYU have an EDIF parser
> written in Java which is free. This may be useful for you.
> Phil
Indeed the parser is for free. But it does just that, it parses, not
generates. But i will look in the generated edifs, and try figuring it out
myself.
Richard
>
> --
> ---------------------------------------------------------------------
> __
> / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545
> \ \ Staff Software Engineer Fax: Unreliable use email :-)
> / / Loki/DARPA Email: phil.james-roxby@xilinx.com
> \_\/\ Xilinx Boulder
> ---------------------------------------------------------------------
--
Quest Innovations
tel: +31 (0) 227 604046
http://www.quest-innovations.com
Article: 27184The problem is nots solved but I upgraded to the latest IP upgrade for M3.1 in which they provide a new version of the asynchronous FIFO core which simulates fine with VSS. Thank you for your help. Steven Steven Derrien wrote: > > Hello, > > We've just upgarded to synopsys VSS 2000.05 and Xilinx M3.1, and some of > my design whiwh used to simulate fine now generate an error during > vhdlsim. Specificaly I use a behavioral model for the async_fifo core in > the Coregen Library and this gives me the following error message (note > that I did not forget to recompile all the library source file after > upgrading) > > vhdlsim,106: The following error was encountered while elaborating > > /INFIFO/FIFO/CONTROL/WRSYNC_DCOUNT_BLK/GEN_WRSYNC_DCOUNT/WRSYNC_DATA_COUNT_SUB/COMPONENT: > **Error: vhdlsim,4: > Array index range length mismatch. > > The configuration I use for my design seems consistent to me (and was > actually generated by the > coregen tool itself). What I don't understand is that synopsys now find > an error in xilinxcorelib vhdl > source code while It didn't in previous version. > > for all : pci2usr use entity XilinxCoreLib.async_fifo_v1_0(behavioral) > generic map( > c_wr_err_low => 0, > c_has_rd_count => 0, > c_has_rd_ack => 0, > c_wr_ack_low => 0, > c_has_wr_count => 1, > c_has_wr_ack => 0, > c_has_almost_full => 0, > c_has_almost_empty => 1, > c_wr_count_width => 8, > c_rd_count_width => 0, > c_has_rd_err => 1, > c_data_width => 32, > c_has_wr_err => 1, > c_rd_ack_low => 0, > c_rd_err_low => 0, > c_fifo_depth => 255, > c_enable_rlocs => 1, > c_use_blockmem => 1); > end for; > > Has someone faced the same problem ? > > StevenArticle: 27185
Mon, 13 Nov 2000 07:33:47 +0000 (UTC) V Ram
<ipickeledthefigsmyself@mrbourns.com> written:
>I would like to find an ISP Serial EEPROM for an Altera 10K10. I currently
>have a EPC1LC20, but that requires a seperate programmer. Altera does have
>the EPC2 parts but they're pretty expensive (more expensive than the
>FPGA!). Any alternatives?
>
>I know Atmel makes parts that work with Xilinx/Altera, but they aren't
>JTAG ISP. Would the Xilinx config PROMs work an Altera? I think they're
>JTAG ISP...
>
>Any known working alternatives for the 10K10?
Try "In System Programming of configurators
AT17C65/128/256/512/010 of firm ATMEL"
http://www.orc.ru/~dkuzn/at17isp_e.htm
Supported functions:
- Setting and testing a polarity of pin Reset/OE.
- Disable and enabling a built-in generator DCLK.
- Reading and writing through 2-wires interface I2C.
- Verification - comparison with exemplary (source) file.
- Support of textual format TTF.
Used ByteBlaster.
Works under DOS or Win9x only. Version for WinNT inaccessible :(
Read file "AT17_ENG.TXT". All drawings in the ASCII-coding.
Configurator AT17C512A-10JI with built-in generator DCLK cost
approximately $10.
Best regards!
Dmitry Kuznetsov, Moscow, http://www.orc.ru/~dkuzn/index.htm
[Team RaceTerrapin] [Team LEXX]
===
Article: 27186
Hi,
Thank you all for your answers. As i could see, the best thing to
do is before launching Leonardo, starts maxplus2 to set .ACF correctly.
I heard from Mentor that there were a bug in Leonardo level 1, for
Altera.
Bye,
Flávio
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 27187You need to select the EDIF netlist format (*.edf or something similiar) in the generate schematic dialog box. The synopsys FPGA sythesiser uses the EDIF format for gate level descriptions. This should work although the schematics are useually to big and complex to follow, but thats life... Chris. <qianz@my-deja.com> wrote in message news:8up4fn$1ii$1@nnrp1.deja.com... > By Xilinx Foundation 3.li > At first create a simple VHDL project > then synthesis, if successfully synthesis this > click schematic menu, select > Generate schematic from netlist > but it shows > " Check Netlist File(types 0)" > while gives me a blank schematic > What is wrong?:( > Thank you very much! > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 27188
Hello, Can anybody suggest a mailing list or news group where I can post a job opportunity(other than the usual-Monster, ne.jobs, etc. I have done that) I have for a FPGA designer in the Boston Ma. area? I don't want to insult the integrity of this group by posting the details here. Thanks, MarkArticle: 27189
In article <8ur6lf$nk3$1@nnrp1.deja.com>, flavioas@my-deja.com wrote: > > > Hi, > > Thank you all for your answers. As i could see, the best thing to > do is before launching Leonardo, starts maxplus2 to set .ACF correctly. > I heard from Mentor that there were a bug in Leonardo level 1, for > Altera. > > Bye, > > Flávio > > Sent via Deja.com http://www.deja.com/ > Before you buy. > No You Don't. The best Methodology is : synthesize your design with leonardo in a separate directory and don't forget to uncheck the automatic creation of ACF file in leonardo because we didn't need it. And because it always write over the existing acf file too. then, go to another directory named (for example) place. copy the edif file that leonardo create in the place directory. launch maxplus2 or Quartus from the place directory. It create a ACF for the first time. so now, You have a good ACF that you can modify to apply your pinout. And this file will be never rewrite by leonardo. that's all best regards Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27190
Hi Rick, I think I have exactly what you need - a generic (any data and polynomial size, programmable polynomial and initial value), portable (any FPGA and/or ASIC) VHDL CRC generator that runs at over 80MHz (2.6Gbps) in Virtex FPGAs for 32-bit input data and 32-bit polynomial. If you are interested you can reach me at catalin59@yahoo.com Catalin BaetoniuArticle: 27191
Richard Meester wrote: > Yes, the 16*1 lookup table. The articel i read described this lookup table, > but i am not sure which inputs are for which part of the lookup table. I did > what steven and you are suggesting and trying to figure out the edif from > simple vhdl examples. This also gives me lut equations. I.e. for an AND i > qet the equation I0 + I1 and an init string of E. > in a 4lut lookup table i would have something simular. But which input is > connected to which place in the table. This is needed to calculate the init <snip> OK, first thing is the INIT value is the truth table in hex, where I0 is the least significant bit, I1 is the next least and so on. So you read from the top of the truth table, in your case a 2 input AND, so its only 1 when I0 and I1 are 1, so 0001, then you have to invert this value (don't ask me why!) to get 1110 or E in Hex. > Secondly, the luts can also behave as rams, and LFSR. How do you connect > such a lut, and how does the table look like. Don't instantiate a LUT, instantiate a RAM16x1 or an SRL16. Your favourite VHDL tool or the Xilinx library guide can give you the 'pinouts' for these components. They are found in the vcomponents library. > Indeed the parser is for free. But it does just that, it parses, not > generates. But i will look in the generated edifs, and try figuring it out > myself. I generate just by spitting out the relevant EDIF using Java. I have a few helper classes which keep track of open paranthesis and will format accordingly. You are (all) welcome to those. I dunno if there is a more intelligent way than this. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder ---------------------------------------------------------------------Article: 27192
hey, just basic question. will the reset pulse be generated "automatically" after configuration? can i use this pulse to clear some counters synchrnously. i don't want to infer the startup because of...(the famous story) thanks --Erika Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27193
I forget to add, is there any prefixed from where i can drive it ? In article <8usd7d$pqh$1@nnrp1.deja.com>, erika_uk@my-deja.com wrote: > hey, > > just basic question. will the reset pulse be generated "automatically" > after configuration? can i use this pulse to clear some counters > synchrnously. i don't want to infer the startup because of...(the > famous story) > > thanks > > --Erika > > Sent via Deja.com http://www.deja.com/ > Before you buy. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27194
Wisut, The way to begin is by going to the web site of the tool vendor that you happen to be working with. In your case, if I am not mistaken, this would be www.altera.com. In your post you say that you have the maxplusII tools. That is a good start. I, myself, use Xilinx tools but I am sure that the whole design process is documented at the altera web site. Take the time, download the proper manuals and you will get a feel for what you need to do. As for the programming method you will use, that is up to you (whichever is easiest for now....verilog, vhdl, abel, etc.). I am sure that Altera supports them all. I am sorry that this answer is not very detailed but I think that you have a lot of reading to do. Once you get more familiar with the process you will be able to ask more detailed questions. Good luck. Tom Cipollone tomcip@concentric.net Wisut Hantanong wrote: > I want to burn my own PLD (with my universal programmer ALL 11 from > www.hilosystems.com ), How to begin ? > I've got some *.vhd and abel code. How to compile and program it? > Is there use HEX code like in eprom for microprocessor? > I have some vhdl skill, digital circuit design, I can use maxplusII program > from altera (vhdl design course in university but only done with start > kit). > My first project is DRAM Controller form PAL device.I've get vhld code for > xilinx fpga. > Please tell me good introduction web.Article: 27195
Tim Jaynes wrote: > Hi all, > This is a known issue normally seen in non-English versions of Windows. > There is a solution on this- 10223: simply enter 'parser' in the Answers > Database search area. > It will tell you to open a support case with Xilinx- and you are supported > > even if using WebPACK- so that a support engineer here can get you > the tactical patch for this problem. > Regards, > Tim > ... or, alternatively, dump the GUI & run ngdbuild from the command line ?Article: 27196
but if I wanna to setup an initial value what can I do? For example I have a counter while the counter starts not from 0 but from 11 what can I do? Thank you very much! Andy Peters n o a o [.] e d u> <"apeters <"@> wrote in message news:8upcda$sjm$1@noao.edu... > madisonfff@usa.net wrote: > > > > Hi When I tried to synthesis > > > > the errors are > > > > the sequential mapping has detected that the cell "/ver1- > > Optimized/Counter_r > > > > eg<i?' > > > > uses both the asynchronous 'set' and 'clear' pins > > > > Can anyone tell me how to deal with that? > > > > What is the difference of 'set' and 'clear' pins > > > > Thank you very very much! > > > > Here is my VHDL program > > > > COUNTER_Gen: process > > > > (CLK,COUNTER,RESET,IFREQ,IDEADTIME,IDUTYRATIO,REALCONTROL,REALPHASE,IPH > > > > ASE) > > [snip rest of code] > > You should read the Synopsys HDL guide that comes with FPGA Express and > the Xilinx tools -- there's a style guide that will tell you the correct > constructs to use in your HDL to get it to do what you want to do. You > may also want to pick up one of the books about VHDL for synthesis. > > Part of your problem is that your sensitivity list should only have a > clock and an async reset if you intend to infer flip-flops. Your code > is confusing the tool. > > As for the difference between set and clear pins, when the async reset > is asserted, the flop's output is either set (to 1) or cleared (to 0). > Since the Xilinx architecture only lets you do one or the other, it > complains if you try to do both. > -- > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d u > > "It is better to be silent and thought a fool, > than to send an e-mail to the entire company > and remove all doubt."Article: 27197
Hi I tried this way and got a lot of *.alr file but there is still errors "G28*** error" but when I synthesized only the warning shows. what is wrong? Thank you once again! Chris Mc Clements <cmcclement@computing.dundee.ac.uk> wrote in message news:8urr0k$hss$1@dux.dundee.ac.uk... > You need to select the EDIF netlist format (*.edf or something similiar) in > the generate schematic dialog box. The synopsys FPGA sythesiser uses the > EDIF format for gate level descriptions. This should work although the > schematics are useually to big and complex to follow, but thats life... > > Chris. > > > <qianz@my-deja.com> wrote in message news:8up4fn$1ii$1@nnrp1.deja.com... > > By Xilinx Foundation 3.li > > At first create a simple VHDL project > > then synthesis, if successfully synthesis this > > click schematic menu, select > > Generate schematic from netlist > > but it shows > > " Check Netlist File(types 0)" > > while gives me a blank schematic > > What is wrong?:( > > Thank you very much! > > > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > >Article: 27198
Hi There the Xilinx Foundation 3.li tells me that the synthesis sucessfully implemented but there are a lot of warning, does it matter? Thank you very much! QianArticle: 27199
Rick,
(It's Tuesday already, you probably have what you need by now, but..)
I wouldn't give up on Peter's suggestion too quickly.
Check out Ross Williams' paper at:
http://www.ross.net/crc/crcpaper.html
It is a good explanation of CRC, and some interesting
ways to calculate. In particular, the 'table driven'
method does not require a really deep table.
Quoting from the paper:
"Algorithm
1.Shift the register left by one byte,
reading in a new message byte.
2.Use the top byte just rotated out of
the register to index the table of 256 32-bit values.
3.XOR the table value into the register.
4.Goto 1 iff more augmented message bytes."
(Company news server doesn't have start of this thread,
but I gather you want to process 4 bytes/cycle,
and don't know what clock rate you need)
The algorithm above only needs a 256 deep x 32 wide table.
That's a mere 1 BlockRAM, using 256 x 16 x Dualport.
Unfortunately, the need for a clocked read out of the
BlockRAMs means this takes two cycles (Peter, here is
another case where the clocked read is a nuisance! Is
there really no way to design these things with flow-thru
address->data? ). And to do four bytes using that
algorithm might be implemented with 4 BlockRAMs
in 5 cycles.
Check out the paper, it may give you some ideas.
HTH
John
rickman wrote:
> > rickman wrote:
> > >
> > > Certainly this would work if we were doing a smaller calculation. We
> > > could use the block ram as a lookup table. But we have 32 bits input
> > > with 9 to 16 bits of feedback and 32 bits out. This would need far too
> > > large of a RAM to be practical.
> > >
> > > We also can't use proprietary features. This company wants to be
> > > independant of FPGA vendors so we don't make use of any proprietary
> > > features. Every time they design a new module, they compete price to
> > > pick a vendor. This may be smart or not depending on how much larger of
> > > a part they need to do a given job. But mine is not to reason why...
> > >
> > > It is also an interesting problem. I could stand to learn a little more
> > > about modular arithmetic and other such matters.
> > >
> > > Peter Alfke wrote:
> > > >
> > > > Is there a way to simplify ( and speed up ) this calculation by using
> > > > BlockRAMs as look-up tables?
> > > > Today's Virtex offers many 4k-bit dual-ported RAMs ( or call them ROMs ) of
> > > > arbitrary aspect ratio, e.g. 256 x 16.
> > > > The upcoming Virtex-II has 18 Kb dual-ported BlockRAMs that can be used as 1K
> > > > x 18 or 512 x 36 look-up tables. ( And each BlockRAM has two independent
> > > > ports, so it can implement the same code conversion or algorithm twice,
> > > > simultaneously. )
> > > >
> > > > These RAMs or ROMs are very fast, 1 ns set-up, < 3 ns clock-to-out,
> > > > and they are free, if you don't need them for anything better.
> > > >
> > > > Just a half-cooked thought...
> > > > Peter Alfke
> > > >
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