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Hi Magnus, Yes, skew is the difference between the arrival time of two signals, but again, it's the same clock net with the same driver that's have the skew problem. How can one part of one net have a maximum Tpd and another part of that same net have a minimum? Enough so that it makes a big difference, like in the ns range? And yes, on chip routing is slow. It's all capacitive loading of the entire net plus the gate of the receiver(s). That is not in dispute at all. What I'm saying is that skew on a signal net that is driven by a single driver can only come from the differences in propagation delay, or buffering elements in between. If all elements get their clock from a single clock net, how can there be skew in the range they are reporting? I hope this makes it a little clearer... Cheers, WallyArticle: 27451
eml@riverside-machines.com.NOSPAM schrieb: > > On Fri, 17 Nov 2000 14:46:43 +0100, Wolfgang Kufer > <wolfgang.kufer@rsd.rsd.de> wrote: > > >Hi All, > > > >I want to use an FPGA as PCI target. > > > >What are the possibilities of configuring this device? > >Must I use an onboard flash/eeprom device as configuration memory or is > >there any way to download the configuration data via the pci bus? > > This is a nasty problem. In principle, it should be possible to do it > by adding some extra circuitry which latches the address of > configuration writes, and resistor-isolating it so as not to violate > the PCI loading specs (hey, Mr. Xilinx, have you thought about > hard-coding this inside the FPGA?). If it works, it should be cheaper > than storing the configuration on your card. > > This was discussed a couple of years ago here and in > comp.os.ms-windows.programmer.vxd, but deja doesn't seem to be fixed > yet so you probably wont be able to find the threads. If you're > desperate, try emailing Joseph Allen (jhallen@world.std.com) to see if > he got it to work. > > Evan But with this method you can't configure your PCI-Device bevor the host didn't boot the fpga. Is it possible to reconfigure one PCI-Device? Do I have problems with Win NT? Which drivers do I need?? Thanks to all! EckhardArticle: 27452
Hi! I'm looking for Virtex prototyping boards with a PCI-interface. The PCI-interface shold be controlled by a seperate chip, so that the FPGA does not need to provide the functionality for the PCI-Bus. Is there anybody who has some (good or bad) experiences with such a board and can give me any hints which board I should buy? As I don't know much about PCI-programming I would appreciate a board that is shipped with ready-to-use PCI-drivers for Linux and/or Windows and some examples how to use them. Thanks in advance, Christian WernerArticle: 27453
Christian Werner wrote: > > Hi! > > I'm looking for Virtex prototyping boards with a PCI-interface. > > The PCI-interface shold be controlled by a seperate chip, so that the FPGA > does not need to provide the functionality for the PCI-Bus. > > Is there anybody who has some (good or bad) experiences with such a board > and can give me any hints which board I should buy? > > As I don't know much about PCI-programming I would appreciate a board > that is shipped with ready-to-use PCI-drivers for Linux and/or Windows and > some examples how to use them. There are 4 suppliers (as far as I can tell) for this type of board, here are their website: http://www.alphadata.co.uk/dsheet/adc-rc1000.html http://www.annapmicro.com/ http://www.nallatech.com/products/index.htm http://www.x2e.de/ (Spyder X2) That's the one I have, It seems that these type of board are more targeted at fast prototyping rather than for doing a reconfigurable accelerator, the design is fine, but it reaaly lack a on board programable clock generator. PCI performance are not great (at most 40Mb/sec on slave DMA) but as far as i heard it is not much worse than for wildforce and co. BTW, If someone have experience with one of the listed board above, I'd be happy to hear from him (especially in regards of the software driver flexibilty and PCI performance) Steven > > Thanks in advance, > > Christian WernerArticle: 27454
On Wed, 22 Nov 2000 07:35:35 -0800, "Walter Haas" <walter_haas@pmc-sierra.com> wrote: >Hi Magnus, > >Yes, skew is the difference between the arrival time of two signals, but again, it's the same clock net with the same driver that's have the skew problem. How can one part of one net have a maximum Tpd and another part of that same net have a minimum? Enough so that it makes a big difference, like in the ns range? > >And yes, on chip routing is slow. It's all capacitive loading of the entire net plus the gate of the receiver(s). That is not in dispute at all. > >What I'm saying is that skew on a signal net that is driven by a single driver can only come from the differences in propagation delay, or buffering elements in between. If all elements get their clock from a single clock net, how can there be skew in the range they are reporting? > >I hope this makes it a little clearer... > >Cheers, > >Wally I think you are missing the fact that you need to look at this as a transmission line. The clock signal doesn't arrive at all the inputs at the same time. If you are closer to the source you see the clock earlier. Muzaffer http://www.dspia.comArticle: 27455
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walter haas wrote: /* They are both clocked by the exact same clock net, but a clock net that is on local routing. */ The words "local routing" are the key. Look at the design in the FPGA Editor, and see exactly how that routing is achieved. Your clock might be going through all sorts of stuff (LUTs as pass-throughs, etc) that contribute to delay on the clock net and hence skew. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 27457
In article <ee6ec96.-1@WebX.sUN8CHnE>, "walter haas" <walter_haas@pmc-sierra.com> wrote: > Hi Everybody, > (snip) > > I have a design where I have two synchronous elements, a register feeding a RAM. They are both clocked by the exact same clock net, but a clock net that is on local routing. The Xilinx tools report that I have skew between the data signal and the clock signal between those two elements. > (snip) It sounds to me like you are not using global clock resources for this clock. If this is true, then you will have clock skew problems. Routing of non-global signals is via horizontal and vertical metal lines, which are connected via buffers and switches. If you are not using a global clock, then two adjacent logic blocks can have the clocks routed to them in very different ways, depending on how the local routing resources are allocated. You *must* use global clock resources for synchronous logic in FPGAs. If you don't then you are asking for all kinds of trouble. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27458
Hi Muzaffer, Yes, if Xilinx did model these lines as transmission lines, then the closer element would see the clock faster. However, a point I neglected to mention which I should have, is that Xilinx also told me they do not differentiate between capacitive delay and propagation delay, which would imply not using transmission lines. Quoting from Norman Johnson, you can lump the parameters of a circuit (as in, ignore transmission line effects) if the length of the net divided by 6 is larger than the rise time (unloaded) of the buffer divided by the speed of electrical material. The speed for FR4 is 180ps/inch. So, with the rise time being ~1ns (all I could find in the databook), using double the electrical speed of FR4 to 360ps/inch, gives me a lumped parameter cut-off of 1/2 an inch. With no trace being 1/2 inch, there is no effective transmission line. All the capacitance in lumped together. So, I'm back to my original problem. And Andy, in regards to the editor, looking at the FPGA editor, the net does not go through any buffering elements of any kind, just through the routing matrix. But, I am getting good discussion on this. Cheers. WallyArticle: 27459
On Wed, 22 Nov 2000 16:45:07 +0100, Eckhard Hammer <Eckhard.Hammer@rsd.rsd.de> wrote: >But with this method you can't configure your PCI-Device bevor the host >didn't boot the fpga. Is it possible to reconfigure one PCI-Device? Do I >have problems with Win NT? Which drivers do I need?? > >Thanks to all! >Eckhard Don't know about NT - try asking on comp.os.ms-windows.programmer.nt.kernel-mode EvanArticle: 27460
On Wed, 22 Nov 2000 07:35:35 -0800, "Walter Haas" <walter_haas@pmc-sierra.com> wrote: >Hi Magnus, > >Yes, skew is the difference between the arrival time of two signals, but again, it's the same clock net with the same driver that's have the skew problem. How can one part of one net have a maximum Tpd and another part of that same net have a minimum? Enough so that it makes a big difference, like in the ns range? > >And yes, on chip routing is slow. It's all capacitive loading of the entire net plus the gate of the receiver(s). That is not in dispute at all. > >What I'm saying is that skew on a signal net that is driven by a single driver can only come from the differences in propagation delay, or buffering elements in between. If all elements get their clock from a single clock net, how can there be skew in the range they are reporting? > >I hope this makes it a little clearer... > >Cheers, > >Wally I'm not sure if I follow your argument, but you seem to be saying that that if points A and B are on the same line, and are driven from point C, then C sees a single lumped capacitance and this is therefore not relevant to the skew calculation. The skew is therefore just a function of the distance between A and B and the speed of the wavefront. If so, this is very simplistic, and it doesn't work. I believe the original Neocad software did this, but certainly Lucent, and almost certainly Xilinx, have much more sophisticated distributed element models now. You could easily get real skews of several nanoseconds across a device, even though the distance between the points is minimal. BTW, of all the 'experts' I've come across, 'signal integrity experts' are easily the least expert... EvanArticle: 27461
Go to http://www.optimagic.com/ and click on boards. You will find plenty of choices. -- Zhen "Christian Werner" <cwerner@informatik.hu-berlin.de> wrote in message news:Pine.GSO.4.02.10011221458100.4926-100000@rock... > Hi! > > I'm looking for Virtex prototyping boards with a PCI-interface. > > The PCI-interface shold be controlled by a seperate chip, so that the FPGA > does not need to provide the functionality for the PCI-Bus. > > Is there anybody who has some (good or bad) experiences with such a board > and can give me any hints which board I should buy? > > As I don't know much about PCI-programming I would appreciate a board > that is shipped with ready-to-use PCI-drivers for Linux and/or Windows and > some examples how to use them. > > Thanks in advance, > > Christian Werner >Article: 27462
Jurjen Boss wrote:
> Hi,
>
> We want to implement a Xilinx Spartan-II FPGA, type XC2S50, in our
> (excisting) application. I'm trying to estimate the current supply of this
> device by using the datasheets ("Spartan-II 2.5V FPGA Family: DC and
> Switching Charateristics"). From this datasheet I get the following
> information:
> - Iccintq = 50mA; (supply current internal part)
> - Iccoq = 2mA; (supply current I/O-part)
> - Iccpo=500mA; (ramp rate 2ms)
>
> Does this FPGA needs so much current at power-up? How can this ramp rate be
> adjusted? I just can't imagine that this FPGA needs 500mA at power-up. I
> thought these devices where low-power!?! Is there some information available
> on this subject?
>
> Regards,
>
> Jurjen
If you consider that the device is being programmed very rapidly the 500mA is
quite reasonable. There are millions of CMOS gates being turned on and off at
once so 500mA is quite reasonable. More to the point... They do indeed require
a high current a programming. That is why Xilinx says so. You had better
design for it or you will be sorry. Note that this is a transient state and
thus the total energy (V*I* time product) required is quite small. After
programming they are much like any other CMOS device. namely ... Fast clock
speed means high power. Zero clock speed means very low power. Obviously all
sections of the device do not clock at the same rate so you take a summation
over the whole device and integrate over time.
Article: 27463In article <ee6ec96.5@WebX.sUN8CHnE>, "Walter Haas" <walter_haas@pmc-sierra.com> wrote: > Hi Muzaffer, > (snip) > > And Andy, in regards to the editor, looking at the FPGA editor, the net does not go through any buffering elements of any kind, just through the routing matrix. > (snip) The point Andy and I are trying to make is that local routing resources are not designed for delivering low-skew clocks. The routing matrix includes active elements (switches and buffers) that appear only as route matrix intersections in FPGA editor. Only the global clock routing resources provide the balanced buffer delays and net propagation delays needed for low skew clock routing. I have had to fix designs for companies where engineers used local routing resources for synchronous clocks. These designs had symptoms like temperature and lot dependent failures. Please trust me when I tell you that forcing synchronous clocks through local routing resources is a *bad* idea. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27464
"Walter Haas" <walter_haas@pmc-sierra.com> writes: > However, a point I neglected to mention which I should have, is that > Xilinx also told me they do not differentiate between capacitive > delay and propagation delay, which would imply not using > transmission lines. What do you mean? I don't think they model the capicatance and the length separately, but instead the measure the actual time througha conductor, and from that you either calculate an "effective Er" or an "effective capacitance" or an "effective lngth", if you want. But what is interesting is the Tpd, not why it is there. Surely, they have more intricate models than this, but that's just what they are, models. > Quoting from Norman Johnson, you can lump the parameters of a > circuit (as in, ignore transmission line effects) if the length of > the net divided by 6 is larger than the rise time (unloaded) of the > buffer divided by the speed of electrical material. The speed for > FR4 is 180ps/inch. Would that be Howard Johnson? If you have the chance to attend one of his classes, try to! Your quote doesn't sound right: The length of the net multiplied by speed gives you the delay. That delay should be less than 1/6 of the rise time. Have a look at http://www.sigcon.com/news/3_18.htm I do not understand why you have the speed for FR4. Surely, the substrate is of silicon, and not FR4. There might be FR4 in the BGA, but that's outside the die. The speed of the electrcial material is, in this case the Tpd of the net/divided by the length of it. If you have the Tpd of the net in the FPGA at 2ns (either due to distributed cap, length or Er), it is not likely that you can use any lumped model. Say the driver has a (linear) Tr of 1ns. Also say that the receiver have a threshold of 50 %. If you place one receiver halfway (no stub) and the other in the end, there is no way you get the skew less than 1 ns. In fact, add to that 20% variation of speed for the line between receivers, and then add 50% of Tr for different thresholds at the receivers... It all adds up. Now, if you route from driver to he recievers completely different way, you could end up with much more than that. I have even heard people mumble about transmission line effects on chip (over/undershoot/reflection etc). > And Andy, in regards to the editor, looking at the FPGA editor, the > net does not go through any buffering elements of any kind, just > through the routing matrix. Just out of curiosity, are the recievers close to eachother? Are they routed different ways? Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 27465
Magnus Homann wrote: > > > I would guess that they take the max Tpd to the receiver as skew. Not > many FPGA (any?) manufacturer have implemented min. Tpd calculation. A > min Tpd of 25% of Max, would still get you 1.50 ns skew. Skew is diff > between max delay to one element and min delay to the other. If you > have a min of 0, skew equals max delay. > This analysis is way too pessimistic. The difference between Tpd(max) & Tpd(min) is over all variations of temp, voltage, silicon. However clock skew analysis applies to a specific device where o the voltage is constant o the temp may vary and there may be localised hot spots but not not over the range of a few CLBs - assuming in the situation described here the reg & RAM are placed reasonably close together. o The silicon doping levels will be constant. Therefore all the internal devices will be at or near the same point in their min-max range. [Walter you might try to see if this is allowed for in the Xilinx skew calculation by setting the Temp & Voltage derate parameters in the UCF/PCF].> "The way in which we implement and characterize our internal routing is proprietary. What I can tell you is this- believe what the tool tells you: > > there is skew between those synchronous elements. You may infer what you'd > > like about the meaning of that (existance of buffers and other such elements > > that would cause skew / type of material we use to implement routing), > > but the fact remains- you have a race condition." > > > > Umm...OK. Anybody have any ideas on what this proprietary way is? Or, is it just a way to tell me to be quiet and just use the tools as is? > That's just a warning that Xilinx are about to take out a patent on Physics. > > It's a way telling you to stick to the specified interface, so that > Xilinx can redesign internally as needed. Could be said in a nicer > way, but i basically agree with him/her. > Taken to it conclusion this argument means we should all go back to pushing the big friendly green GUI button and forget about trying to make the tools do what we want. Don't forget its not Xilinx that has to get products out the door with these *&~$!!## devices, its us.Article: 27466
"Walter Haas" <walter_haas@pmc-sierra.com> writes: >Yes, if Xilinx did model these lines as transmission lines, >then the closer element would see the clock faster. >However, a point I neglected to mention which I should have, >is that Xilinx also told me they do not differentiate between >capacitive delay and propagation delay, which would imply not >using transmission lines. >Quoting from Norman Johnson, you can lump the parameters of a >circuit (as in, ignore transmission line effects) if the length >of the net divided by 6 is larger than the rise time (unloaded) >of the buffer divided by the speed of electrical material. >The speed for FR4 is 180ps/inch. >So, with the rise time being ~1ns (all I could find in the databook), >using double the electrical speed of FR4 to 360ps/inch, gives me a >lumped parameter cut-off of 1/2 an inch. With no trace being 1/2 inch, >there is no effective transmission line. All the capacitance in lumped >together. So, I'm back to my original problem. Someone else probably knows the details better, but as I understand it the lumped capacitance model didn't work as of about 0.3 micron technology. The problem is that the resistance of the lines is much more significant than the source impedance of the driver. (The metal gets thinner and narowwer, so the resistance increases with the square of the scale factor. Capacitance decreases linearly.) Simple transmission line theory assumes no loss, so that doesn't help much here. For PC boards, the wire resistance is small enough that simple transmission line theory works. That is, use only the capacitance and inductance terms. In this case, you need the resistive and inductive terms, and it is more like a diffusion equation than a wave equation. Note also that the dielectric constant of Si is around 10. -- glenArticle: 27467
Thanks for the replies for my previous posting. They are really helpful. Here are more questions about general aspects of configurable computing. I think most FPGA designers today go for the HDL synthesis and automatic placement and routing approach. And in this process, designers would try to include the hard macros like Xilinx cores in their design to improve the overall performance. However, one of my reviewers believed most designers for commercial products would probably still go for manual placement and routing. Secondly, I state that configurable computing shortens the development cycle by comparison to ASIC design. However, one of my reviewers argue that ASIC design can also be done in a comparable time frame through design automation. I wonder if that is really the case. Please tell me your opinions on these two issues and I would be very grateful for you answers. Thanks! -- Zhen LuoArticle: 27468
In article <3A1C49C8.DBCFFD61@algor.co.uk>, Rick Filipkiewicz <rick@algor.co.uk> wrote: (snip) > > This analysis is way too pessimistic. The difference between Tpd(max) & Tpd(min) is over all variations of temp, voltage, silicon. However clock skew > analysis applies to a specific device where > > o the voltage is constant > > o the temp may vary and there may be localised hot spots but not not over the range of a few CLBs - assuming in the situation described here the reg & > RAM are placed reasonably close together. > > o The silicon doping levels will be constant. > > Therefore all the internal devices will be at or near the same point in their min-max range. (snip) This is only partially true. I have seen repeatable FPGA FF hold-time failures at ambient temperature extremes, and in different FPGA lots, in designs where clocks were routed using local resources. Things like counters getting stuck, and shift registers scrambling bits. I'm not talking theoretical analysis here, I'm talking about actual observed failure modes and effects. I'll say this one more time: routing clocks using local routing resources is a *bad* idea. If you do this, it will come back to haunt you. Unfortunately, many engineers that do this don't understand the problem they are introducing, and are then at a loss to explain why the design is flaky in the field. For example, a system that failed to respond to a fire sensor input, but only when the system got hot... -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27469
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Greetings, I've been wondering for some time now what the different "speed grade" versions really mean. I'll compile a design for a XC4005XL-3C and it may run as fast as 80MHz. From some semi-ambiguous graphs on Xilinx's site, 3C is only supposed to do about 40MHz... Pardon for the lame question, I just cant find any clear definition.Article: 27471
Hi, there Currently I'm doing a design with VirtexE, but have problem to achieve Tco performance: AD is a bidi bus with oe control AD <= D_OUT when OE = '1' else "ZZZZ"; here D_OUT is a registered internal signal, and also used somewhere else in the design. When I run it in Foundation ISE 3.1i + SP5, the SW keeps implement the tristate with internal tristate bus(BUFT), which will add more delay, and the Tco is as long as 10ns. Is there anyway to disable the internal tristate in the SW? How to? Thanks FrankArticle: 27472
Rick Filipkiewicz <rick@algor.co.uk> writes: > This analysis is way too pessimistic. The difference between > Tpd(max) & Tpd(min) is over all variations of temp, voltage, > silicon. However clock skew analysis applies to a specific device > where > > o the voltage is constant > > o the temp may vary and there may be localised hot spots but not not over the range of a few CLBs - assuming in the situation described here the reg & > RAM are placed reasonably close together. > > o The silicon doping levels will be constant. You are of course right. In another post I noted that all FPGA manufacturers considers max Tpd only. I also said that I would be happy if they even managed to characterize the ouput hold of an I/O. After they have have done that, I would also be interested in skew on-chip. > > It's a way telling you to stick to the specified interface, so that > > Xilinx can redesign internally as needed. Could be said in a nicer > > way, but i basically agree with him/her. > Taken to it conclusion this argument means we should all go back to > pushing the big friendly green GUI button and forget about trying to > make the tools do what we want. No. If you want to do a worst case design, I recommend always stick to the public spec. That goes for all digital design. Noit many digital devices have publicied there skew, I've had this problem with all sorts of devices. "Skew? Zero, of course!" Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 27473
hello everybody,
i am working with XILINX foundation series v1.5(students editionn). in my design work, when i synthesize one of my macro (schematic type) it is giving right pins for Virtex family but does not work for spartan family. can any one help to me.
Article: 27474hi, all. I am plowing a lieteratural survey on fpga applications. I found that there are six major potential fields: communication &networks, consumer, industry, automotive, data processing and military& aerospace. but I can not find the details of them and some examples. anybody can give me some valuable reference? cheers Jianyong.Niu
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