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Hi All, I am looking for some in depth information about LUTS and edif file specs. I know what luts are, and what they can be used for, but is there any information on what equations to use when, and what init strings to provide. I read an article which described some of this by a truth table, but i would much like a xilinx documentation on the technical part of a lut. About the edif specs. I would like to know how to write a valid edif file structure. Do you know of any information about this, except for the $300,00 specs itself. Richard -- Quest Innovations tel: +31 (0) 227 604046 http://www.quest-innovations.comArticle: 27151
Hul Tytus wrote: > > comp.arch.fpga > manchester decoder > Anyone know of a text that shows a decoder of Manchester encoded data? > If so, leaving a note here or sending one to me via email would be much > appreciated. > Hul htytus@iglou.com Some time ago I received the message below: > > > A Manchester encoder is trivial, essentially an XOR. > A Manchester decoder is described in the Xilinx XCell magazine in 1995. > The design uses only three XC3000 or XC4000 or Spartan CLBs. > > http://www.xilinx.com/xcell/xl17/xl17-30.pdf > > Peter Alfke, Xilinx Applications -- Eduardo Augusto Bezerra Space Science Centre School of Engineering and Information Technology The University of Sussex Brighton, BN1 9QT England, UK Phones: +44 (0)1273 877086 or +44 (0)700 5568783 Fax: +44 (0)1273 678399 EIT II, room 4B11 *** UK *** mailto:E.A.Bezerra@sussex.ac.uk - http://www.sussex.ac.uk/~tapu9 Space Group: http://www.sussex.ac.uk/engg/research_groups/space/ ABEP: http://welcome.to/Abep *** Brasil *** mailto:eduardob@inf.pucrs.br - http://www.inf.pucrs.br/~eduardob GAPH: http://www.inf.pucrs.br/~gaph *** ACM *** mailto:eduardob@acm.orgArticle: 27152
Richard Meester wrote: > > Hi All, > > I am looking for some in depth information about LUTS and edif file > specs. > > I know what luts are, and what they can be used for, but is there any > information on what equations to use when, and what init strings to > provide. I read an article which described some of this by a truth > table, but i would much like a xilinx documentation on the technical > part of a lut. > > About the edif specs. I would like to know how to write a valid edif > file structure. Do you know of any information about this, except for > the $300,00 specs itself. The edif grammar and syntax is fairly simple (lisp like). The best way to learn about it is to use a synthesizer and look at the generated edif files, it should help you to understand its structure. Otherwise, i've seen some free-edif parser file ssomewhere on the web and on www.jhdl.org Steven > > Richard > > -- > Quest Innovations > tel: +31 (0) 227 604046 > http://www.quest-innovations.comArticle: 27153
I've received similar error when service pack 4 for Foundation 3.1i is installed. Damir <jaypt123@my-deja.com> wrote in message news:8uipql$esh$1@nnrp1.deja.com... > I downloaded Webpack release version Webpack 3.2WP3.x from Xilinx. > The installation was OK. However, when I run the software there is > error as follows. > > ------------------------------------------------------------------- > > Starting: 'ngdbuild -f ngdbuild.rsp ' > > > Release WebPACK 3.2WP3.x - ngdbuild D.22 > Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. > > Command Line: ngdbuild -dd __ngo -nt timestamp -sd > D:\Xilinx_WebPACK\Spartan2\data\map -p 2S200-FG456-5 stopwatch.edn > stopwatch.ngd > > Launcher: "stopwatch.ngo" is up to date. > Reading NGO file "D:/Xilinx/watchvhd/__ngo/stopwatch.ngo" ... > Reading component libraries for design expansion... > > Checking timing specifications ... > > Checking expanded design ... > > The XML Parser environment is incorrectly set up, preventing it from > finding its text transcoding files. Normally these will be located > via the ICU_DATA environment variable, or located relative to the > XML4C2 DLL (or SharedLib.) Please check your installation > EXEWRAP detected a return code of '9999' from program 'ngdbuild' > > Done: failed with exit code: 9999. > ------------------------------------------------------------ > > Since this is a free software, I don't know if Xilinx is willing > to answer any question. For now, it is a useless software. > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 27154
What I have done in a recent design is: A Spartan-LCA is connected to its serial configuration prom, which in this case is an ATMEL-product, additionally to a byte wide Flashprom, which stores various error correction polynomials to support the original task of the LCA (a communication processor for special protocoll implementations), and furthermore to an 16-bit flash which contains the programm code for an 80186-mikroprozessor. These three different devices are programmed via JTAG-port using a very efficient method: First the LCA is JTAG-programmed with a special logic which implements programming interfaces to the devices. From then on the JTAG pins are used to implement my own serial interface to access one of the three devices for programm and verify. Sure, one extra pin of the LCA must be sacrifieced for a wire-ored CCLK, and the 16-Bit-Prom must be isolated from the Mikroprozessor. Every programming is done via parallelport of a standard PC. I write this note to encourage using the JTAG port for LCA programming. Hope it helps. Sorry for my "net english" (= not english)Article: 27155
Ty Ray, I will think I will use an external pull-up.<br>JonasArticle: 27156
Hi, I am converting some older designs from Xilinx XC4000 to Spartan2. I found that a simple loadable counter like the CC8CLE fits in a XC4000 within 4 CLBs. The Spartan2 implementation uses also 4 CLBs, but these CLB have double the logic density of the older XC4000 CLBs. I thought Spartan2 will fit that counter within 2CLBs (=4Slices) So what is the problem with the Spartan2 CLBs? peterArticle: 27157
Hi, Do anyone knows a page with an applet for drawing a sorting network based on the merge methodology from Batcher. Thanks -- __________________________________ qfwfq Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27158
Hello,
We've just upgarded to synopsys VSS 2000.05 and Xilinx M3.1, and some of
my design whiwh used to simulate fine now generate an error during
vhdlsim. Specificaly I use a behavioral model for the async_fifo core in
the Coregen Library and this gives me the following error message (note
that I did not forget to recompile all the library source file after
upgrading)
vhdlsim,106: The following error was encountered while elaborating
/INFIFO/FIFO/CONTROL/WRSYNC_DCOUNT_BLK/GEN_WRSYNC_DCOUNT/WRSYNC_DATA_COUNT_SUB/COMPONENT:
**Error: vhdlsim,4:
Array index range length mismatch.
The configuration I use for my design seems consistent to me (and was
actually generated by the
coregen tool itself). What I don't understand is that synopsys now find
an error in xilinxcorelib vhdl
source code while It didn't in previous version.
for all : pci2usr use entity XilinxCoreLib.async_fifo_v1_0(behavioral)
generic map(
c_wr_err_low => 0,
c_has_rd_count => 0,
c_has_rd_ack => 0,
c_wr_ack_low => 0,
c_has_wr_count => 1,
c_has_wr_ack => 0,
c_has_almost_full => 0,
c_has_almost_empty => 1,
c_wr_count_width => 8,
c_rd_count_width => 0,
c_has_rd_err => 1,
c_data_width => 32,
c_has_wr_err => 1,
c_rd_ack_low => 0,
c_rd_err_low => 0,
c_fifo_depth => 255,
c_enable_rlocs => 1,
c_use_blockmem => 1);
end for;
Has someone faced the same problem ?
Steven
Article: 27159The 'problem' is the architecture is different. The Spartan2/virtex has the carry chain after the LUT. Your logic is putting a mux after the carry chain, which is making it two levels of logic deep. If this is synthesized, you need to be very careful about the coding style to make the synthesizer do the right thing. You can do a loadable counter in the S2/V architecture but the synthesis tools don't always infer it. Peter Lang wrote: > > Hi, > I am converting some older designs from Xilinx XC4000 to Spartan2. > I found that a simple loadable counter like the CC8CLE fits in a > XC4000 within 4 CLBs. The Spartan2 implementation uses also > 4 CLBs, but these CLB have double the logic density of the older > XC4000 CLBs. > I thought Spartan2 will fit that counter within 2CLBs (=4Slices) > So what is the problem with the Spartan2 CLBs? > peter -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27160
Hi all I tried to install the WebPack but I can't run it because it complains about a missing dll (libNgd.dll) Taht's quite strange for a program that's supposed to be "standalone"... -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 00 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 27161
I guess I should've qualified that this method of learning VHDL would
not suit MY particular learning style. Sometimes I accidently speak in
absolutes. I'll try to find the names of the books I referred to.
I would offer the possibility that VHDL differs from the assembly to C
progression in that VHDL supports very different levels of abstraction
in the language itself. VHDL is a full-blown programming language of
which synthesizable VHDL is mearly a subset. It seems that a natural
progression might be for synthesizable VHDL to include more of the
capabilities of VHDL. This would allow the tools to be maintained as
well as the wealth of IP already developed in VHDL.
<end idle thoughts>
Tim
In article
<826B0204FE58C885.E1341890FDB47D09.0AD952EE96FACC62@lp.airnews.net>,
"Peter Dennett" <pdennett@padsoft.com> wrote:
>
> <timjeno@my-deja.com> wrote in message news:8ue9t6
$nni$1@nnrp1.deja.com...
> > I don't know of any such product. I would question whether such an
> > approach would be the best way to get your "feet wet" anyway. The
code
> > produced by such a process would unlikely be clean and would
therefore
> > offer little help as an educational tool. I can almost gaurantee it
> > won't do everything you want without tweaking which will ultimately
> > involve learning VHDL.
>
> Basically I agree with all of what you said but not with the
conclusion.
> I do expect "ratty VHDL" to be generated, I do expect to have to learn
> why it does not do what I expect. But I do think it seems like a good
> way to learn VHDL. It's also how I expect to be programming FPGA
> devices in the future.
>
> I see VHDL and schematic capture is the equivalent to assembly
> language. Longer ago then I like to think I learned programming
> using assemblers. I understand what is happening below the skins.
> I seldom use assembler any more and when I do I normally start
> by coding it in C and looking at its output as a starting point.
>
> I've moved on to systems that may be a bit sloppy in the details but
> they handle them so I don't have to. I'd like to apply the same
> concept to FPGAs.
>
> > Besides this, there's a good chance that only a
> > subset of C would be supported, perhaps a "synthesizable C". This
> > would involve a learning curve for the C-side also.
>
> Yep, expected.
>
> > Perhaps a book on VHDL targetted to programmers would work best? I
> > haven't read any but I could probably at least find names.
>
> I'd love to hear of one. Those authors in the audience should take
> heed. The next source of FPGA developers will come from the
> software side. The don't want to know logic design they want to
> know algorythm implementation.
>
> > Good luck with whatever you decide to do!
>
> Thanks, and thank you for the input.
>
> > p.s. - If it helps, I went from a programming background to VHDL.
It
> > requires a conceptual shift but the language is simple. It's
similar
> > to going from C to object oriented C++. The syntax jump is easy but
> > the concepts are very different. I learned VHDL from VHDL
tutorials.
> > They're all over the place.
>
> I've been cruising the net for awhile now looking that the tutorials,
> there indeed a lot and many are high quality. I have some books
> on order and have been working on getting an Altera UP1 board.
> I'll be heading down a comparable path.
>
> --
> Peter Dennett Email: pdennett@padsoft.com
> 61 Harbor Lane Web: www.padsoft.com
> Kemah, TX 77565 Web: www.boatbrains.com
> Voice: 281 334 3800 Cell: 713 899 6100 Fax: 281 521 1032
>
>
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 27162Richard Meester wrote: > > Hi All, > > I am looking for some in depth information about LUTS and edif file > specs. > > I know what luts are, and what they can be used for, but is there any > information on what equations to use when, and what init strings to > provide. I read an article which described some of this by a truth > table, but i would much like a xilinx documentation on the technical > part of a lut. > > About the edif specs. I would like to know how to write a valid edif > file structure. Do you know of any information about this, except for > the $300,00 specs itself. I've done a fair bit of work involving LUTs and EDIF. I'm not entirely sure what you mean in the second paragraph, in terms of equations and init strings. The init string for a LUT in a Xilinx piece is simply the 1 bit wide 16 entry look-up table. Is this what you mean? I sussed how to write EDIF by looking at the output of synthesis tools, its all ASCII and quite humanly readable. To check the syntax of my handwritten EDIF, I used Active VHDL which will tell you the line number of your first error and not much else. But its about as good as it gets. I believe Brad Hutchings and the people at BYU have an EDIF parser written in Java which is free. This may be useful for you. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder ---------------------------------------------------------------------Article: 27163
Peter Lang wrote: > > Hi, > I am converting some older designs from Xilinx XC4000 to Spartan2. > I found that a simple loadable counter like the CC8CLE fits in a > XC4000 within 4 CLBs. The Spartan2 implementation uses also > 4 CLBs, but these CLB have double the logic density of the older > XC4000 CLBs. > I thought Spartan2 will fit that counter within 2CLBs (=4Slices) > So what is the problem with the Spartan2 CLBs? > peter Its the carry chain. You may have used 4 CLBs but you have only used one slice within each of those CLBs. The other slices are still there to be used by the rest of your circuit. The carry chains in Spartan 2 cannot swap slices, so once your arithmetic structure starts in slice 0, it will just grow vertically, it cannot jump to slice 1 and vice versa. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder ---------------------------------------------------------------------Article: 27164
Hi When I tried to synthesis
the errors are
the sequential mapping has detected that the cell "/ver1-
Optimized/Counter_r
eg<i?'
uses both the asynchronous 'set' and 'clear' pins
Can anyone tell me how to deal with that?
What is the difference of 'set' and 'clear' pins
Thank you very very much!
Here is my VHDL program
COUNTER_Gen: process
(CLK,COUNTER,RESET,IFREQ,IDEADTIME,IDUTYRATIO,REALCONTROL,REALPHASE,IPH
ASE)
variable UpOrDown : STD_LOGIC; -- Go Up or Go Down
-- When UpOrDown = '1',
coun
ter goes up
-- When UpOrDown = '0',
coun
ter goes down
variable CHANGEC: STD_LOGIC; ---CONTROL signal changes
variable CHANGEP: STD_LOGIC; ---PHASE signal changes
begin
if RESET= '1' then
-- IIPHASE:=CONV_INTEGER(UNSIGNED(PHASE));
COUNTER <= IPHASE-1;
if IPHASE = 0 then
UpOrDown := '0';
else
UpOrDown:='1';
end if;
-- elsif REALCONTROL/=LASTCONTROL then
-- CHANGEC:='1';
-- elsif REALPHASE/=LASTPHASE then
-- CHANGEP:='1';
elsif CLK'event and CLK='1' then
-- /\ /\ /\
-- / \ / \ / \
-- / \ / \ / \
-----/------\--/------\--/------\--
-- / \/ \/ \
--if REALCONTROL='0' then --Synchronous WAVE
case REALCONTROL is
when '0' =>
if COUNTER= IFREQ then
UpOrDown :='1';
elsif COUNTER = 0 then
UpOrDown:='0';
end if;
if UpOrDown='0' then --UpOrDowm='0' Waveform goes up
--
UpOrDow
m='1' Waveform goes down
COUNTER <= COUNTER + 1; --WAVE goes
up
else
COUNTER <= COUNTER - 1;
end if;
-- /| /| /| /|
-- / | / | / | / |
-- / | / | / | / |
-----/---|-/---|-/---|-/---|--
-- / |/ |/ |/ |
when '1'=>
COUNTER <= COUNTER + 1;
if COUNTER = IFREQ then
COUNTER <= 0;
end if;
when others =>
end case;
if CHANGEC='1' and COUNTER=IFREQ and REALCONTROL='0' then
COUNTER<=0;
UpOrDown :='1';
CHANGEC:='0';
end if;
if CHANGEP='1' and ((COUNTER=IFREQ and REALCONTROL='1')
or (CO
UNTER=0
and REALCONTROL='0')) then
if REALCONTROL='0' then
if IPHASE>IFREQ and IPHASE<2*IFREQ then
COUNTER<=2*IFREQ-IPHASE;
UpOrDown:='1';
elsif IPHASE>0 and IPHASE<IFREQ then
COUNTER<=IPHASE;
UpOrDown :='0';
end if;
else
if IPHASE>0 and IPHASE<IFREQ then
COUNTER<=IPHASE;
UpOrDown:='0';
end if;
end if;
CHANGEP:='0';
end if;
end if;
end process COUNTER_Gen;
--
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 27165By Xilinx Foundation 3.li At first create a simple VHDL project then synthesis, if successfully synthesis this click schematic menu, select Generate schematic from netlist but it shows " Check Netlist File(types 0)" while gives me a blank schematic What is wrong?:( Thank you very much! Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27166
Eric Smith wrote in message ... >haydenso@my-deja.com writes: >> the posting on this group has been talking about how a Spartan-II >> (Virtex-E) communicates with 5V TTL level or 5V CMOS level devices. The >> bad news is it is "ok" to talk to TTL but not CMOS. So in my situation, >> because I am just plugging my card to a PC, I will have no clue what the >> other end(s) are (namly, the ISA controller on MB, or other ISA devices >> sharing the bus)... >snip> >However, the bigger problem to be considered is that proper bus drive >requires a lot of mA. You may want to use an external bus transceiver >anyhow. 74FCT245 and the like should work fine. FCT devices are very good for this in that they've got plenty of drive, have CMOS dissipation and 100mV of hysteresis on their receivers. Consider also using "old-fashioned" 74LS245 transceivers here. Being bipolar TTL they have higher dissipation than the FCTs, but they do have hysteresis on the receivers and because they're an older technology their edge rates are slower, leading to fewer reflections on the non-impedance-controlled ISA bus. Given the slow speed of ISA transactions LS-TTL speeds are adequate.Article: 27167
The Spartan-II (Virtex-family) carry logic is different from that of the XC4000 family. It is possible to implement a CC8CLE in 4 slices (4 half CLBs), but as I wrote just yesterday at www.fpgacpu.org, the CC8CLE implementation (F2.1i library) uses twice as many slices as necessary. I suspect your favorite synthesis product also requires 8 slices. As I wrote yesterday, you can implement o = add ? a + b : a o = add ? a + b : c o = add ? a + b : a ~& b <<and other even cooler things>> in one logic cell (half-slice) per bit if you know the trick (using MULT_AND together with MUXCY and XORCY). The Virtex library CC8CLE implementor (and my synthesis vendor's technology mapper) are apparently unaware of the technique. Jan Gray, Gray Research LLC FPGA CPU News: www.fpgacpu.orgArticle: 27168
Steve Fair wrote: > Peter - > > Further clarification: > > If all the clock DELAYS into the core match exactly then > internal fmax is purely based on the > internal data delay (regardless of how big or small the clock delay is). > The internal fmax "robber" is > clock SKEW, not clock delay. So DLL/PLL's do help remove SKEW, but not > dramatically > from what I've seen in designs I've run (kudo's to the clock tree > designers). But then again, > a few MHz is sometimes a WONDERFUL thing!! It seems like we are sayingthe same thing, just use different language. PLL/DLL can eliminate the clock delay, but cannot affect clock skew. > > > > > > Xilinx DLLs have exactly the same capabilty, we call it "clock mirroring". > You > > can use the FPGA to be your zero-delay clock driver. Considering the > multitude > > of I/O standards supported in Virtex FPGAs, this feature can be quite > handy. > > > Can you move the output clock in .5ns increments?? That's the feature I was > referring to in the altera parts (as well as the 90/180/270 adjustments)?? Virtex has the 90/180/270 option. You can move the clock in absolute time by including internal delays in the feedback loop. Wait for Virtex-II for substantially greater versatility. > > That > goes into the point below about stealing . . . > > Peter - I was more referring to the fact that delaying a clock in a > synchronous > system will help tsu on the part you're talking to (i.e. the SDRAM case), > but > you have to take it back into account. I.e. on a 100 MHz synchronous > system, > if you delay an output clock 2ns, then the part better be able to get the > data > back out in 8ns to line up with the master clock (please allow me to leave > all > the other timings out like hold for simplicity's sake). I should never have > mentioned > the board deskew in the same paragraph as the clock shift / clock delay. My > bad! > Removing skew, good, adding skew, stealing! Thanks for clarifying my > muddled > prose. > > Appreciate your help. > > Steve > We all agree that a PLL/DLL can only only move the clock about. You are still limited by the clock cycle time. But it is sometimes nice to be able to "rob Peter to pay Paul". Greetings Peter AlfkeArticle: 27169
Hi all, This is a known issue normally seen in non-English versions of Windows. There is a solution on this- 10223: simply enter 'parser' in the Answers Database search area. It will tell you to open a support case with Xilinx- and you are supported even if using WebPACK- so that a support engineer here can get you the tactical patch for this problem. Regards, Tim jaypt123@my-deja.com wrote: > I downloaded Webpack release version Webpack 3.2WP3.x from Xilinx. > The installation was OK. However, when I run the software there is > error as follows. > > ------------------------------------------------------------------- > > Starting: 'ngdbuild -f ngdbuild.rsp ' > > Release WebPACK 3.2WP3.x - ngdbuild D.22 > Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. > > Command Line: ngdbuild -dd __ngo -nt timestamp -sd > D:\Xilinx_WebPACK\Spartan2\data\map -p 2S200-FG456-5 stopwatch.edn > stopwatch.ngd > > Launcher: "stopwatch.ngo" is up to date. > Reading NGO file "D:/Xilinx/watchvhd/__ngo/stopwatch.ngo" ... > Reading component libraries for design expansion... > > Checking timing specifications ... > > Checking expanded design ... > > The XML Parser environment is incorrectly set up, preventing it from > finding its text transcoding files. Normally these will be located > via the ICU_DATA environment variable, or located relative to the > XML4C2 DLL (or SharedLib.) Please check your installation > EXEWRAP detected a return code of '9999' from program 'ngdbuild' > > Done: failed with exit code: 9999. > ------------------------------------------------------------ > > Since this is a free software, I don't know if Xilinx is willing > to answer any question. For now, it is a useless software. > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 27170
Ray Andraka wrote: > > It is possible, however I strongly recommend you use an external pullup. The > internal pull ups are weak pull ups sufficient to tie an unconnected pin high. > However when that pin has a trace and loads attached, the pull up value is > really too small to ensure a) that the trace does not act as an antenna and b) > that the open drain output goes back high in a reasonable amount of time. The > high impedance (>100K) of the internal pullup does little to guarantee this. Ray, You're right. My last design used open-drain outputs on two FPGAs to drive a common interrupt request line, and I used a 4.7k external pullup. I don't think I even considered using the internal pullup. I DID use the pullups as weak keepers to keep SDRAM data lines pulled high when the SDRAMs are not being accessed. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 27171
madisonfff@usa.net wrote: > > Hi When I tried to synthesis > > the errors are > > the sequential mapping has detected that the cell "/ver1- > Optimized/Counter_r > > eg<i?' > > uses both the asynchronous 'set' and 'clear' pins > > Can anyone tell me how to deal with that? > > What is the difference of 'set' and 'clear' pins > > Thank you very very much! > > Here is my VHDL program > > COUNTER_Gen: process > > (CLK,COUNTER,RESET,IFREQ,IDEADTIME,IDUTYRATIO,REALCONTROL,REALPHASE,IPH > > ASE) [snip rest of code] You should read the Synopsys HDL guide that comes with FPGA Express and the Xilinx tools -- there's a style guide that will tell you the correct constructs to use in your HDL to get it to do what you want to do. You may also want to pick up one of the books about VHDL for synthesis. Part of your problem is that your sensitivity list should only have a clock and an async reset if you intend to infer flip-flops. Your code is confusing the tool. As for the difference between set and clear pins, when the async reset is asserted, the flop's output is either set (to 1) or cleared (to 0). Since the Xilinx architecture only lets you do one or the other, it complains if you try to do both. -- ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 27172
Robert Sturm wrote: > > Hi all- > > We are currently looking into this issue and will try and implement a remedy as quickly as possible. You can keep us apraised of any immediate issues you might be having by sending us<a href="http://support.xilinx.com/support/asksxc.htm">Feedback</a> or by opening a WebCase with our Technical Support Hotline. Um, duh, how are we supposed to use your Web-based Support stuff if we CAN'T CONNECT TO THE WEB SITE? -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 27173
What is the method for conversion of a POF file for an Altera EPC1441 device into an equivalent POF file for an Altera EPC2, when only the POF file exists? Thanks in advance, DanArticle: 27174
"Geoffrey G. Rochat" <geoff.nospam@nospam.pkworks.com> writes: > Given the slow speed of ISA > transactions LS-TTL speeds are adequate. Depends. If you're trying to do 0-WS I/O, the 74LS is too slow for some of the signals. This is due to poor design of the ISA bus; the time to decode the address and assert the necessary signals is very short. (It's been a few years, so I don't recall the exact details.)
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